gpio-tegra.c 18 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * arch/arm/mach-tegra/gpio.c
  4. *
  5. * Copyright (c) 2010 Google, Inc
  6. * Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved.
  7. *
  8. * Author:
  9. * Erik Gilling <konkers@google.com>
  10. */
  11. #include <linux/err.h>
  12. #include <linux/init.h>
  13. #include <linux/irq.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/io.h>
  16. #include <linux/gpio/driver.h>
  17. #include <linux/of_device.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/module.h>
  20. #include <linux/irqdomain.h>
  21. #include <linux/irqchip/chained_irq.h>
  22. #include <linux/pinctrl/consumer.h>
  23. #include <linux/pm.h>
  24. #define GPIO_BANK(x) ((x) >> 5)
  25. #define GPIO_PORT(x) (((x) >> 3) & 0x3)
  26. #define GPIO_BIT(x) ((x) & 0x7)
  27. #define GPIO_REG(tgi, x) (GPIO_BANK(x) * tgi->soc->bank_stride + \
  28. GPIO_PORT(x) * 4)
  29. #define GPIO_CNF(t, x) (GPIO_REG(t, x) + 0x00)
  30. #define GPIO_OE(t, x) (GPIO_REG(t, x) + 0x10)
  31. #define GPIO_OUT(t, x) (GPIO_REG(t, x) + 0X20)
  32. #define GPIO_IN(t, x) (GPIO_REG(t, x) + 0x30)
  33. #define GPIO_INT_STA(t, x) (GPIO_REG(t, x) + 0x40)
  34. #define GPIO_INT_ENB(t, x) (GPIO_REG(t, x) + 0x50)
  35. #define GPIO_INT_LVL(t, x) (GPIO_REG(t, x) + 0x60)
  36. #define GPIO_INT_CLR(t, x) (GPIO_REG(t, x) + 0x70)
  37. #define GPIO_DBC_CNT(t, x) (GPIO_REG(t, x) + 0xF0)
  38. #define GPIO_MSK_CNF(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x00)
  39. #define GPIO_MSK_OE(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x10)
  40. #define GPIO_MSK_OUT(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0X20)
  41. #define GPIO_MSK_DBC_EN(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x30)
  42. #define GPIO_MSK_INT_STA(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x40)
  43. #define GPIO_MSK_INT_ENB(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x50)
  44. #define GPIO_MSK_INT_LVL(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x60)
  45. #define GPIO_INT_LVL_MASK 0x010101
  46. #define GPIO_INT_LVL_EDGE_RISING 0x000101
  47. #define GPIO_INT_LVL_EDGE_FALLING 0x000100
  48. #define GPIO_INT_LVL_EDGE_BOTH 0x010100
  49. #define GPIO_INT_LVL_LEVEL_HIGH 0x000001
  50. #define GPIO_INT_LVL_LEVEL_LOW 0x000000
  51. struct tegra_gpio_info;
  52. struct tegra_gpio_bank {
  53. unsigned int bank;
  54. unsigned int irq;
  55. spinlock_t lvl_lock[4];
  56. spinlock_t dbc_lock[4]; /* Lock for updating debounce count register */
  57. #ifdef CONFIG_PM_SLEEP
  58. u32 cnf[4];
  59. u32 out[4];
  60. u32 oe[4];
  61. u32 int_enb[4];
  62. u32 int_lvl[4];
  63. u32 wake_enb[4];
  64. u32 dbc_enb[4];
  65. #endif
  66. u32 dbc_cnt[4];
  67. struct tegra_gpio_info *tgi;
  68. };
  69. struct tegra_gpio_soc_config {
  70. bool debounce_supported;
  71. u32 bank_stride;
  72. u32 upper_offset;
  73. };
  74. struct tegra_gpio_info {
  75. struct device *dev;
  76. void __iomem *regs;
  77. struct irq_domain *irq_domain;
  78. struct tegra_gpio_bank *bank_info;
  79. const struct tegra_gpio_soc_config *soc;
  80. struct gpio_chip gc;
  81. struct irq_chip ic;
  82. u32 bank_count;
  83. };
  84. static inline void tegra_gpio_writel(struct tegra_gpio_info *tgi,
  85. u32 val, u32 reg)
  86. {
  87. writel_relaxed(val, tgi->regs + reg);
  88. }
  89. static inline u32 tegra_gpio_readl(struct tegra_gpio_info *tgi, u32 reg)
  90. {
  91. return readl_relaxed(tgi->regs + reg);
  92. }
  93. static unsigned int tegra_gpio_compose(unsigned int bank, unsigned int port,
  94. unsigned int bit)
  95. {
  96. return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
  97. }
  98. static void tegra_gpio_mask_write(struct tegra_gpio_info *tgi, u32 reg,
  99. unsigned int gpio, u32 value)
  100. {
  101. u32 val;
  102. val = 0x100 << GPIO_BIT(gpio);
  103. if (value)
  104. val |= 1 << GPIO_BIT(gpio);
  105. tegra_gpio_writel(tgi, val, reg);
  106. }
  107. static void tegra_gpio_enable(struct tegra_gpio_info *tgi, unsigned int gpio)
  108. {
  109. tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 1);
  110. }
  111. static void tegra_gpio_disable(struct tegra_gpio_info *tgi, unsigned int gpio)
  112. {
  113. tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 0);
  114. }
  115. static int tegra_gpio_request(struct gpio_chip *chip, unsigned int offset)
  116. {
  117. return pinctrl_gpio_request(chip->base + offset);
  118. }
  119. static void tegra_gpio_free(struct gpio_chip *chip, unsigned int offset)
  120. {
  121. struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
  122. pinctrl_gpio_free(chip->base + offset);
  123. tegra_gpio_disable(tgi, offset);
  124. }
  125. static void tegra_gpio_set(struct gpio_chip *chip, unsigned int offset,
  126. int value)
  127. {
  128. struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
  129. tegra_gpio_mask_write(tgi, GPIO_MSK_OUT(tgi, offset), offset, value);
  130. }
  131. static int tegra_gpio_get(struct gpio_chip *chip, unsigned int offset)
  132. {
  133. struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
  134. unsigned int bval = BIT(GPIO_BIT(offset));
  135. /* If gpio is in output mode then read from the out value */
  136. if (tegra_gpio_readl(tgi, GPIO_OE(tgi, offset)) & bval)
  137. return !!(tegra_gpio_readl(tgi, GPIO_OUT(tgi, offset)) & bval);
  138. return !!(tegra_gpio_readl(tgi, GPIO_IN(tgi, offset)) & bval);
  139. }
  140. static int tegra_gpio_direction_input(struct gpio_chip *chip,
  141. unsigned int offset)
  142. {
  143. struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
  144. int ret;
  145. tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 0);
  146. tegra_gpio_enable(tgi, offset);
  147. ret = pinctrl_gpio_direction_input(chip->base + offset);
  148. if (ret < 0)
  149. dev_err(tgi->dev,
  150. "Failed to set pinctrl input direction of GPIO %d: %d",
  151. chip->base + offset, ret);
  152. return ret;
  153. }
  154. static int tegra_gpio_direction_output(struct gpio_chip *chip,
  155. unsigned int offset,
  156. int value)
  157. {
  158. struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
  159. int ret;
  160. tegra_gpio_set(chip, offset, value);
  161. tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 1);
  162. tegra_gpio_enable(tgi, offset);
  163. ret = pinctrl_gpio_direction_output(chip->base + offset);
  164. if (ret < 0)
  165. dev_err(tgi->dev,
  166. "Failed to set pinctrl output direction of GPIO %d: %d",
  167. chip->base + offset, ret);
  168. return ret;
  169. }
  170. static int tegra_gpio_get_direction(struct gpio_chip *chip,
  171. unsigned int offset)
  172. {
  173. struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
  174. u32 pin_mask = BIT(GPIO_BIT(offset));
  175. u32 cnf, oe;
  176. cnf = tegra_gpio_readl(tgi, GPIO_CNF(tgi, offset));
  177. if (!(cnf & pin_mask))
  178. return -EINVAL;
  179. oe = tegra_gpio_readl(tgi, GPIO_OE(tgi, offset));
  180. if (oe & pin_mask)
  181. return GPIO_LINE_DIRECTION_OUT;
  182. return GPIO_LINE_DIRECTION_IN;
  183. }
  184. static int tegra_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset,
  185. unsigned int debounce)
  186. {
  187. struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
  188. struct tegra_gpio_bank *bank = &tgi->bank_info[GPIO_BANK(offset)];
  189. unsigned int debounce_ms = DIV_ROUND_UP(debounce, 1000);
  190. unsigned long flags;
  191. unsigned int port;
  192. if (!debounce_ms) {
  193. tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset),
  194. offset, 0);
  195. return 0;
  196. }
  197. debounce_ms = min(debounce_ms, 255U);
  198. port = GPIO_PORT(offset);
  199. /* There is only one debounce count register per port and hence
  200. * set the maximum of current and requested debounce time.
  201. */
  202. spin_lock_irqsave(&bank->dbc_lock[port], flags);
  203. if (bank->dbc_cnt[port] < debounce_ms) {
  204. tegra_gpio_writel(tgi, debounce_ms, GPIO_DBC_CNT(tgi, offset));
  205. bank->dbc_cnt[port] = debounce_ms;
  206. }
  207. spin_unlock_irqrestore(&bank->dbc_lock[port], flags);
  208. tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset), offset, 1);
  209. return 0;
  210. }
  211. static int tegra_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
  212. unsigned long config)
  213. {
  214. u32 debounce;
  215. if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
  216. return -ENOTSUPP;
  217. debounce = pinconf_to_config_argument(config);
  218. return tegra_gpio_set_debounce(chip, offset, debounce);
  219. }
  220. static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
  221. {
  222. struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
  223. return irq_find_mapping(tgi->irq_domain, offset);
  224. }
  225. static void tegra_gpio_irq_ack(struct irq_data *d)
  226. {
  227. struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
  228. struct tegra_gpio_info *tgi = bank->tgi;
  229. unsigned int gpio = d->hwirq;
  230. tegra_gpio_writel(tgi, 1 << GPIO_BIT(gpio), GPIO_INT_CLR(tgi, gpio));
  231. }
  232. static void tegra_gpio_irq_mask(struct irq_data *d)
  233. {
  234. struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
  235. struct tegra_gpio_info *tgi = bank->tgi;
  236. unsigned int gpio = d->hwirq;
  237. tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 0);
  238. }
  239. static void tegra_gpio_irq_unmask(struct irq_data *d)
  240. {
  241. struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
  242. struct tegra_gpio_info *tgi = bank->tgi;
  243. unsigned int gpio = d->hwirq;
  244. tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 1);
  245. }
  246. static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
  247. {
  248. unsigned int gpio = d->hwirq, port = GPIO_PORT(gpio), lvl_type;
  249. struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
  250. struct tegra_gpio_info *tgi = bank->tgi;
  251. unsigned long flags;
  252. u32 val;
  253. int ret;
  254. switch (type & IRQ_TYPE_SENSE_MASK) {
  255. case IRQ_TYPE_EDGE_RISING:
  256. lvl_type = GPIO_INT_LVL_EDGE_RISING;
  257. break;
  258. case IRQ_TYPE_EDGE_FALLING:
  259. lvl_type = GPIO_INT_LVL_EDGE_FALLING;
  260. break;
  261. case IRQ_TYPE_EDGE_BOTH:
  262. lvl_type = GPIO_INT_LVL_EDGE_BOTH;
  263. break;
  264. case IRQ_TYPE_LEVEL_HIGH:
  265. lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
  266. break;
  267. case IRQ_TYPE_LEVEL_LOW:
  268. lvl_type = GPIO_INT_LVL_LEVEL_LOW;
  269. break;
  270. default:
  271. return -EINVAL;
  272. }
  273. spin_lock_irqsave(&bank->lvl_lock[port], flags);
  274. val = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio));
  275. val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
  276. val |= lvl_type << GPIO_BIT(gpio);
  277. tegra_gpio_writel(tgi, val, GPIO_INT_LVL(tgi, gpio));
  278. spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
  279. tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, gpio), gpio, 0);
  280. tegra_gpio_enable(tgi, gpio);
  281. ret = gpiochip_lock_as_irq(&tgi->gc, gpio);
  282. if (ret) {
  283. dev_err(tgi->dev,
  284. "unable to lock Tegra GPIO %u as IRQ\n", gpio);
  285. tegra_gpio_disable(tgi, gpio);
  286. return ret;
  287. }
  288. if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
  289. irq_set_handler_locked(d, handle_level_irq);
  290. else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
  291. irq_set_handler_locked(d, handle_edge_irq);
  292. return 0;
  293. }
  294. static void tegra_gpio_irq_shutdown(struct irq_data *d)
  295. {
  296. struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
  297. struct tegra_gpio_info *tgi = bank->tgi;
  298. unsigned int gpio = d->hwirq;
  299. tegra_gpio_irq_mask(d);
  300. gpiochip_unlock_as_irq(&tgi->gc, gpio);
  301. }
  302. static void tegra_gpio_irq_handler(struct irq_desc *desc)
  303. {
  304. unsigned int port, pin, gpio;
  305. bool unmasked = false;
  306. u32 lvl;
  307. unsigned long sta;
  308. struct irq_chip *chip = irq_desc_get_chip(desc);
  309. struct tegra_gpio_bank *bank = irq_desc_get_handler_data(desc);
  310. struct tegra_gpio_info *tgi = bank->tgi;
  311. chained_irq_enter(chip, desc);
  312. for (port = 0; port < 4; port++) {
  313. gpio = tegra_gpio_compose(bank->bank, port, 0);
  314. sta = tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)) &
  315. tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio));
  316. lvl = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio));
  317. for_each_set_bit(pin, &sta, 8) {
  318. tegra_gpio_writel(tgi, 1 << pin,
  319. GPIO_INT_CLR(tgi, gpio));
  320. /* if gpio is edge triggered, clear condition
  321. * before executing the handler so that we don't
  322. * miss edges
  323. */
  324. if (!unmasked && lvl & (0x100 << pin)) {
  325. unmasked = true;
  326. chained_irq_exit(chip, desc);
  327. }
  328. generic_handle_irq(irq_find_mapping(tgi->irq_domain,
  329. gpio + pin));
  330. }
  331. }
  332. if (!unmasked)
  333. chained_irq_exit(chip, desc);
  334. }
  335. #ifdef CONFIG_PM_SLEEP
  336. static int tegra_gpio_resume(struct device *dev)
  337. {
  338. struct tegra_gpio_info *tgi = dev_get_drvdata(dev);
  339. unsigned int b, p;
  340. for (b = 0; b < tgi->bank_count; b++) {
  341. struct tegra_gpio_bank *bank = &tgi->bank_info[b];
  342. for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
  343. unsigned int gpio = (b << 5) | (p << 3);
  344. tegra_gpio_writel(tgi, bank->cnf[p],
  345. GPIO_CNF(tgi, gpio));
  346. if (tgi->soc->debounce_supported) {
  347. tegra_gpio_writel(tgi, bank->dbc_cnt[p],
  348. GPIO_DBC_CNT(tgi, gpio));
  349. tegra_gpio_writel(tgi, bank->dbc_enb[p],
  350. GPIO_MSK_DBC_EN(tgi, gpio));
  351. }
  352. tegra_gpio_writel(tgi, bank->out[p],
  353. GPIO_OUT(tgi, gpio));
  354. tegra_gpio_writel(tgi, bank->oe[p],
  355. GPIO_OE(tgi, gpio));
  356. tegra_gpio_writel(tgi, bank->int_lvl[p],
  357. GPIO_INT_LVL(tgi, gpio));
  358. tegra_gpio_writel(tgi, bank->int_enb[p],
  359. GPIO_INT_ENB(tgi, gpio));
  360. }
  361. }
  362. return 0;
  363. }
  364. static int tegra_gpio_suspend(struct device *dev)
  365. {
  366. struct tegra_gpio_info *tgi = dev_get_drvdata(dev);
  367. unsigned int b, p;
  368. for (b = 0; b < tgi->bank_count; b++) {
  369. struct tegra_gpio_bank *bank = &tgi->bank_info[b];
  370. for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
  371. unsigned int gpio = (b << 5) | (p << 3);
  372. bank->cnf[p] = tegra_gpio_readl(tgi,
  373. GPIO_CNF(tgi, gpio));
  374. bank->out[p] = tegra_gpio_readl(tgi,
  375. GPIO_OUT(tgi, gpio));
  376. bank->oe[p] = tegra_gpio_readl(tgi,
  377. GPIO_OE(tgi, gpio));
  378. if (tgi->soc->debounce_supported) {
  379. bank->dbc_enb[p] = tegra_gpio_readl(tgi,
  380. GPIO_MSK_DBC_EN(tgi, gpio));
  381. bank->dbc_enb[p] = (bank->dbc_enb[p] << 8) |
  382. bank->dbc_enb[p];
  383. }
  384. bank->int_enb[p] = tegra_gpio_readl(tgi,
  385. GPIO_INT_ENB(tgi, gpio));
  386. bank->int_lvl[p] = tegra_gpio_readl(tgi,
  387. GPIO_INT_LVL(tgi, gpio));
  388. /* Enable gpio irq for wake up source */
  389. tegra_gpio_writel(tgi, bank->wake_enb[p],
  390. GPIO_INT_ENB(tgi, gpio));
  391. }
  392. }
  393. return 0;
  394. }
  395. static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
  396. {
  397. struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
  398. unsigned int gpio = d->hwirq;
  399. u32 port, bit, mask;
  400. int err;
  401. err = irq_set_irq_wake(bank->irq, enable);
  402. if (err)
  403. return err;
  404. port = GPIO_PORT(gpio);
  405. bit = GPIO_BIT(gpio);
  406. mask = BIT(bit);
  407. if (enable)
  408. bank->wake_enb[port] |= mask;
  409. else
  410. bank->wake_enb[port] &= ~mask;
  411. return 0;
  412. }
  413. #endif
  414. #ifdef CONFIG_DEBUG_FS
  415. #include <linux/debugfs.h>
  416. #include <linux/seq_file.h>
  417. static int tegra_dbg_gpio_show(struct seq_file *s, void *unused)
  418. {
  419. struct tegra_gpio_info *tgi = s->private;
  420. unsigned int i, j;
  421. for (i = 0; i < tgi->bank_count; i++) {
  422. for (j = 0; j < 4; j++) {
  423. unsigned int gpio = tegra_gpio_compose(i, j, 0);
  424. seq_printf(s,
  425. "%u:%u %02x %02x %02x %02x %02x %02x %06x\n",
  426. i, j,
  427. tegra_gpio_readl(tgi, GPIO_CNF(tgi, gpio)),
  428. tegra_gpio_readl(tgi, GPIO_OE(tgi, gpio)),
  429. tegra_gpio_readl(tgi, GPIO_OUT(tgi, gpio)),
  430. tegra_gpio_readl(tgi, GPIO_IN(tgi, gpio)),
  431. tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)),
  432. tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio)),
  433. tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio)));
  434. }
  435. }
  436. return 0;
  437. }
  438. DEFINE_SHOW_ATTRIBUTE(tegra_dbg_gpio);
  439. static void tegra_gpio_debuginit(struct tegra_gpio_info *tgi)
  440. {
  441. debugfs_create_file("tegra_gpio", 0444, NULL, tgi,
  442. &tegra_dbg_gpio_fops);
  443. }
  444. #else
  445. static inline void tegra_gpio_debuginit(struct tegra_gpio_info *tgi)
  446. {
  447. }
  448. #endif
  449. static const struct dev_pm_ops tegra_gpio_pm_ops = {
  450. SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume)
  451. };
  452. static int tegra_gpio_probe(struct platform_device *pdev)
  453. {
  454. struct tegra_gpio_info *tgi;
  455. struct tegra_gpio_bank *bank;
  456. unsigned int gpio, i, j;
  457. int ret;
  458. tgi = devm_kzalloc(&pdev->dev, sizeof(*tgi), GFP_KERNEL);
  459. if (!tgi)
  460. return -ENODEV;
  461. tgi->soc = of_device_get_match_data(&pdev->dev);
  462. tgi->dev = &pdev->dev;
  463. ret = platform_irq_count(pdev);
  464. if (ret < 0)
  465. return ret;
  466. tgi->bank_count = ret;
  467. if (!tgi->bank_count) {
  468. dev_err(&pdev->dev, "Missing IRQ resource\n");
  469. return -ENODEV;
  470. }
  471. tgi->gc.label = "tegra-gpio";
  472. tgi->gc.request = tegra_gpio_request;
  473. tgi->gc.free = tegra_gpio_free;
  474. tgi->gc.direction_input = tegra_gpio_direction_input;
  475. tgi->gc.get = tegra_gpio_get;
  476. tgi->gc.direction_output = tegra_gpio_direction_output;
  477. tgi->gc.set = tegra_gpio_set;
  478. tgi->gc.get_direction = tegra_gpio_get_direction;
  479. tgi->gc.to_irq = tegra_gpio_to_irq;
  480. tgi->gc.base = 0;
  481. tgi->gc.ngpio = tgi->bank_count * 32;
  482. tgi->gc.parent = &pdev->dev;
  483. tgi->gc.of_node = pdev->dev.of_node;
  484. tgi->ic.name = "GPIO";
  485. tgi->ic.irq_ack = tegra_gpio_irq_ack;
  486. tgi->ic.irq_mask = tegra_gpio_irq_mask;
  487. tgi->ic.irq_unmask = tegra_gpio_irq_unmask;
  488. tgi->ic.irq_set_type = tegra_gpio_irq_set_type;
  489. tgi->ic.irq_shutdown = tegra_gpio_irq_shutdown;
  490. #ifdef CONFIG_PM_SLEEP
  491. tgi->ic.irq_set_wake = tegra_gpio_irq_set_wake;
  492. #endif
  493. platform_set_drvdata(pdev, tgi);
  494. if (tgi->soc->debounce_supported)
  495. tgi->gc.set_config = tegra_gpio_set_config;
  496. tgi->bank_info = devm_kcalloc(&pdev->dev, tgi->bank_count,
  497. sizeof(*tgi->bank_info), GFP_KERNEL);
  498. if (!tgi->bank_info)
  499. return -ENOMEM;
  500. tgi->irq_domain = irq_domain_add_linear(pdev->dev.of_node,
  501. tgi->gc.ngpio,
  502. &irq_domain_simple_ops, NULL);
  503. if (!tgi->irq_domain)
  504. return -ENODEV;
  505. for (i = 0; i < tgi->bank_count; i++) {
  506. ret = platform_get_irq(pdev, i);
  507. if (ret < 0)
  508. return ret;
  509. bank = &tgi->bank_info[i];
  510. bank->bank = i;
  511. bank->irq = ret;
  512. bank->tgi = tgi;
  513. }
  514. tgi->regs = devm_platform_ioremap_resource(pdev, 0);
  515. if (IS_ERR(tgi->regs))
  516. return PTR_ERR(tgi->regs);
  517. for (i = 0; i < tgi->bank_count; i++) {
  518. for (j = 0; j < 4; j++) {
  519. int gpio = tegra_gpio_compose(i, j, 0);
  520. tegra_gpio_writel(tgi, 0x00, GPIO_INT_ENB(tgi, gpio));
  521. }
  522. }
  523. ret = devm_gpiochip_add_data(&pdev->dev, &tgi->gc, tgi);
  524. if (ret < 0) {
  525. irq_domain_remove(tgi->irq_domain);
  526. return ret;
  527. }
  528. for (gpio = 0; gpio < tgi->gc.ngpio; gpio++) {
  529. int irq = irq_create_mapping(tgi->irq_domain, gpio);
  530. /* No validity check; all Tegra GPIOs are valid IRQs */
  531. bank = &tgi->bank_info[GPIO_BANK(gpio)];
  532. irq_set_chip_data(irq, bank);
  533. irq_set_chip_and_handler(irq, &tgi->ic, handle_simple_irq);
  534. }
  535. for (i = 0; i < tgi->bank_count; i++) {
  536. bank = &tgi->bank_info[i];
  537. irq_set_chained_handler_and_data(bank->irq,
  538. tegra_gpio_irq_handler, bank);
  539. for (j = 0; j < 4; j++) {
  540. spin_lock_init(&bank->lvl_lock[j]);
  541. spin_lock_init(&bank->dbc_lock[j]);
  542. }
  543. }
  544. tegra_gpio_debuginit(tgi);
  545. return 0;
  546. }
  547. static const struct tegra_gpio_soc_config tegra20_gpio_config = {
  548. .bank_stride = 0x80,
  549. .upper_offset = 0x800,
  550. };
  551. static const struct tegra_gpio_soc_config tegra30_gpio_config = {
  552. .bank_stride = 0x100,
  553. .upper_offset = 0x80,
  554. };
  555. static const struct tegra_gpio_soc_config tegra210_gpio_config = {
  556. .debounce_supported = true,
  557. .bank_stride = 0x100,
  558. .upper_offset = 0x80,
  559. };
  560. static const struct of_device_id tegra_gpio_of_match[] = {
  561. { .compatible = "nvidia,tegra210-gpio", .data = &tegra210_gpio_config },
  562. { .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config },
  563. { .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config },
  564. { },
  565. };
  566. static struct platform_driver tegra_gpio_driver = {
  567. .driver = {
  568. .name = "tegra-gpio",
  569. .pm = &tegra_gpio_pm_ops,
  570. .of_match_table = tegra_gpio_of_match,
  571. },
  572. .probe = tegra_gpio_probe,
  573. };
  574. static int __init tegra_gpio_init(void)
  575. {
  576. return platform_driver_register(&tegra_gpio_driver);
  577. }
  578. subsys_initcall(tegra_gpio_init);