gpio-tc3589x.c 10 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) ST-Ericsson SA 2010
  4. *
  5. * Author: Hanumath Prasad <hanumath.prasad@stericsson.com> for ST-Ericsson
  6. * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
  7. */
  8. #include <linux/init.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/slab.h>
  11. #include <linux/gpio/driver.h>
  12. #include <linux/of.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/mfd/tc3589x.h>
  15. #include <linux/bitops.h>
  16. /*
  17. * These registers are modified under the irq bus lock and cached to avoid
  18. * unnecessary writes in bus_sync_unlock.
  19. */
  20. enum { REG_IBE, REG_IEV, REG_IS, REG_IE, REG_DIRECT };
  21. #define CACHE_NR_REGS 5
  22. #define CACHE_NR_BANKS 3
  23. struct tc3589x_gpio {
  24. struct gpio_chip chip;
  25. struct tc3589x *tc3589x;
  26. struct device *dev;
  27. struct mutex irq_lock;
  28. /* Caches of interrupt control registers for bus_lock */
  29. u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
  30. u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
  31. };
  32. static int tc3589x_gpio_get(struct gpio_chip *chip, unsigned int offset)
  33. {
  34. struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
  35. struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
  36. u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2;
  37. u8 mask = BIT(offset % 8);
  38. int ret;
  39. ret = tc3589x_reg_read(tc3589x, reg);
  40. if (ret < 0)
  41. return ret;
  42. return !!(ret & mask);
  43. }
  44. static void tc3589x_gpio_set(struct gpio_chip *chip, unsigned int offset, int val)
  45. {
  46. struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
  47. struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
  48. u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2;
  49. unsigned int pos = offset % 8;
  50. u8 data[] = {val ? BIT(pos) : 0, BIT(pos)};
  51. tc3589x_block_write(tc3589x, reg, ARRAY_SIZE(data), data);
  52. }
  53. static int tc3589x_gpio_direction_output(struct gpio_chip *chip,
  54. unsigned int offset, int val)
  55. {
  56. struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
  57. struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
  58. u8 reg = TC3589x_GPIODIR0 + offset / 8;
  59. unsigned int pos = offset % 8;
  60. tc3589x_gpio_set(chip, offset, val);
  61. return tc3589x_set_bits(tc3589x, reg, BIT(pos), BIT(pos));
  62. }
  63. static int tc3589x_gpio_direction_input(struct gpio_chip *chip,
  64. unsigned int offset)
  65. {
  66. struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
  67. struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
  68. u8 reg = TC3589x_GPIODIR0 + offset / 8;
  69. unsigned int pos = offset % 8;
  70. return tc3589x_set_bits(tc3589x, reg, BIT(pos), 0);
  71. }
  72. static int tc3589x_gpio_get_direction(struct gpio_chip *chip,
  73. unsigned int offset)
  74. {
  75. struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
  76. struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
  77. u8 reg = TC3589x_GPIODIR0 + offset / 8;
  78. unsigned int pos = offset % 8;
  79. int ret;
  80. ret = tc3589x_reg_read(tc3589x, reg);
  81. if (ret < 0)
  82. return ret;
  83. if (ret & BIT(pos))
  84. return GPIO_LINE_DIRECTION_OUT;
  85. return GPIO_LINE_DIRECTION_IN;
  86. }
  87. static int tc3589x_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
  88. unsigned long config)
  89. {
  90. struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
  91. struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
  92. /*
  93. * These registers are alterated at each second address
  94. * ODM bit 0 = drive to GND or Hi-Z (open drain)
  95. * ODM bit 1 = drive to VDD or Hi-Z (open source)
  96. */
  97. u8 odmreg = TC3589x_GPIOODM0 + (offset / 8) * 2;
  98. u8 odereg = TC3589x_GPIOODE0 + (offset / 8) * 2;
  99. unsigned int pos = offset % 8;
  100. int ret;
  101. switch (pinconf_to_config_param(config)) {
  102. case PIN_CONFIG_DRIVE_OPEN_DRAIN:
  103. /* Set open drain mode */
  104. ret = tc3589x_set_bits(tc3589x, odmreg, BIT(pos), 0);
  105. if (ret)
  106. return ret;
  107. /* Enable open drain/source mode */
  108. return tc3589x_set_bits(tc3589x, odereg, BIT(pos), BIT(pos));
  109. case PIN_CONFIG_DRIVE_OPEN_SOURCE:
  110. /* Set open source mode */
  111. ret = tc3589x_set_bits(tc3589x, odmreg, BIT(pos), BIT(pos));
  112. if (ret)
  113. return ret;
  114. /* Enable open drain/source mode */
  115. return tc3589x_set_bits(tc3589x, odereg, BIT(pos), BIT(pos));
  116. case PIN_CONFIG_DRIVE_PUSH_PULL:
  117. /* Disable open drain/source mode */
  118. return tc3589x_set_bits(tc3589x, odereg, BIT(pos), 0);
  119. default:
  120. break;
  121. }
  122. return -ENOTSUPP;
  123. }
  124. static const struct gpio_chip template_chip = {
  125. .label = "tc3589x",
  126. .owner = THIS_MODULE,
  127. .get = tc3589x_gpio_get,
  128. .set = tc3589x_gpio_set,
  129. .direction_output = tc3589x_gpio_direction_output,
  130. .direction_input = tc3589x_gpio_direction_input,
  131. .get_direction = tc3589x_gpio_get_direction,
  132. .set_config = tc3589x_gpio_set_config,
  133. .can_sleep = true,
  134. };
  135. static int tc3589x_gpio_irq_set_type(struct irq_data *d, unsigned int type)
  136. {
  137. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  138. struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
  139. int offset = d->hwirq;
  140. int regoffset = offset / 8;
  141. int mask = BIT(offset % 8);
  142. if (type == IRQ_TYPE_EDGE_BOTH) {
  143. tc3589x_gpio->regs[REG_IBE][regoffset] |= mask;
  144. return 0;
  145. }
  146. tc3589x_gpio->regs[REG_IBE][regoffset] &= ~mask;
  147. if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH)
  148. tc3589x_gpio->regs[REG_IS][regoffset] |= mask;
  149. else
  150. tc3589x_gpio->regs[REG_IS][regoffset] &= ~mask;
  151. if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH)
  152. tc3589x_gpio->regs[REG_IEV][regoffset] |= mask;
  153. else
  154. tc3589x_gpio->regs[REG_IEV][regoffset] &= ~mask;
  155. return 0;
  156. }
  157. static void tc3589x_gpio_irq_lock(struct irq_data *d)
  158. {
  159. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  160. struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
  161. mutex_lock(&tc3589x_gpio->irq_lock);
  162. }
  163. static void tc3589x_gpio_irq_sync_unlock(struct irq_data *d)
  164. {
  165. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  166. struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
  167. struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
  168. static const u8 regmap[] = {
  169. [REG_IBE] = TC3589x_GPIOIBE0,
  170. [REG_IEV] = TC3589x_GPIOIEV0,
  171. [REG_IS] = TC3589x_GPIOIS0,
  172. [REG_IE] = TC3589x_GPIOIE0,
  173. [REG_DIRECT] = TC3589x_DIRECT0,
  174. };
  175. int i, j;
  176. for (i = 0; i < CACHE_NR_REGS; i++) {
  177. for (j = 0; j < CACHE_NR_BANKS; j++) {
  178. u8 old = tc3589x_gpio->oldregs[i][j];
  179. u8 new = tc3589x_gpio->regs[i][j];
  180. if (new == old)
  181. continue;
  182. tc3589x_gpio->oldregs[i][j] = new;
  183. tc3589x_reg_write(tc3589x, regmap[i] + j, new);
  184. }
  185. }
  186. mutex_unlock(&tc3589x_gpio->irq_lock);
  187. }
  188. static void tc3589x_gpio_irq_mask(struct irq_data *d)
  189. {
  190. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  191. struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
  192. int offset = d->hwirq;
  193. int regoffset = offset / 8;
  194. int mask = BIT(offset % 8);
  195. tc3589x_gpio->regs[REG_IE][regoffset] &= ~mask;
  196. tc3589x_gpio->regs[REG_DIRECT][regoffset] |= mask;
  197. }
  198. static void tc3589x_gpio_irq_unmask(struct irq_data *d)
  199. {
  200. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  201. struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
  202. int offset = d->hwirq;
  203. int regoffset = offset / 8;
  204. int mask = BIT(offset % 8);
  205. tc3589x_gpio->regs[REG_IE][regoffset] |= mask;
  206. tc3589x_gpio->regs[REG_DIRECT][regoffset] &= ~mask;
  207. }
  208. static struct irq_chip tc3589x_gpio_irq_chip = {
  209. .name = "tc3589x-gpio",
  210. .irq_bus_lock = tc3589x_gpio_irq_lock,
  211. .irq_bus_sync_unlock = tc3589x_gpio_irq_sync_unlock,
  212. .irq_mask = tc3589x_gpio_irq_mask,
  213. .irq_unmask = tc3589x_gpio_irq_unmask,
  214. .irq_set_type = tc3589x_gpio_irq_set_type,
  215. };
  216. static irqreturn_t tc3589x_gpio_irq(int irq, void *dev)
  217. {
  218. struct tc3589x_gpio *tc3589x_gpio = dev;
  219. struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
  220. u8 status[CACHE_NR_BANKS];
  221. int ret;
  222. int i;
  223. ret = tc3589x_block_read(tc3589x, TC3589x_GPIOMIS0,
  224. ARRAY_SIZE(status), status);
  225. if (ret < 0)
  226. return IRQ_NONE;
  227. for (i = 0; i < ARRAY_SIZE(status); i++) {
  228. unsigned int stat = status[i];
  229. if (!stat)
  230. continue;
  231. while (stat) {
  232. int bit = __ffs(stat);
  233. int line = i * 8 + bit;
  234. int irq = irq_find_mapping(tc3589x_gpio->chip.irq.domain,
  235. line);
  236. handle_nested_irq(irq);
  237. stat &= ~(1 << bit);
  238. }
  239. tc3589x_reg_write(tc3589x, TC3589x_GPIOIC0 + i, status[i]);
  240. }
  241. return IRQ_HANDLED;
  242. }
  243. static int tc3589x_gpio_probe(struct platform_device *pdev)
  244. {
  245. struct tc3589x *tc3589x = dev_get_drvdata(pdev->dev.parent);
  246. struct device_node *np = pdev->dev.of_node;
  247. struct tc3589x_gpio *tc3589x_gpio;
  248. struct gpio_irq_chip *girq;
  249. int ret;
  250. int irq;
  251. if (!np) {
  252. dev_err(&pdev->dev, "No Device Tree node found\n");
  253. return -EINVAL;
  254. }
  255. irq = platform_get_irq(pdev, 0);
  256. if (irq < 0)
  257. return irq;
  258. tc3589x_gpio = devm_kzalloc(&pdev->dev, sizeof(struct tc3589x_gpio),
  259. GFP_KERNEL);
  260. if (!tc3589x_gpio)
  261. return -ENOMEM;
  262. mutex_init(&tc3589x_gpio->irq_lock);
  263. tc3589x_gpio->dev = &pdev->dev;
  264. tc3589x_gpio->tc3589x = tc3589x;
  265. tc3589x_gpio->chip = template_chip;
  266. tc3589x_gpio->chip.ngpio = tc3589x->num_gpio;
  267. tc3589x_gpio->chip.parent = &pdev->dev;
  268. tc3589x_gpio->chip.base = -1;
  269. tc3589x_gpio->chip.of_node = np;
  270. girq = &tc3589x_gpio->chip.irq;
  271. girq->chip = &tc3589x_gpio_irq_chip;
  272. /* This will let us handle the parent IRQ in the driver */
  273. girq->parent_handler = NULL;
  274. girq->num_parents = 0;
  275. girq->parents = NULL;
  276. girq->default_type = IRQ_TYPE_NONE;
  277. girq->handler = handle_simple_irq;
  278. girq->threaded = true;
  279. /* Bring the GPIO module out of reset */
  280. ret = tc3589x_set_bits(tc3589x, TC3589x_RSTCTRL,
  281. TC3589x_RSTCTRL_GPIRST, 0);
  282. if (ret < 0)
  283. return ret;
  284. /* For tc35894, have to disable Direct KBD interrupts,
  285. * else IRQST will always be 0x20, IRQN low level, can't
  286. * clear the irq status.
  287. * TODO: need more test on other tc3589x chip.
  288. *
  289. */
  290. ret = tc3589x_reg_write(tc3589x, TC3589x_DKBDMSK,
  291. TC3589x_DKBDMSK_ELINT | TC3589x_DKBDMSK_EINT);
  292. if (ret < 0)
  293. return ret;
  294. ret = devm_request_threaded_irq(&pdev->dev,
  295. irq, NULL, tc3589x_gpio_irq,
  296. IRQF_ONESHOT, "tc3589x-gpio",
  297. tc3589x_gpio);
  298. if (ret) {
  299. dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
  300. return ret;
  301. }
  302. ret = devm_gpiochip_add_data(&pdev->dev, &tc3589x_gpio->chip,
  303. tc3589x_gpio);
  304. if (ret) {
  305. dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
  306. return ret;
  307. }
  308. platform_set_drvdata(pdev, tc3589x_gpio);
  309. return 0;
  310. }
  311. static struct platform_driver tc3589x_gpio_driver = {
  312. .driver.name = "tc3589x-gpio",
  313. .probe = tc3589x_gpio_probe,
  314. };
  315. static int __init tc3589x_gpio_init(void)
  316. {
  317. return platform_driver_register(&tc3589x_gpio_driver);
  318. }
  319. subsys_initcall(tc3589x_gpio_init);