gpio-tb10x.c 6.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /* Abilis Systems MODULE DESCRIPTION
  3. *
  4. * Copyright (C) Abilis Systems 2013
  5. *
  6. * Authors: Sascha Leuenberger <sascha.leuenberger@abilis.com>
  7. * Christian Ruppert <christian.ruppert@abilis.com>
  8. */
  9. #include <linux/kernel.h>
  10. #include <linux/module.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/gpio/driver.h>
  13. #include <linux/slab.h>
  14. #include <linux/irq.h>
  15. #include <linux/irqdomain.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/io.h>
  18. #include <linux/of.h>
  19. #include <linux/of_platform.h>
  20. #include <linux/spinlock.h>
  21. #include <linux/bitops.h>
  22. #include <linux/pinctrl/consumer.h>
  23. #define TB10X_GPIO_DIR_IN (0x00000000)
  24. #define TB10X_GPIO_DIR_OUT (0x00000001)
  25. #define OFFSET_TO_REG_DDR (0x00)
  26. #define OFFSET_TO_REG_DATA (0x04)
  27. #define OFFSET_TO_REG_INT_EN (0x08)
  28. #define OFFSET_TO_REG_CHANGE (0x0C)
  29. #define OFFSET_TO_REG_WRMASK (0x10)
  30. #define OFFSET_TO_REG_INT_TYPE (0x14)
  31. /**
  32. * @base: register base address
  33. * @domain: IRQ domain of GPIO generated interrupts managed by this controller
  34. * @irq: Interrupt line of parent interrupt controller
  35. * @gc: gpio_chip structure associated to this GPIO controller
  36. */
  37. struct tb10x_gpio {
  38. void __iomem *base;
  39. struct irq_domain *domain;
  40. int irq;
  41. struct gpio_chip gc;
  42. };
  43. static inline u32 tb10x_reg_read(struct tb10x_gpio *gpio, unsigned int offs)
  44. {
  45. return ioread32(gpio->base + offs);
  46. }
  47. static inline void tb10x_reg_write(struct tb10x_gpio *gpio, unsigned int offs,
  48. u32 val)
  49. {
  50. iowrite32(val, gpio->base + offs);
  51. }
  52. static inline void tb10x_set_bits(struct tb10x_gpio *gpio, unsigned int offs,
  53. u32 mask, u32 val)
  54. {
  55. u32 r;
  56. unsigned long flags;
  57. spin_lock_irqsave(&gpio->gc.bgpio_lock, flags);
  58. r = tb10x_reg_read(gpio, offs);
  59. r = (r & ~mask) | (val & mask);
  60. tb10x_reg_write(gpio, offs, r);
  61. spin_unlock_irqrestore(&gpio->gc.bgpio_lock, flags);
  62. }
  63. static int tb10x_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
  64. {
  65. struct tb10x_gpio *tb10x_gpio = gpiochip_get_data(chip);
  66. return irq_create_mapping(tb10x_gpio->domain, offset);
  67. }
  68. static int tb10x_gpio_irq_set_type(struct irq_data *data, unsigned int type)
  69. {
  70. if ((type & IRQF_TRIGGER_MASK) != IRQ_TYPE_EDGE_BOTH) {
  71. pr_err("Only (both) edge triggered interrupts supported.\n");
  72. return -EINVAL;
  73. }
  74. irqd_set_trigger_type(data, type);
  75. return IRQ_SET_MASK_OK;
  76. }
  77. static irqreturn_t tb10x_gpio_irq_cascade(int irq, void *data)
  78. {
  79. struct tb10x_gpio *tb10x_gpio = data;
  80. u32 r = tb10x_reg_read(tb10x_gpio, OFFSET_TO_REG_CHANGE);
  81. u32 m = tb10x_reg_read(tb10x_gpio, OFFSET_TO_REG_INT_EN);
  82. const unsigned long bits = r & m;
  83. int i;
  84. for_each_set_bit(i, &bits, 32)
  85. generic_handle_irq(irq_find_mapping(tb10x_gpio->domain, i));
  86. return IRQ_HANDLED;
  87. }
  88. static int tb10x_gpio_probe(struct platform_device *pdev)
  89. {
  90. struct tb10x_gpio *tb10x_gpio;
  91. struct device *dev = &pdev->dev;
  92. struct device_node *np = dev->of_node;
  93. int ret = -EBUSY;
  94. u32 ngpio;
  95. if (!np)
  96. return -EINVAL;
  97. if (of_property_read_u32(np, "abilis,ngpio", &ngpio))
  98. return -EINVAL;
  99. tb10x_gpio = devm_kzalloc(dev, sizeof(*tb10x_gpio), GFP_KERNEL);
  100. if (tb10x_gpio == NULL)
  101. return -ENOMEM;
  102. tb10x_gpio->base = devm_platform_ioremap_resource(pdev, 0);
  103. if (IS_ERR(tb10x_gpio->base))
  104. return PTR_ERR(tb10x_gpio->base);
  105. tb10x_gpio->gc.label =
  106. devm_kasprintf(dev, GFP_KERNEL, "%pOF", pdev->dev.of_node);
  107. if (!tb10x_gpio->gc.label)
  108. return -ENOMEM;
  109. /*
  110. * Initialize generic GPIO with one single register for reading and setting
  111. * the lines, no special set or clear registers and a data direction register
  112. * wher 1 means "output".
  113. */
  114. ret = bgpio_init(&tb10x_gpio->gc, dev, 4,
  115. tb10x_gpio->base + OFFSET_TO_REG_DATA,
  116. NULL,
  117. NULL,
  118. tb10x_gpio->base + OFFSET_TO_REG_DDR,
  119. NULL,
  120. 0);
  121. if (ret) {
  122. dev_err(dev, "unable to init generic GPIO\n");
  123. return ret;
  124. }
  125. tb10x_gpio->gc.base = -1;
  126. tb10x_gpio->gc.parent = dev;
  127. tb10x_gpio->gc.owner = THIS_MODULE;
  128. /*
  129. * ngpio is set by bgpio_init() but we override it, this .request()
  130. * callback also overrides the one set up by generic GPIO.
  131. */
  132. tb10x_gpio->gc.ngpio = ngpio;
  133. tb10x_gpio->gc.request = gpiochip_generic_request;
  134. tb10x_gpio->gc.free = gpiochip_generic_free;
  135. ret = devm_gpiochip_add_data(dev, &tb10x_gpio->gc, tb10x_gpio);
  136. if (ret < 0) {
  137. dev_err(dev, "Could not add gpiochip.\n");
  138. return ret;
  139. }
  140. platform_set_drvdata(pdev, tb10x_gpio);
  141. if (of_find_property(np, "interrupt-controller", NULL)) {
  142. struct irq_chip_generic *gc;
  143. ret = platform_get_irq(pdev, 0);
  144. if (ret < 0)
  145. return ret;
  146. tb10x_gpio->gc.to_irq = tb10x_gpio_to_irq;
  147. tb10x_gpio->irq = ret;
  148. ret = devm_request_irq(dev, ret, tb10x_gpio_irq_cascade,
  149. IRQF_TRIGGER_NONE | IRQF_SHARED,
  150. dev_name(dev), tb10x_gpio);
  151. if (ret != 0)
  152. return ret;
  153. tb10x_gpio->domain = irq_domain_add_linear(np,
  154. tb10x_gpio->gc.ngpio,
  155. &irq_generic_chip_ops, NULL);
  156. if (!tb10x_gpio->domain) {
  157. return -ENOMEM;
  158. }
  159. ret = irq_alloc_domain_generic_chips(tb10x_gpio->domain,
  160. tb10x_gpio->gc.ngpio, 1, tb10x_gpio->gc.label,
  161. handle_edge_irq, IRQ_NOREQUEST, IRQ_NOPROBE,
  162. IRQ_GC_INIT_MASK_CACHE);
  163. if (ret)
  164. return ret;
  165. gc = tb10x_gpio->domain->gc->gc[0];
  166. gc->reg_base = tb10x_gpio->base;
  167. gc->chip_types[0].type = IRQ_TYPE_EDGE_BOTH;
  168. gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
  169. gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
  170. gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
  171. gc->chip_types[0].chip.irq_set_type = tb10x_gpio_irq_set_type;
  172. gc->chip_types[0].regs.ack = OFFSET_TO_REG_CHANGE;
  173. gc->chip_types[0].regs.mask = OFFSET_TO_REG_INT_EN;
  174. }
  175. return 0;
  176. }
  177. static int tb10x_gpio_remove(struct platform_device *pdev)
  178. {
  179. struct tb10x_gpio *tb10x_gpio = platform_get_drvdata(pdev);
  180. if (tb10x_gpio->gc.to_irq) {
  181. irq_remove_generic_chip(tb10x_gpio->domain->gc->gc[0],
  182. BIT(tb10x_gpio->gc.ngpio) - 1, 0, 0);
  183. kfree(tb10x_gpio->domain->gc);
  184. irq_domain_remove(tb10x_gpio->domain);
  185. }
  186. return 0;
  187. }
  188. static const struct of_device_id tb10x_gpio_dt_ids[] = {
  189. { .compatible = "abilis,tb10x-gpio" },
  190. { }
  191. };
  192. MODULE_DEVICE_TABLE(of, tb10x_gpio_dt_ids);
  193. static struct platform_driver tb10x_gpio_driver = {
  194. .probe = tb10x_gpio_probe,
  195. .remove = tb10x_gpio_remove,
  196. .driver = {
  197. .name = "tb10x-gpio",
  198. .of_match_table = tb10x_gpio_dt_ids,
  199. }
  200. };
  201. module_platform_driver(tb10x_gpio_driver);
  202. MODULE_LICENSE("GPL");
  203. MODULE_DESCRIPTION("tb10x gpio.");