gpio-syscon.c 7.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * SYSCON GPIO driver
  4. *
  5. * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
  6. */
  7. #include <linux/err.h>
  8. #include <linux/gpio/driver.h>
  9. #include <linux/module.h>
  10. #include <linux/of.h>
  11. #include <linux/of_device.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/regmap.h>
  14. #include <linux/mfd/syscon.h>
  15. #define GPIO_SYSCON_FEAT_IN BIT(0)
  16. #define GPIO_SYSCON_FEAT_OUT BIT(1)
  17. #define GPIO_SYSCON_FEAT_DIR BIT(2)
  18. /* SYSCON driver is designed to use 32-bit wide registers */
  19. #define SYSCON_REG_SIZE (4)
  20. #define SYSCON_REG_BITS (SYSCON_REG_SIZE * 8)
  21. /**
  22. * struct syscon_gpio_data - Configuration for the device.
  23. * @compatible: SYSCON driver compatible string.
  24. * @flags: Set of GPIO_SYSCON_FEAT_ flags:
  25. * GPIO_SYSCON_FEAT_IN: GPIOs supports input,
  26. * GPIO_SYSCON_FEAT_OUT: GPIOs supports output,
  27. * GPIO_SYSCON_FEAT_DIR: GPIOs supports switch direction.
  28. * @bit_count: Number of bits used as GPIOs.
  29. * @dat_bit_offset: Offset (in bits) to the first GPIO bit.
  30. * @dir_bit_offset: Optional offset (in bits) to the first bit to switch
  31. * GPIO direction (Used with GPIO_SYSCON_FEAT_DIR flag).
  32. * @set: HW specific callback to assigns output value
  33. * for signal "offset"
  34. */
  35. struct syscon_gpio_data {
  36. const char *compatible;
  37. unsigned int flags;
  38. unsigned int bit_count;
  39. unsigned int dat_bit_offset;
  40. unsigned int dir_bit_offset;
  41. void (*set)(struct gpio_chip *chip,
  42. unsigned offset, int value);
  43. };
  44. struct syscon_gpio_priv {
  45. struct gpio_chip chip;
  46. struct regmap *syscon;
  47. const struct syscon_gpio_data *data;
  48. u32 dreg_offset;
  49. u32 dir_reg_offset;
  50. };
  51. static int syscon_gpio_get(struct gpio_chip *chip, unsigned offset)
  52. {
  53. struct syscon_gpio_priv *priv = gpiochip_get_data(chip);
  54. unsigned int val, offs;
  55. int ret;
  56. offs = priv->dreg_offset + priv->data->dat_bit_offset + offset;
  57. ret = regmap_read(priv->syscon,
  58. (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE, &val);
  59. if (ret)
  60. return ret;
  61. return !!(val & BIT(offs % SYSCON_REG_BITS));
  62. }
  63. static void syscon_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
  64. {
  65. struct syscon_gpio_priv *priv = gpiochip_get_data(chip);
  66. unsigned int offs;
  67. offs = priv->dreg_offset + priv->data->dat_bit_offset + offset;
  68. regmap_update_bits(priv->syscon,
  69. (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE,
  70. BIT(offs % SYSCON_REG_BITS),
  71. val ? BIT(offs % SYSCON_REG_BITS) : 0);
  72. }
  73. static int syscon_gpio_dir_in(struct gpio_chip *chip, unsigned offset)
  74. {
  75. struct syscon_gpio_priv *priv = gpiochip_get_data(chip);
  76. if (priv->data->flags & GPIO_SYSCON_FEAT_DIR) {
  77. unsigned int offs;
  78. offs = priv->dir_reg_offset +
  79. priv->data->dir_bit_offset + offset;
  80. regmap_update_bits(priv->syscon,
  81. (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE,
  82. BIT(offs % SYSCON_REG_BITS), 0);
  83. }
  84. return 0;
  85. }
  86. static int syscon_gpio_dir_out(struct gpio_chip *chip, unsigned offset, int val)
  87. {
  88. struct syscon_gpio_priv *priv = gpiochip_get_data(chip);
  89. if (priv->data->flags & GPIO_SYSCON_FEAT_DIR) {
  90. unsigned int offs;
  91. offs = priv->dir_reg_offset +
  92. priv->data->dir_bit_offset + offset;
  93. regmap_update_bits(priv->syscon,
  94. (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE,
  95. BIT(offs % SYSCON_REG_BITS),
  96. BIT(offs % SYSCON_REG_BITS));
  97. }
  98. chip->set(chip, offset, val);
  99. return 0;
  100. }
  101. static const struct syscon_gpio_data clps711x_mctrl_gpio = {
  102. /* ARM CLPS711X SYSFLG1 Bits 8-10 */
  103. .compatible = "cirrus,ep7209-syscon1",
  104. .flags = GPIO_SYSCON_FEAT_IN,
  105. .bit_count = 3,
  106. .dat_bit_offset = 0x40 * 8 + 8,
  107. };
  108. static void rockchip_gpio_set(struct gpio_chip *chip, unsigned int offset,
  109. int val)
  110. {
  111. struct syscon_gpio_priv *priv = gpiochip_get_data(chip);
  112. unsigned int offs;
  113. u8 bit;
  114. u32 data;
  115. int ret;
  116. offs = priv->dreg_offset + priv->data->dat_bit_offset + offset;
  117. bit = offs % SYSCON_REG_BITS;
  118. data = (val ? BIT(bit) : 0) | BIT(bit + 16);
  119. ret = regmap_write(priv->syscon,
  120. (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE,
  121. data);
  122. if (ret < 0)
  123. dev_err(chip->parent, "gpio write failed ret(%d)\n", ret);
  124. }
  125. static const struct syscon_gpio_data rockchip_rk3328_gpio_mute = {
  126. /* RK3328 GPIO_MUTE is an output only pin at GRF_SOC_CON10[1] */
  127. .flags = GPIO_SYSCON_FEAT_OUT,
  128. .bit_count = 1,
  129. .dat_bit_offset = 0x0428 * 8 + 1,
  130. .set = rockchip_gpio_set,
  131. };
  132. #define KEYSTONE_LOCK_BIT BIT(0)
  133. static void keystone_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
  134. {
  135. struct syscon_gpio_priv *priv = gpiochip_get_data(chip);
  136. unsigned int offs;
  137. int ret;
  138. offs = priv->dreg_offset + priv->data->dat_bit_offset + offset;
  139. if (!val)
  140. return;
  141. ret = regmap_update_bits(
  142. priv->syscon,
  143. (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE,
  144. BIT(offs % SYSCON_REG_BITS) | KEYSTONE_LOCK_BIT,
  145. BIT(offs % SYSCON_REG_BITS) | KEYSTONE_LOCK_BIT);
  146. if (ret < 0)
  147. dev_err(chip->parent, "gpio write failed ret(%d)\n", ret);
  148. }
  149. static const struct syscon_gpio_data keystone_dsp_gpio = {
  150. /* ARM Keystone 2 */
  151. .compatible = NULL,
  152. .flags = GPIO_SYSCON_FEAT_OUT,
  153. .bit_count = 28,
  154. .dat_bit_offset = 4,
  155. .set = keystone_gpio_set,
  156. };
  157. static const struct of_device_id syscon_gpio_ids[] = {
  158. {
  159. .compatible = "cirrus,ep7209-mctrl-gpio",
  160. .data = &clps711x_mctrl_gpio,
  161. },
  162. {
  163. .compatible = "ti,keystone-dsp-gpio",
  164. .data = &keystone_dsp_gpio,
  165. },
  166. {
  167. .compatible = "rockchip,rk3328-grf-gpio",
  168. .data = &rockchip_rk3328_gpio_mute,
  169. },
  170. { }
  171. };
  172. MODULE_DEVICE_TABLE(of, syscon_gpio_ids);
  173. static int syscon_gpio_probe(struct platform_device *pdev)
  174. {
  175. struct device *dev = &pdev->dev;
  176. struct syscon_gpio_priv *priv;
  177. struct device_node *np = dev->of_node;
  178. int ret;
  179. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  180. if (!priv)
  181. return -ENOMEM;
  182. priv->data = of_device_get_match_data(dev);
  183. if (priv->data->compatible) {
  184. priv->syscon = syscon_regmap_lookup_by_compatible(
  185. priv->data->compatible);
  186. if (IS_ERR(priv->syscon))
  187. return PTR_ERR(priv->syscon);
  188. } else {
  189. priv->syscon =
  190. syscon_regmap_lookup_by_phandle(np, "gpio,syscon-dev");
  191. if (IS_ERR(priv->syscon) && np->parent)
  192. priv->syscon = syscon_node_to_regmap(np->parent);
  193. if (IS_ERR(priv->syscon))
  194. return PTR_ERR(priv->syscon);
  195. ret = of_property_read_u32_index(np, "gpio,syscon-dev", 1,
  196. &priv->dreg_offset);
  197. if (ret)
  198. dev_err(dev, "can't read the data register offset!\n");
  199. priv->dreg_offset <<= 3;
  200. ret = of_property_read_u32_index(np, "gpio,syscon-dev", 2,
  201. &priv->dir_reg_offset);
  202. if (ret)
  203. dev_dbg(dev, "can't read the dir register offset!\n");
  204. priv->dir_reg_offset <<= 3;
  205. }
  206. priv->chip.parent = dev;
  207. priv->chip.owner = THIS_MODULE;
  208. priv->chip.label = dev_name(dev);
  209. priv->chip.base = -1;
  210. priv->chip.ngpio = priv->data->bit_count;
  211. priv->chip.get = syscon_gpio_get;
  212. if (priv->data->flags & GPIO_SYSCON_FEAT_IN)
  213. priv->chip.direction_input = syscon_gpio_dir_in;
  214. if (priv->data->flags & GPIO_SYSCON_FEAT_OUT) {
  215. priv->chip.set = priv->data->set ? : syscon_gpio_set;
  216. priv->chip.direction_output = syscon_gpio_dir_out;
  217. }
  218. platform_set_drvdata(pdev, priv);
  219. return devm_gpiochip_add_data(&pdev->dev, &priv->chip, priv);
  220. }
  221. static struct platform_driver syscon_gpio_driver = {
  222. .driver = {
  223. .name = "gpio-syscon",
  224. .of_match_table = syscon_gpio_ids,
  225. },
  226. .probe = syscon_gpio_probe,
  227. };
  228. module_platform_driver(syscon_gpio_driver);
  229. MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
  230. MODULE_DESCRIPTION("SYSCON GPIO driver");
  231. MODULE_LICENSE("GPL");