gpio-stp-xway.c 9.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. *
  4. * Copyright (C) 2012 John Crispin <john@phrozen.org>
  5. */
  6. #include <linux/slab.h>
  7. #include <linux/init.h>
  8. #include <linux/module.h>
  9. #include <linux/types.h>
  10. #include <linux/of_platform.h>
  11. #include <linux/mutex.h>
  12. #include <linux/gpio/driver.h>
  13. #include <linux/io.h>
  14. #include <linux/clk.h>
  15. #include <linux/err.h>
  16. /*
  17. * The Serial To Parallel (STP) is found on MIPS based Lantiq socs. It is a
  18. * peripheral controller used to drive external shift register cascades. At most
  19. * 3 groups of 8 bits can be driven. The hardware is able to allow the DSL modem
  20. * to drive the 2 LSBs of the cascade automatically.
  21. */
  22. /* control register 0 */
  23. #define XWAY_STP_CON0 0x00
  24. /* control register 1 */
  25. #define XWAY_STP_CON1 0x04
  26. /* data register 0 */
  27. #define XWAY_STP_CPU0 0x08
  28. /* data register 1 */
  29. #define XWAY_STP_CPU1 0x0C
  30. /* access register */
  31. #define XWAY_STP_AR 0x10
  32. /* software or hardware update select bit */
  33. #define XWAY_STP_CON_SWU BIT(31)
  34. /* automatic update rates */
  35. #define XWAY_STP_2HZ 0
  36. #define XWAY_STP_4HZ BIT(23)
  37. #define XWAY_STP_8HZ BIT(24)
  38. #define XWAY_STP_10HZ (BIT(24) | BIT(23))
  39. #define XWAY_STP_SPEED_MASK (BIT(23) | BIT(24) | BIT(25) | BIT(26) | BIT(27))
  40. #define XWAY_STP_FPIS_VALUE BIT(21)
  41. #define XWAY_STP_FPIS_MASK (BIT(20) | BIT(21))
  42. /* clock source for automatic update */
  43. #define XWAY_STP_UPD_FPI BIT(31)
  44. #define XWAY_STP_UPD_MASK (BIT(31) | BIT(30))
  45. /* let the adsl core drive the 2 LSBs */
  46. #define XWAY_STP_ADSL_SHIFT 24
  47. #define XWAY_STP_ADSL_MASK 0x3
  48. /* 2 groups of 3 bits can be driven by the phys */
  49. #define XWAY_STP_PHY_MASK 0x7
  50. #define XWAY_STP_PHY1_SHIFT 27
  51. #define XWAY_STP_PHY2_SHIFT 3
  52. #define XWAY_STP_PHY3_SHIFT 6
  53. #define XWAY_STP_PHY4_SHIFT 15
  54. /* STP has 3 groups of 8 bits */
  55. #define XWAY_STP_GROUP0 BIT(0)
  56. #define XWAY_STP_GROUP1 BIT(1)
  57. #define XWAY_STP_GROUP2 BIT(2)
  58. #define XWAY_STP_GROUP_MASK (0x7)
  59. /* Edge configuration bits */
  60. #define XWAY_STP_FALLING BIT(26)
  61. #define XWAY_STP_EDGE_MASK BIT(26)
  62. #define xway_stp_r32(m, reg) __raw_readl(m + reg)
  63. #define xway_stp_w32(m, val, reg) __raw_writel(val, m + reg)
  64. #define xway_stp_w32_mask(m, clear, set, reg) \
  65. xway_stp_w32(m, (xway_stp_r32(m, reg) & ~(clear)) | (set), reg)
  66. struct xway_stp {
  67. struct gpio_chip gc;
  68. void __iomem *virt;
  69. u32 edge; /* rising or falling edge triggered shift register */
  70. u32 shadow; /* shadow the shift registers state */
  71. u8 groups; /* we can drive 1-3 groups of 8bit each */
  72. u8 dsl; /* the 2 LSBs can be driven by the dsl core */
  73. u8 phy1; /* 3 bits can be driven by phy1 */
  74. u8 phy2; /* 3 bits can be driven by phy2 */
  75. u8 phy3; /* 3 bits can be driven by phy3 */
  76. u8 phy4; /* 3 bits can be driven by phy4 */
  77. u8 reserved; /* mask out the hw driven bits in gpio_request */
  78. };
  79. /**
  80. * xway_stp_get() - gpio_chip->get - get gpios.
  81. * @gc: Pointer to gpio_chip device structure.
  82. * @gpio: GPIO signal number.
  83. *
  84. * Gets the shadow value.
  85. */
  86. static int xway_stp_get(struct gpio_chip *gc, unsigned int gpio)
  87. {
  88. struct xway_stp *chip = gpiochip_get_data(gc);
  89. return (xway_stp_r32(chip->virt, XWAY_STP_CPU0) & BIT(gpio));
  90. }
  91. /**
  92. * xway_stp_set() - gpio_chip->set - set gpios.
  93. * @gc: Pointer to gpio_chip device structure.
  94. * @gpio: GPIO signal number.
  95. * @val: Value to be written to specified signal.
  96. *
  97. * Set the shadow value and call ltq_ebu_apply.
  98. */
  99. static void xway_stp_set(struct gpio_chip *gc, unsigned gpio, int val)
  100. {
  101. struct xway_stp *chip = gpiochip_get_data(gc);
  102. if (val)
  103. chip->shadow |= BIT(gpio);
  104. else
  105. chip->shadow &= ~BIT(gpio);
  106. xway_stp_w32(chip->virt, chip->shadow, XWAY_STP_CPU0);
  107. if (!chip->reserved)
  108. xway_stp_w32_mask(chip->virt, 0, XWAY_STP_CON_SWU, XWAY_STP_CON0);
  109. }
  110. /**
  111. * xway_stp_dir_out() - gpio_chip->dir_out - set gpio direction.
  112. * @gc: Pointer to gpio_chip device structure.
  113. * @gpio: GPIO signal number.
  114. * @val: Value to be written to specified signal.
  115. *
  116. * Same as xway_stp_set, always returns 0.
  117. */
  118. static int xway_stp_dir_out(struct gpio_chip *gc, unsigned gpio, int val)
  119. {
  120. xway_stp_set(gc, gpio, val);
  121. return 0;
  122. }
  123. /**
  124. * xway_stp_request() - gpio_chip->request
  125. * @gc: Pointer to gpio_chip device structure.
  126. * @gpio: GPIO signal number.
  127. *
  128. * We mask out the HW driven pins
  129. */
  130. static int xway_stp_request(struct gpio_chip *gc, unsigned gpio)
  131. {
  132. struct xway_stp *chip = gpiochip_get_data(gc);
  133. if ((gpio < 8) && (chip->reserved & BIT(gpio))) {
  134. dev_err(gc->parent, "GPIO %d is driven by hardware\n", gpio);
  135. return -ENODEV;
  136. }
  137. return 0;
  138. }
  139. /**
  140. * xway_stp_hw_init() - Configure the STP unit and enable the clock gate
  141. * @chip: Pointer to the xway_stp chip structure
  142. */
  143. static void xway_stp_hw_init(struct xway_stp *chip)
  144. {
  145. /* sane defaults */
  146. xway_stp_w32(chip->virt, 0, XWAY_STP_AR);
  147. xway_stp_w32(chip->virt, 0, XWAY_STP_CPU0);
  148. xway_stp_w32(chip->virt, 0, XWAY_STP_CPU1);
  149. xway_stp_w32(chip->virt, XWAY_STP_CON_SWU, XWAY_STP_CON0);
  150. xway_stp_w32(chip->virt, 0, XWAY_STP_CON1);
  151. /* apply edge trigger settings for the shift register */
  152. xway_stp_w32_mask(chip->virt, XWAY_STP_EDGE_MASK,
  153. chip->edge, XWAY_STP_CON0);
  154. /* apply led group settings */
  155. xway_stp_w32_mask(chip->virt, XWAY_STP_GROUP_MASK,
  156. chip->groups, XWAY_STP_CON1);
  157. /* tell the hardware which pins are controlled by the dsl modem */
  158. xway_stp_w32_mask(chip->virt,
  159. XWAY_STP_ADSL_MASK << XWAY_STP_ADSL_SHIFT,
  160. chip->dsl << XWAY_STP_ADSL_SHIFT,
  161. XWAY_STP_CON0);
  162. /* tell the hardware which pins are controlled by the phys */
  163. xway_stp_w32_mask(chip->virt,
  164. XWAY_STP_PHY_MASK << XWAY_STP_PHY1_SHIFT,
  165. chip->phy1 << XWAY_STP_PHY1_SHIFT,
  166. XWAY_STP_CON0);
  167. xway_stp_w32_mask(chip->virt,
  168. XWAY_STP_PHY_MASK << XWAY_STP_PHY2_SHIFT,
  169. chip->phy2 << XWAY_STP_PHY2_SHIFT,
  170. XWAY_STP_CON1);
  171. if (of_machine_is_compatible("lantiq,grx390")
  172. || of_machine_is_compatible("lantiq,ar10")) {
  173. xway_stp_w32_mask(chip->virt,
  174. XWAY_STP_PHY_MASK << XWAY_STP_PHY3_SHIFT,
  175. chip->phy3 << XWAY_STP_PHY3_SHIFT,
  176. XWAY_STP_CON1);
  177. }
  178. if (of_machine_is_compatible("lantiq,grx390")) {
  179. xway_stp_w32_mask(chip->virt,
  180. XWAY_STP_PHY_MASK << XWAY_STP_PHY4_SHIFT,
  181. chip->phy4 << XWAY_STP_PHY4_SHIFT,
  182. XWAY_STP_CON1);
  183. }
  184. /* mask out the hw driven bits in gpio_request */
  185. chip->reserved = (chip->phy4 << 11) | (chip->phy3 << 8) | (chip->phy2 << 5)
  186. | (chip->phy1 << 2) | chip->dsl;
  187. /*
  188. * if we have pins that are driven by hw, we need to tell the stp what
  189. * clock to use as a timer.
  190. */
  191. if (chip->reserved) {
  192. xway_stp_w32_mask(chip->virt, XWAY_STP_UPD_MASK,
  193. XWAY_STP_UPD_FPI, XWAY_STP_CON1);
  194. xway_stp_w32_mask(chip->virt, XWAY_STP_SPEED_MASK,
  195. XWAY_STP_10HZ, XWAY_STP_CON1);
  196. xway_stp_w32_mask(chip->virt, XWAY_STP_FPIS_MASK,
  197. XWAY_STP_FPIS_VALUE, XWAY_STP_CON1);
  198. }
  199. }
  200. static int xway_stp_probe(struct platform_device *pdev)
  201. {
  202. u32 shadow, groups, dsl, phy;
  203. struct xway_stp *chip;
  204. struct clk *clk;
  205. int ret = 0;
  206. chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
  207. if (!chip)
  208. return -ENOMEM;
  209. chip->virt = devm_platform_ioremap_resource(pdev, 0);
  210. if (IS_ERR(chip->virt))
  211. return PTR_ERR(chip->virt);
  212. chip->gc.parent = &pdev->dev;
  213. chip->gc.label = "stp-xway";
  214. chip->gc.direction_output = xway_stp_dir_out;
  215. chip->gc.get = xway_stp_get;
  216. chip->gc.set = xway_stp_set;
  217. chip->gc.request = xway_stp_request;
  218. chip->gc.base = -1;
  219. chip->gc.owner = THIS_MODULE;
  220. /* store the shadow value if one was passed by the devicetree */
  221. if (!of_property_read_u32(pdev->dev.of_node, "lantiq,shadow", &shadow))
  222. chip->shadow = shadow;
  223. /* find out which gpio groups should be enabled */
  224. if (!of_property_read_u32(pdev->dev.of_node, "lantiq,groups", &groups))
  225. chip->groups = groups & XWAY_STP_GROUP_MASK;
  226. else
  227. chip->groups = XWAY_STP_GROUP0;
  228. chip->gc.ngpio = fls(chip->groups) * 8;
  229. /* find out which gpios are controlled by the dsl core */
  230. if (!of_property_read_u32(pdev->dev.of_node, "lantiq,dsl", &dsl))
  231. chip->dsl = dsl & XWAY_STP_ADSL_MASK;
  232. /* find out which gpios are controlled by the phys */
  233. if (of_machine_is_compatible("lantiq,ar9") ||
  234. of_machine_is_compatible("lantiq,gr9") ||
  235. of_machine_is_compatible("lantiq,vr9") ||
  236. of_machine_is_compatible("lantiq,ar10") ||
  237. of_machine_is_compatible("lantiq,grx390")) {
  238. if (!of_property_read_u32(pdev->dev.of_node, "lantiq,phy1", &phy))
  239. chip->phy1 = phy & XWAY_STP_PHY_MASK;
  240. if (!of_property_read_u32(pdev->dev.of_node, "lantiq,phy2", &phy))
  241. chip->phy2 = phy & XWAY_STP_PHY_MASK;
  242. }
  243. if (of_machine_is_compatible("lantiq,ar10") ||
  244. of_machine_is_compatible("lantiq,grx390")) {
  245. if (!of_property_read_u32(pdev->dev.of_node, "lantiq,phy3", &phy))
  246. chip->phy3 = phy & XWAY_STP_PHY_MASK;
  247. }
  248. if (of_machine_is_compatible("lantiq,grx390")) {
  249. if (!of_property_read_u32(pdev->dev.of_node, "lantiq,phy4", &phy))
  250. chip->phy4 = phy & XWAY_STP_PHY_MASK;
  251. }
  252. /* check which edge trigger we should use, default to a falling edge */
  253. if (!of_find_property(pdev->dev.of_node, "lantiq,rising", NULL))
  254. chip->edge = XWAY_STP_FALLING;
  255. clk = devm_clk_get(&pdev->dev, NULL);
  256. if (IS_ERR(clk)) {
  257. dev_err(&pdev->dev, "Failed to get clock\n");
  258. return PTR_ERR(clk);
  259. }
  260. ret = clk_prepare_enable(clk);
  261. if (ret)
  262. return ret;
  263. xway_stp_hw_init(chip);
  264. ret = devm_gpiochip_add_data(&pdev->dev, &chip->gc, chip);
  265. if (ret) {
  266. clk_disable_unprepare(clk);
  267. return ret;
  268. }
  269. dev_info(&pdev->dev, "Init done\n");
  270. return 0;
  271. }
  272. static const struct of_device_id xway_stp_match[] = {
  273. { .compatible = "lantiq,gpio-stp-xway" },
  274. {},
  275. };
  276. MODULE_DEVICE_TABLE(of, xway_stp_match);
  277. static struct platform_driver xway_stp_driver = {
  278. .probe = xway_stp_probe,
  279. .driver = {
  280. .name = "gpio-stp-xway",
  281. .of_match_table = xway_stp_match,
  282. },
  283. };
  284. static int __init xway_stp_init(void)
  285. {
  286. return platform_driver_register(&xway_stp_driver);
  287. }
  288. subsys_initcall(xway_stp_init);