gpio-stmpe.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) ST-Ericsson SA 2010
  4. *
  5. * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
  6. */
  7. #include <linux/init.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/slab.h>
  10. #include <linux/gpio/driver.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/of.h>
  13. #include <linux/mfd/stmpe.h>
  14. #include <linux/seq_file.h>
  15. #include <linux/bitops.h>
  16. /*
  17. * These registers are modified under the irq bus lock and cached to avoid
  18. * unnecessary writes in bus_sync_unlock.
  19. */
  20. enum { REG_RE, REG_FE, REG_IE };
  21. enum { LSB, CSB, MSB };
  22. #define CACHE_NR_REGS 3
  23. /* No variant has more than 24 GPIOs */
  24. #define CACHE_NR_BANKS (24 / 8)
  25. struct stmpe_gpio {
  26. struct gpio_chip chip;
  27. struct stmpe *stmpe;
  28. struct device *dev;
  29. struct mutex irq_lock;
  30. u32 norequest_mask;
  31. /* Caches of interrupt control registers for bus_lock */
  32. u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
  33. u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
  34. };
  35. static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
  36. {
  37. struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
  38. struct stmpe *stmpe = stmpe_gpio->stmpe;
  39. u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB + (offset / 8)];
  40. u8 mask = BIT(offset % 8);
  41. int ret;
  42. ret = stmpe_reg_read(stmpe, reg);
  43. if (ret < 0)
  44. return ret;
  45. return !!(ret & mask);
  46. }
  47. static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
  48. {
  49. struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
  50. struct stmpe *stmpe = stmpe_gpio->stmpe;
  51. int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
  52. u8 reg = stmpe->regs[which + (offset / 8)];
  53. u8 mask = BIT(offset % 8);
  54. /*
  55. * Some variants have single register for gpio set/clear functionality.
  56. * For them we need to write 0 to clear and 1 to set.
  57. */
  58. if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB])
  59. stmpe_set_bits(stmpe, reg, mask, val ? mask : 0);
  60. else
  61. stmpe_reg_write(stmpe, reg, mask);
  62. }
  63. static int stmpe_gpio_get_direction(struct gpio_chip *chip,
  64. unsigned offset)
  65. {
  66. struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
  67. struct stmpe *stmpe = stmpe_gpio->stmpe;
  68. u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
  69. u8 mask = BIT(offset % 8);
  70. int ret;
  71. ret = stmpe_reg_read(stmpe, reg);
  72. if (ret < 0)
  73. return ret;
  74. if (ret & mask)
  75. return GPIO_LINE_DIRECTION_OUT;
  76. return GPIO_LINE_DIRECTION_IN;
  77. }
  78. static int stmpe_gpio_direction_output(struct gpio_chip *chip,
  79. unsigned offset, int val)
  80. {
  81. struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
  82. struct stmpe *stmpe = stmpe_gpio->stmpe;
  83. u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
  84. u8 mask = BIT(offset % 8);
  85. stmpe_gpio_set(chip, offset, val);
  86. return stmpe_set_bits(stmpe, reg, mask, mask);
  87. }
  88. static int stmpe_gpio_direction_input(struct gpio_chip *chip,
  89. unsigned offset)
  90. {
  91. struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
  92. struct stmpe *stmpe = stmpe_gpio->stmpe;
  93. u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
  94. u8 mask = BIT(offset % 8);
  95. return stmpe_set_bits(stmpe, reg, mask, 0);
  96. }
  97. static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
  98. {
  99. struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
  100. struct stmpe *stmpe = stmpe_gpio->stmpe;
  101. if (stmpe_gpio->norequest_mask & BIT(offset))
  102. return -EINVAL;
  103. return stmpe_set_altfunc(stmpe, BIT(offset), STMPE_BLOCK_GPIO);
  104. }
  105. static const struct gpio_chip template_chip = {
  106. .label = "stmpe",
  107. .owner = THIS_MODULE,
  108. .get_direction = stmpe_gpio_get_direction,
  109. .direction_input = stmpe_gpio_direction_input,
  110. .get = stmpe_gpio_get,
  111. .direction_output = stmpe_gpio_direction_output,
  112. .set = stmpe_gpio_set,
  113. .request = stmpe_gpio_request,
  114. .can_sleep = true,
  115. };
  116. static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
  117. {
  118. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  119. struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
  120. int offset = d->hwirq;
  121. int regoffset = offset / 8;
  122. int mask = BIT(offset % 8);
  123. if (type & IRQ_TYPE_LEVEL_LOW || type & IRQ_TYPE_LEVEL_HIGH)
  124. return -EINVAL;
  125. /* STMPE801 and STMPE 1600 don't have RE and FE registers */
  126. if (stmpe_gpio->stmpe->partnum == STMPE801 ||
  127. stmpe_gpio->stmpe->partnum == STMPE1600)
  128. return 0;
  129. if (type & IRQ_TYPE_EDGE_RISING)
  130. stmpe_gpio->regs[REG_RE][regoffset] |= mask;
  131. else
  132. stmpe_gpio->regs[REG_RE][regoffset] &= ~mask;
  133. if (type & IRQ_TYPE_EDGE_FALLING)
  134. stmpe_gpio->regs[REG_FE][regoffset] |= mask;
  135. else
  136. stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;
  137. return 0;
  138. }
  139. static void stmpe_gpio_irq_lock(struct irq_data *d)
  140. {
  141. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  142. struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
  143. mutex_lock(&stmpe_gpio->irq_lock);
  144. }
  145. static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
  146. {
  147. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  148. struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
  149. struct stmpe *stmpe = stmpe_gpio->stmpe;
  150. int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
  151. static const u8 regmap[CACHE_NR_REGS][CACHE_NR_BANKS] = {
  152. [REG_RE][LSB] = STMPE_IDX_GPRER_LSB,
  153. [REG_RE][CSB] = STMPE_IDX_GPRER_CSB,
  154. [REG_RE][MSB] = STMPE_IDX_GPRER_MSB,
  155. [REG_FE][LSB] = STMPE_IDX_GPFER_LSB,
  156. [REG_FE][CSB] = STMPE_IDX_GPFER_CSB,
  157. [REG_FE][MSB] = STMPE_IDX_GPFER_MSB,
  158. [REG_IE][LSB] = STMPE_IDX_IEGPIOR_LSB,
  159. [REG_IE][CSB] = STMPE_IDX_IEGPIOR_CSB,
  160. [REG_IE][MSB] = STMPE_IDX_IEGPIOR_MSB,
  161. };
  162. int i, j;
  163. /*
  164. * STMPE1600: to be able to get IRQ from pins,
  165. * a read must be done on GPMR register, or a write in
  166. * GPSR or GPCR registers
  167. */
  168. if (stmpe->partnum == STMPE1600) {
  169. stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_LSB]);
  170. stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_CSB]);
  171. }
  172. for (i = 0; i < CACHE_NR_REGS; i++) {
  173. /* STMPE801 and STMPE1600 don't have RE and FE registers */
  174. if ((stmpe->partnum == STMPE801 ||
  175. stmpe->partnum == STMPE1600) &&
  176. (i != REG_IE))
  177. continue;
  178. for (j = 0; j < num_banks; j++) {
  179. u8 old = stmpe_gpio->oldregs[i][j];
  180. u8 new = stmpe_gpio->regs[i][j];
  181. if (new == old)
  182. continue;
  183. stmpe_gpio->oldregs[i][j] = new;
  184. stmpe_reg_write(stmpe, stmpe->regs[regmap[i][j]], new);
  185. }
  186. }
  187. mutex_unlock(&stmpe_gpio->irq_lock);
  188. }
  189. static void stmpe_gpio_irq_mask(struct irq_data *d)
  190. {
  191. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  192. struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
  193. int offset = d->hwirq;
  194. int regoffset = offset / 8;
  195. int mask = BIT(offset % 8);
  196. stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
  197. }
  198. static void stmpe_gpio_irq_unmask(struct irq_data *d)
  199. {
  200. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  201. struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
  202. int offset = d->hwirq;
  203. int regoffset = offset / 8;
  204. int mask = BIT(offset % 8);
  205. stmpe_gpio->regs[REG_IE][regoffset] |= mask;
  206. }
  207. static void stmpe_dbg_show_one(struct seq_file *s,
  208. struct gpio_chip *gc,
  209. unsigned offset, unsigned gpio)
  210. {
  211. struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
  212. struct stmpe *stmpe = stmpe_gpio->stmpe;
  213. const char *label = gpiochip_is_requested(gc, offset);
  214. bool val = !!stmpe_gpio_get(gc, offset);
  215. u8 bank = offset / 8;
  216. u8 dir_reg = stmpe->regs[STMPE_IDX_GPDR_LSB + bank];
  217. u8 mask = BIT(offset % 8);
  218. int ret;
  219. u8 dir;
  220. ret = stmpe_reg_read(stmpe, dir_reg);
  221. if (ret < 0)
  222. return;
  223. dir = !!(ret & mask);
  224. if (dir) {
  225. seq_printf(s, " gpio-%-3d (%-20.20s) out %s",
  226. gpio, label ?: "(none)",
  227. val ? "hi" : "lo");
  228. } else {
  229. u8 edge_det_reg;
  230. u8 rise_reg;
  231. u8 fall_reg;
  232. u8 irqen_reg;
  233. static const char * const edge_det_values[] = {
  234. "edge-inactive",
  235. "edge-asserted",
  236. "not-supported"
  237. };
  238. static const char * const rise_values[] = {
  239. "no-rising-edge-detection",
  240. "rising-edge-detection",
  241. "not-supported"
  242. };
  243. static const char * const fall_values[] = {
  244. "no-falling-edge-detection",
  245. "falling-edge-detection",
  246. "not-supported"
  247. };
  248. #define NOT_SUPPORTED_IDX 2
  249. u8 edge_det = NOT_SUPPORTED_IDX;
  250. u8 rise = NOT_SUPPORTED_IDX;
  251. u8 fall = NOT_SUPPORTED_IDX;
  252. bool irqen;
  253. switch (stmpe->partnum) {
  254. case STMPE610:
  255. case STMPE811:
  256. case STMPE1601:
  257. case STMPE2401:
  258. case STMPE2403:
  259. edge_det_reg = stmpe->regs[STMPE_IDX_GPEDR_LSB + bank];
  260. ret = stmpe_reg_read(stmpe, edge_det_reg);
  261. if (ret < 0)
  262. return;
  263. edge_det = !!(ret & mask);
  264. fallthrough;
  265. case STMPE1801:
  266. rise_reg = stmpe->regs[STMPE_IDX_GPRER_LSB + bank];
  267. fall_reg = stmpe->regs[STMPE_IDX_GPFER_LSB + bank];
  268. ret = stmpe_reg_read(stmpe, rise_reg);
  269. if (ret < 0)
  270. return;
  271. rise = !!(ret & mask);
  272. ret = stmpe_reg_read(stmpe, fall_reg);
  273. if (ret < 0)
  274. return;
  275. fall = !!(ret & mask);
  276. fallthrough;
  277. case STMPE801:
  278. case STMPE1600:
  279. irqen_reg = stmpe->regs[STMPE_IDX_IEGPIOR_LSB + bank];
  280. break;
  281. default:
  282. return;
  283. }
  284. ret = stmpe_reg_read(stmpe, irqen_reg);
  285. if (ret < 0)
  286. return;
  287. irqen = !!(ret & mask);
  288. seq_printf(s, " gpio-%-3d (%-20.20s) in %s %13s %13s %25s %25s",
  289. gpio, label ?: "(none)",
  290. val ? "hi" : "lo",
  291. edge_det_values[edge_det],
  292. irqen ? "IRQ-enabled" : "IRQ-disabled",
  293. rise_values[rise],
  294. fall_values[fall]);
  295. }
  296. }
  297. static void stmpe_dbg_show(struct seq_file *s, struct gpio_chip *gc)
  298. {
  299. unsigned i;
  300. unsigned gpio = gc->base;
  301. for (i = 0; i < gc->ngpio; i++, gpio++) {
  302. stmpe_dbg_show_one(s, gc, i, gpio);
  303. seq_putc(s, '\n');
  304. }
  305. }
  306. static struct irq_chip stmpe_gpio_irq_chip = {
  307. .name = "stmpe-gpio",
  308. .irq_bus_lock = stmpe_gpio_irq_lock,
  309. .irq_bus_sync_unlock = stmpe_gpio_irq_sync_unlock,
  310. .irq_mask = stmpe_gpio_irq_mask,
  311. .irq_unmask = stmpe_gpio_irq_unmask,
  312. .irq_set_type = stmpe_gpio_irq_set_type,
  313. };
  314. #define MAX_GPIOS 24
  315. static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
  316. {
  317. struct stmpe_gpio *stmpe_gpio = dev;
  318. struct stmpe *stmpe = stmpe_gpio->stmpe;
  319. u8 statmsbreg;
  320. int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
  321. u8 status[DIV_ROUND_UP(MAX_GPIOS, 8)];
  322. int ret;
  323. int i;
  324. /*
  325. * the stmpe_block_read() call below, imposes to set statmsbreg
  326. * with the register located at the lowest address. As STMPE1600
  327. * variant is the only one which respect registers address's order
  328. * (LSB regs located at lowest address than MSB ones) whereas all
  329. * the others have a registers layout with MSB located before the
  330. * LSB regs.
  331. */
  332. if (stmpe->partnum == STMPE1600)
  333. statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_LSB];
  334. else
  335. statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];
  336. ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
  337. if (ret < 0)
  338. return IRQ_NONE;
  339. for (i = 0; i < num_banks; i++) {
  340. int bank = (stmpe_gpio->stmpe->partnum == STMPE1600) ? i :
  341. num_banks - i - 1;
  342. unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
  343. unsigned int stat = status[i];
  344. stat &= enabled;
  345. if (!stat)
  346. continue;
  347. while (stat) {
  348. int bit = __ffs(stat);
  349. int line = bank * 8 + bit;
  350. int child_irq = irq_find_mapping(stmpe_gpio->chip.irq.domain,
  351. line);
  352. handle_nested_irq(child_irq);
  353. stat &= ~BIT(bit);
  354. }
  355. /*
  356. * interrupt status register write has no effect on
  357. * 801/1801/1600, bits are cleared when read.
  358. * Edge detect register is not present on 801/1600/1801
  359. */
  360. if (stmpe->partnum != STMPE801 && stmpe->partnum != STMPE1600 &&
  361. stmpe->partnum != STMPE1801) {
  362. stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
  363. stmpe_reg_write(stmpe,
  364. stmpe->regs[STMPE_IDX_GPEDR_MSB] + i,
  365. status[i]);
  366. }
  367. }
  368. return IRQ_HANDLED;
  369. }
  370. static void stmpe_init_irq_valid_mask(struct gpio_chip *gc,
  371. unsigned long *valid_mask,
  372. unsigned int ngpios)
  373. {
  374. struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
  375. int i;
  376. if (!stmpe_gpio->norequest_mask)
  377. return;
  378. /* Forbid unused lines to be mapped as IRQs */
  379. for (i = 0; i < sizeof(u32); i++) {
  380. if (stmpe_gpio->norequest_mask & BIT(i))
  381. clear_bit(i, valid_mask);
  382. }
  383. }
  384. static int stmpe_gpio_probe(struct platform_device *pdev)
  385. {
  386. struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent);
  387. struct device_node *np = pdev->dev.of_node;
  388. struct stmpe_gpio *stmpe_gpio;
  389. int ret, irq;
  390. if (stmpe->num_gpios > MAX_GPIOS) {
  391. dev_err(&pdev->dev, "Need to increase maximum GPIO number\n");
  392. return -EINVAL;
  393. }
  394. stmpe_gpio = kzalloc(sizeof(*stmpe_gpio), GFP_KERNEL);
  395. if (!stmpe_gpio)
  396. return -ENOMEM;
  397. mutex_init(&stmpe_gpio->irq_lock);
  398. stmpe_gpio->dev = &pdev->dev;
  399. stmpe_gpio->stmpe = stmpe;
  400. stmpe_gpio->chip = template_chip;
  401. stmpe_gpio->chip.ngpio = stmpe->num_gpios;
  402. stmpe_gpio->chip.parent = &pdev->dev;
  403. stmpe_gpio->chip.of_node = np;
  404. stmpe_gpio->chip.base = -1;
  405. /*
  406. * REVISIT: this makes sure the valid mask gets allocated and
  407. * filled in when adding the gpio_chip, but the rest of the
  408. * gpio_irqchip is still filled in using the old method
  409. * in gpiochip_irqchip_add_nested() so clean this up once we
  410. * get the gpio_irqchip to initialize while adding the
  411. * gpio_chip also for threaded irqchips.
  412. */
  413. stmpe_gpio->chip.irq.init_valid_mask = stmpe_init_irq_valid_mask;
  414. if (IS_ENABLED(CONFIG_DEBUG_FS))
  415. stmpe_gpio->chip.dbg_show = stmpe_dbg_show;
  416. of_property_read_u32(np, "st,norequest-mask",
  417. &stmpe_gpio->norequest_mask);
  418. irq = platform_get_irq(pdev, 0);
  419. if (irq < 0)
  420. dev_info(&pdev->dev,
  421. "device configured in no-irq mode: "
  422. "irqs are not available\n");
  423. ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
  424. if (ret)
  425. goto out_free;
  426. if (irq > 0) {
  427. struct gpio_irq_chip *girq;
  428. ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
  429. stmpe_gpio_irq, IRQF_ONESHOT,
  430. "stmpe-gpio", stmpe_gpio);
  431. if (ret) {
  432. dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
  433. goto out_disable;
  434. }
  435. girq = &stmpe_gpio->chip.irq;
  436. girq->chip = &stmpe_gpio_irq_chip;
  437. /* This will let us handle the parent IRQ in the driver */
  438. girq->parent_handler = NULL;
  439. girq->num_parents = 0;
  440. girq->parents = NULL;
  441. girq->default_type = IRQ_TYPE_NONE;
  442. girq->handler = handle_simple_irq;
  443. girq->threaded = true;
  444. }
  445. ret = gpiochip_add_data(&stmpe_gpio->chip, stmpe_gpio);
  446. if (ret) {
  447. dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
  448. goto out_disable;
  449. }
  450. platform_set_drvdata(pdev, stmpe_gpio);
  451. return 0;
  452. out_disable:
  453. stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
  454. gpiochip_remove(&stmpe_gpio->chip);
  455. out_free:
  456. kfree(stmpe_gpio);
  457. return ret;
  458. }
  459. static struct platform_driver stmpe_gpio_driver = {
  460. .driver = {
  461. .suppress_bind_attrs = true,
  462. .name = "stmpe-gpio",
  463. },
  464. .probe = stmpe_gpio_probe,
  465. };
  466. static int __init stmpe_gpio_init(void)
  467. {
  468. return platform_driver_register(&stmpe_gpio_driver);
  469. }
  470. subsys_initcall(stmpe_gpio_init);