gpio-sprd.c 7.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2018 Spreadtrum Communications Inc.
  4. * Copyright (C) 2018 Linaro Ltd.
  5. */
  6. #include <linux/bitops.h>
  7. #include <linux/gpio/driver.h>
  8. #include <linux/kernel.h>
  9. #include <linux/module.h>
  10. #include <linux/of_device.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/spinlock.h>
  13. /* GPIO registers definition */
  14. #define SPRD_GPIO_DATA 0x0
  15. #define SPRD_GPIO_DMSK 0x4
  16. #define SPRD_GPIO_DIR 0x8
  17. #define SPRD_GPIO_IS 0xc
  18. #define SPRD_GPIO_IBE 0x10
  19. #define SPRD_GPIO_IEV 0x14
  20. #define SPRD_GPIO_IE 0x18
  21. #define SPRD_GPIO_RIS 0x1c
  22. #define SPRD_GPIO_MIS 0x20
  23. #define SPRD_GPIO_IC 0x24
  24. #define SPRD_GPIO_INEN 0x28
  25. /* We have 16 banks GPIOs and each bank contain 16 GPIOs */
  26. #define SPRD_GPIO_BANK_NR 16
  27. #define SPRD_GPIO_NR 256
  28. #define SPRD_GPIO_BANK_SIZE 0x80
  29. #define SPRD_GPIO_BANK_MASK GENMASK(15, 0)
  30. #define SPRD_GPIO_BIT(x) ((x) & (SPRD_GPIO_BANK_NR - 1))
  31. struct sprd_gpio {
  32. struct gpio_chip chip;
  33. void __iomem *base;
  34. spinlock_t lock;
  35. int irq;
  36. };
  37. static inline void __iomem *sprd_gpio_bank_base(struct sprd_gpio *sprd_gpio,
  38. unsigned int bank)
  39. {
  40. return sprd_gpio->base + SPRD_GPIO_BANK_SIZE * bank;
  41. }
  42. static void sprd_gpio_update(struct gpio_chip *chip, unsigned int offset,
  43. u16 reg, int val)
  44. {
  45. struct sprd_gpio *sprd_gpio = gpiochip_get_data(chip);
  46. void __iomem *base = sprd_gpio_bank_base(sprd_gpio,
  47. offset / SPRD_GPIO_BANK_NR);
  48. unsigned long flags;
  49. u32 tmp;
  50. spin_lock_irqsave(&sprd_gpio->lock, flags);
  51. tmp = readl_relaxed(base + reg);
  52. if (val)
  53. tmp |= BIT(SPRD_GPIO_BIT(offset));
  54. else
  55. tmp &= ~BIT(SPRD_GPIO_BIT(offset));
  56. writel_relaxed(tmp, base + reg);
  57. spin_unlock_irqrestore(&sprd_gpio->lock, flags);
  58. }
  59. static int sprd_gpio_read(struct gpio_chip *chip, unsigned int offset, u16 reg)
  60. {
  61. struct sprd_gpio *sprd_gpio = gpiochip_get_data(chip);
  62. void __iomem *base = sprd_gpio_bank_base(sprd_gpio,
  63. offset / SPRD_GPIO_BANK_NR);
  64. return !!(readl_relaxed(base + reg) & BIT(SPRD_GPIO_BIT(offset)));
  65. }
  66. static int sprd_gpio_request(struct gpio_chip *chip, unsigned int offset)
  67. {
  68. sprd_gpio_update(chip, offset, SPRD_GPIO_DMSK, 1);
  69. return 0;
  70. }
  71. static void sprd_gpio_free(struct gpio_chip *chip, unsigned int offset)
  72. {
  73. sprd_gpio_update(chip, offset, SPRD_GPIO_DMSK, 0);
  74. }
  75. static int sprd_gpio_direction_input(struct gpio_chip *chip,
  76. unsigned int offset)
  77. {
  78. sprd_gpio_update(chip, offset, SPRD_GPIO_DIR, 0);
  79. sprd_gpio_update(chip, offset, SPRD_GPIO_INEN, 1);
  80. return 0;
  81. }
  82. static int sprd_gpio_direction_output(struct gpio_chip *chip,
  83. unsigned int offset, int value)
  84. {
  85. sprd_gpio_update(chip, offset, SPRD_GPIO_DIR, 1);
  86. sprd_gpio_update(chip, offset, SPRD_GPIO_INEN, 0);
  87. sprd_gpio_update(chip, offset, SPRD_GPIO_DATA, value);
  88. return 0;
  89. }
  90. static int sprd_gpio_get(struct gpio_chip *chip, unsigned int offset)
  91. {
  92. return sprd_gpio_read(chip, offset, SPRD_GPIO_DATA);
  93. }
  94. static void sprd_gpio_set(struct gpio_chip *chip, unsigned int offset,
  95. int value)
  96. {
  97. sprd_gpio_update(chip, offset, SPRD_GPIO_DATA, value);
  98. }
  99. static void sprd_gpio_irq_mask(struct irq_data *data)
  100. {
  101. struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
  102. u32 offset = irqd_to_hwirq(data);
  103. sprd_gpio_update(chip, offset, SPRD_GPIO_IE, 0);
  104. }
  105. static void sprd_gpio_irq_ack(struct irq_data *data)
  106. {
  107. struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
  108. u32 offset = irqd_to_hwirq(data);
  109. sprd_gpio_update(chip, offset, SPRD_GPIO_IC, 1);
  110. }
  111. static void sprd_gpio_irq_unmask(struct irq_data *data)
  112. {
  113. struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
  114. u32 offset = irqd_to_hwirq(data);
  115. sprd_gpio_update(chip, offset, SPRD_GPIO_IE, 1);
  116. }
  117. static int sprd_gpio_irq_set_type(struct irq_data *data,
  118. unsigned int flow_type)
  119. {
  120. struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
  121. u32 offset = irqd_to_hwirq(data);
  122. switch (flow_type) {
  123. case IRQ_TYPE_EDGE_RISING:
  124. sprd_gpio_update(chip, offset, SPRD_GPIO_IS, 0);
  125. sprd_gpio_update(chip, offset, SPRD_GPIO_IBE, 0);
  126. sprd_gpio_update(chip, offset, SPRD_GPIO_IEV, 1);
  127. sprd_gpio_update(chip, offset, SPRD_GPIO_IC, 1);
  128. irq_set_handler_locked(data, handle_edge_irq);
  129. break;
  130. case IRQ_TYPE_EDGE_FALLING:
  131. sprd_gpio_update(chip, offset, SPRD_GPIO_IS, 0);
  132. sprd_gpio_update(chip, offset, SPRD_GPIO_IBE, 0);
  133. sprd_gpio_update(chip, offset, SPRD_GPIO_IEV, 0);
  134. sprd_gpio_update(chip, offset, SPRD_GPIO_IC, 1);
  135. irq_set_handler_locked(data, handle_edge_irq);
  136. break;
  137. case IRQ_TYPE_EDGE_BOTH:
  138. sprd_gpio_update(chip, offset, SPRD_GPIO_IS, 0);
  139. sprd_gpio_update(chip, offset, SPRD_GPIO_IBE, 1);
  140. sprd_gpio_update(chip, offset, SPRD_GPIO_IC, 1);
  141. irq_set_handler_locked(data, handle_edge_irq);
  142. break;
  143. case IRQ_TYPE_LEVEL_HIGH:
  144. sprd_gpio_update(chip, offset, SPRD_GPIO_IS, 1);
  145. sprd_gpio_update(chip, offset, SPRD_GPIO_IBE, 0);
  146. sprd_gpio_update(chip, offset, SPRD_GPIO_IEV, 1);
  147. irq_set_handler_locked(data, handle_level_irq);
  148. break;
  149. case IRQ_TYPE_LEVEL_LOW:
  150. sprd_gpio_update(chip, offset, SPRD_GPIO_IS, 1);
  151. sprd_gpio_update(chip, offset, SPRD_GPIO_IBE, 0);
  152. sprd_gpio_update(chip, offset, SPRD_GPIO_IEV, 0);
  153. irq_set_handler_locked(data, handle_level_irq);
  154. break;
  155. default:
  156. return -EINVAL;
  157. }
  158. return 0;
  159. }
  160. static void sprd_gpio_irq_handler(struct irq_desc *desc)
  161. {
  162. struct gpio_chip *chip = irq_desc_get_handler_data(desc);
  163. struct irq_chip *ic = irq_desc_get_chip(desc);
  164. struct sprd_gpio *sprd_gpio = gpiochip_get_data(chip);
  165. u32 bank, n, girq;
  166. chained_irq_enter(ic, desc);
  167. for (bank = 0; bank * SPRD_GPIO_BANK_NR < chip->ngpio; bank++) {
  168. void __iomem *base = sprd_gpio_bank_base(sprd_gpio, bank);
  169. unsigned long reg = readl_relaxed(base + SPRD_GPIO_MIS) &
  170. SPRD_GPIO_BANK_MASK;
  171. for_each_set_bit(n, &reg, SPRD_GPIO_BANK_NR) {
  172. girq = irq_find_mapping(chip->irq.domain,
  173. bank * SPRD_GPIO_BANK_NR + n);
  174. generic_handle_irq(girq);
  175. }
  176. }
  177. chained_irq_exit(ic, desc);
  178. }
  179. static struct irq_chip sprd_gpio_irqchip = {
  180. .name = "sprd-gpio",
  181. .irq_ack = sprd_gpio_irq_ack,
  182. .irq_mask = sprd_gpio_irq_mask,
  183. .irq_unmask = sprd_gpio_irq_unmask,
  184. .irq_set_type = sprd_gpio_irq_set_type,
  185. .flags = IRQCHIP_SKIP_SET_WAKE,
  186. };
  187. static int sprd_gpio_probe(struct platform_device *pdev)
  188. {
  189. struct gpio_irq_chip *irq;
  190. struct sprd_gpio *sprd_gpio;
  191. int ret;
  192. sprd_gpio = devm_kzalloc(&pdev->dev, sizeof(*sprd_gpio), GFP_KERNEL);
  193. if (!sprd_gpio)
  194. return -ENOMEM;
  195. sprd_gpio->irq = platform_get_irq(pdev, 0);
  196. if (sprd_gpio->irq < 0)
  197. return sprd_gpio->irq;
  198. sprd_gpio->base = devm_platform_ioremap_resource(pdev, 0);
  199. if (IS_ERR(sprd_gpio->base))
  200. return PTR_ERR(sprd_gpio->base);
  201. spin_lock_init(&sprd_gpio->lock);
  202. sprd_gpio->chip.label = dev_name(&pdev->dev);
  203. sprd_gpio->chip.ngpio = SPRD_GPIO_NR;
  204. sprd_gpio->chip.base = -1;
  205. sprd_gpio->chip.parent = &pdev->dev;
  206. sprd_gpio->chip.of_node = pdev->dev.of_node;
  207. sprd_gpio->chip.request = sprd_gpio_request;
  208. sprd_gpio->chip.free = sprd_gpio_free;
  209. sprd_gpio->chip.get = sprd_gpio_get;
  210. sprd_gpio->chip.set = sprd_gpio_set;
  211. sprd_gpio->chip.direction_input = sprd_gpio_direction_input;
  212. sprd_gpio->chip.direction_output = sprd_gpio_direction_output;
  213. irq = &sprd_gpio->chip.irq;
  214. irq->chip = &sprd_gpio_irqchip;
  215. irq->handler = handle_bad_irq;
  216. irq->default_type = IRQ_TYPE_NONE;
  217. irq->parent_handler = sprd_gpio_irq_handler;
  218. irq->parent_handler_data = sprd_gpio;
  219. irq->num_parents = 1;
  220. irq->parents = &sprd_gpio->irq;
  221. ret = devm_gpiochip_add_data(&pdev->dev, &sprd_gpio->chip, sprd_gpio);
  222. if (ret < 0) {
  223. dev_err(&pdev->dev, "Could not register gpiochip %d\n", ret);
  224. return ret;
  225. }
  226. platform_set_drvdata(pdev, sprd_gpio);
  227. return 0;
  228. }
  229. static const struct of_device_id sprd_gpio_of_match[] = {
  230. { .compatible = "sprd,sc9860-gpio", },
  231. { /* end of list */ }
  232. };
  233. MODULE_DEVICE_TABLE(of, sprd_gpio_of_match);
  234. static struct platform_driver sprd_gpio_driver = {
  235. .probe = sprd_gpio_probe,
  236. .driver = {
  237. .name = "sprd-gpio",
  238. .of_match_table = sprd_gpio_of_match,
  239. },
  240. };
  241. module_platform_driver_probe(sprd_gpio_driver, sprd_gpio_probe);
  242. MODULE_DESCRIPTION("Spreadtrum GPIO driver");
  243. MODULE_LICENSE("GPL v2");