gpio-spear-spics.c 5.2 KB

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  1. /*
  2. * SPEAr platform SPI chipselect abstraction over gpiolib
  3. *
  4. * Copyright (C) 2012 ST Microelectronics
  5. * Shiraz Hashim <shiraz.linux.kernel@gmail.com>
  6. *
  7. * This file is licensed under the terms of the GNU General Public
  8. * License version 2. This program is licensed "as is" without any
  9. * warranty of any kind, whether express or implied.
  10. */
  11. #include <linux/err.h>
  12. #include <linux/gpio/driver.h>
  13. #include <linux/io.h>
  14. #include <linux/init.h>
  15. #include <linux/of.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/types.h>
  18. /* maximum chipselects */
  19. #define NUM_OF_GPIO 4
  20. /*
  21. * Provision is available on some SPEAr SoCs to control ARM PL022 spi cs
  22. * through system registers. This register lies outside spi (pl022)
  23. * address space into system registers.
  24. *
  25. * It provides control for spi chip select lines so that any chipselect
  26. * (out of 4 possible chipselects in pl022) can be made low to select
  27. * the particular slave.
  28. */
  29. /**
  30. * struct spear_spics - represents spi chip select control
  31. * @base: base address
  32. * @perip_cfg: configuration register
  33. * @sw_enable_bit: bit to enable s/w control over chipselects
  34. * @cs_value_bit: bit to program high or low chipselect
  35. * @cs_enable_mask: mask to select bits required to select chipselect
  36. * @cs_enable_shift: bit pos of cs_enable_mask
  37. * @use_count: use count of a spi controller cs lines
  38. * @last_off: stores last offset caller of set_value()
  39. * @chip: gpio_chip abstraction
  40. */
  41. struct spear_spics {
  42. void __iomem *base;
  43. u32 perip_cfg;
  44. u32 sw_enable_bit;
  45. u32 cs_value_bit;
  46. u32 cs_enable_mask;
  47. u32 cs_enable_shift;
  48. unsigned long use_count;
  49. int last_off;
  50. struct gpio_chip chip;
  51. };
  52. /* gpio framework specific routines */
  53. static int spics_get_value(struct gpio_chip *chip, unsigned offset)
  54. {
  55. return -ENXIO;
  56. }
  57. static void spics_set_value(struct gpio_chip *chip, unsigned offset, int value)
  58. {
  59. struct spear_spics *spics = gpiochip_get_data(chip);
  60. u32 tmp;
  61. /* select chip select from register */
  62. tmp = readl_relaxed(spics->base + spics->perip_cfg);
  63. if (spics->last_off != offset) {
  64. spics->last_off = offset;
  65. tmp &= ~(spics->cs_enable_mask << spics->cs_enable_shift);
  66. tmp |= offset << spics->cs_enable_shift;
  67. }
  68. /* toggle chip select line */
  69. tmp &= ~(0x1 << spics->cs_value_bit);
  70. tmp |= value << spics->cs_value_bit;
  71. writel_relaxed(tmp, spics->base + spics->perip_cfg);
  72. }
  73. static int spics_direction_input(struct gpio_chip *chip, unsigned offset)
  74. {
  75. return -ENXIO;
  76. }
  77. static int spics_direction_output(struct gpio_chip *chip, unsigned offset,
  78. int value)
  79. {
  80. spics_set_value(chip, offset, value);
  81. return 0;
  82. }
  83. static int spics_request(struct gpio_chip *chip, unsigned offset)
  84. {
  85. struct spear_spics *spics = gpiochip_get_data(chip);
  86. u32 tmp;
  87. if (!spics->use_count++) {
  88. tmp = readl_relaxed(spics->base + spics->perip_cfg);
  89. tmp |= 0x1 << spics->sw_enable_bit;
  90. tmp |= 0x1 << spics->cs_value_bit;
  91. writel_relaxed(tmp, spics->base + spics->perip_cfg);
  92. }
  93. return 0;
  94. }
  95. static void spics_free(struct gpio_chip *chip, unsigned offset)
  96. {
  97. struct spear_spics *spics = gpiochip_get_data(chip);
  98. u32 tmp;
  99. if (!--spics->use_count) {
  100. tmp = readl_relaxed(spics->base + spics->perip_cfg);
  101. tmp &= ~(0x1 << spics->sw_enable_bit);
  102. writel_relaxed(tmp, spics->base + spics->perip_cfg);
  103. }
  104. }
  105. static int spics_gpio_probe(struct platform_device *pdev)
  106. {
  107. struct device_node *np = pdev->dev.of_node;
  108. struct spear_spics *spics;
  109. int ret;
  110. spics = devm_kzalloc(&pdev->dev, sizeof(*spics), GFP_KERNEL);
  111. if (!spics)
  112. return -ENOMEM;
  113. spics->base = devm_platform_ioremap_resource(pdev, 0);
  114. if (IS_ERR(spics->base))
  115. return PTR_ERR(spics->base);
  116. if (of_property_read_u32(np, "st-spics,peripcfg-reg",
  117. &spics->perip_cfg))
  118. goto err_dt_data;
  119. if (of_property_read_u32(np, "st-spics,sw-enable-bit",
  120. &spics->sw_enable_bit))
  121. goto err_dt_data;
  122. if (of_property_read_u32(np, "st-spics,cs-value-bit",
  123. &spics->cs_value_bit))
  124. goto err_dt_data;
  125. if (of_property_read_u32(np, "st-spics,cs-enable-mask",
  126. &spics->cs_enable_mask))
  127. goto err_dt_data;
  128. if (of_property_read_u32(np, "st-spics,cs-enable-shift",
  129. &spics->cs_enable_shift))
  130. goto err_dt_data;
  131. platform_set_drvdata(pdev, spics);
  132. spics->chip.ngpio = NUM_OF_GPIO;
  133. spics->chip.base = -1;
  134. spics->chip.request = spics_request;
  135. spics->chip.free = spics_free;
  136. spics->chip.direction_input = spics_direction_input;
  137. spics->chip.direction_output = spics_direction_output;
  138. spics->chip.get = spics_get_value;
  139. spics->chip.set = spics_set_value;
  140. spics->chip.label = dev_name(&pdev->dev);
  141. spics->chip.parent = &pdev->dev;
  142. spics->chip.owner = THIS_MODULE;
  143. spics->last_off = -1;
  144. ret = devm_gpiochip_add_data(&pdev->dev, &spics->chip, spics);
  145. if (ret) {
  146. dev_err(&pdev->dev, "unable to add gpio chip\n");
  147. return ret;
  148. }
  149. dev_info(&pdev->dev, "spear spics registered\n");
  150. return 0;
  151. err_dt_data:
  152. dev_err(&pdev->dev, "DT probe failed\n");
  153. return -EINVAL;
  154. }
  155. static const struct of_device_id spics_gpio_of_match[] = {
  156. { .compatible = "st,spear-spics-gpio" },
  157. {}
  158. };
  159. static struct platform_driver spics_gpio_driver = {
  160. .probe = spics_gpio_probe,
  161. .driver = {
  162. .name = "spear-spics-gpio",
  163. .of_match_table = spics_gpio_of_match,
  164. },
  165. };
  166. static int __init spics_gpio_init(void)
  167. {
  168. return platform_driver_register(&spics_gpio_driver);
  169. }
  170. subsys_initcall(spics_gpio_init);