gpio-sodaville.c 5.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * GPIO interface for Intel Sodaville SoCs.
  4. *
  5. * Copyright (c) 2010, 2011 Intel Corporation
  6. *
  7. * Author: Hans J. Koch <hjk@linutronix.de>
  8. */
  9. #include <linux/errno.h>
  10. #include <linux/gpio/driver.h>
  11. #include <linux/init.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/io.h>
  14. #include <linux/irq.h>
  15. #include <linux/kernel.h>
  16. #include <linux/of_irq.h>
  17. #include <linux/pci.h>
  18. #include <linux/platform_device.h>
  19. #define DRV_NAME "sdv_gpio"
  20. #define SDV_NUM_PUB_GPIOS 12
  21. #define PCI_DEVICE_ID_SDV_GPIO 0x2e67
  22. #define GPIO_BAR 0
  23. #define GPOUTR 0x00
  24. #define GPOER 0x04
  25. #define GPINR 0x08
  26. #define GPSTR 0x0c
  27. #define GPIT1R0 0x10
  28. #define GPIO_INT 0x14
  29. #define GPIT1R1 0x18
  30. #define GPMUXCTL 0x1c
  31. struct sdv_gpio_chip_data {
  32. int irq_base;
  33. void __iomem *gpio_pub_base;
  34. struct irq_domain *id;
  35. struct irq_chip_generic *gc;
  36. struct gpio_chip chip;
  37. };
  38. static int sdv_gpio_pub_set_type(struct irq_data *d, unsigned int type)
  39. {
  40. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  41. struct sdv_gpio_chip_data *sd = gc->private;
  42. void __iomem *type_reg;
  43. u32 reg;
  44. if (d->hwirq < 8)
  45. type_reg = sd->gpio_pub_base + GPIT1R0;
  46. else
  47. type_reg = sd->gpio_pub_base + GPIT1R1;
  48. reg = readl(type_reg);
  49. switch (type) {
  50. case IRQ_TYPE_LEVEL_HIGH:
  51. reg &= ~BIT(4 * (d->hwirq % 8));
  52. break;
  53. case IRQ_TYPE_LEVEL_LOW:
  54. reg |= BIT(4 * (d->hwirq % 8));
  55. break;
  56. default:
  57. return -EINVAL;
  58. }
  59. writel(reg, type_reg);
  60. return 0;
  61. }
  62. static irqreturn_t sdv_gpio_pub_irq_handler(int irq, void *data)
  63. {
  64. struct sdv_gpio_chip_data *sd = data;
  65. unsigned long irq_stat = readl(sd->gpio_pub_base + GPSTR);
  66. int irq_bit;
  67. irq_stat &= readl(sd->gpio_pub_base + GPIO_INT);
  68. if (!irq_stat)
  69. return IRQ_NONE;
  70. for_each_set_bit(irq_bit, &irq_stat, 32)
  71. generic_handle_irq(irq_find_mapping(sd->id, irq_bit));
  72. return IRQ_HANDLED;
  73. }
  74. static int sdv_xlate(struct irq_domain *h, struct device_node *node,
  75. const u32 *intspec, u32 intsize, irq_hw_number_t *out_hwirq,
  76. u32 *out_type)
  77. {
  78. u32 line, type;
  79. if (node != irq_domain_get_of_node(h))
  80. return -EINVAL;
  81. if (intsize < 2)
  82. return -EINVAL;
  83. line = *intspec;
  84. *out_hwirq = line;
  85. intspec++;
  86. type = *intspec;
  87. switch (type) {
  88. case IRQ_TYPE_LEVEL_LOW:
  89. case IRQ_TYPE_LEVEL_HIGH:
  90. *out_type = type;
  91. break;
  92. default:
  93. return -EINVAL;
  94. }
  95. return 0;
  96. }
  97. static const struct irq_domain_ops irq_domain_sdv_ops = {
  98. .xlate = sdv_xlate,
  99. };
  100. static int sdv_register_irqsupport(struct sdv_gpio_chip_data *sd,
  101. struct pci_dev *pdev)
  102. {
  103. struct irq_chip_type *ct;
  104. int ret;
  105. sd->irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0,
  106. SDV_NUM_PUB_GPIOS, -1);
  107. if (sd->irq_base < 0)
  108. return sd->irq_base;
  109. /* mask + ACK all interrupt sources */
  110. writel(0, sd->gpio_pub_base + GPIO_INT);
  111. writel((1 << 11) - 1, sd->gpio_pub_base + GPSTR);
  112. ret = devm_request_irq(&pdev->dev, pdev->irq,
  113. sdv_gpio_pub_irq_handler, IRQF_SHARED,
  114. "sdv_gpio", sd);
  115. if (ret)
  116. return ret;
  117. /*
  118. * This gpio irq controller latches level irqs. Testing shows that if
  119. * we unmask & ACK the IRQ before the source of the interrupt is gone
  120. * then the interrupt is active again.
  121. */
  122. sd->gc = devm_irq_alloc_generic_chip(&pdev->dev, "sdv-gpio", 1,
  123. sd->irq_base,
  124. sd->gpio_pub_base,
  125. handle_fasteoi_irq);
  126. if (!sd->gc)
  127. return -ENOMEM;
  128. sd->gc->private = sd;
  129. ct = sd->gc->chip_types;
  130. ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
  131. ct->regs.eoi = GPSTR;
  132. ct->regs.mask = GPIO_INT;
  133. ct->chip.irq_mask = irq_gc_mask_clr_bit;
  134. ct->chip.irq_unmask = irq_gc_mask_set_bit;
  135. ct->chip.irq_eoi = irq_gc_eoi;
  136. ct->chip.irq_set_type = sdv_gpio_pub_set_type;
  137. irq_setup_generic_chip(sd->gc, IRQ_MSK(SDV_NUM_PUB_GPIOS),
  138. IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST,
  139. IRQ_LEVEL | IRQ_NOPROBE);
  140. sd->id = irq_domain_add_legacy(pdev->dev.of_node, SDV_NUM_PUB_GPIOS,
  141. sd->irq_base, 0, &irq_domain_sdv_ops, sd);
  142. if (!sd->id)
  143. return -ENODEV;
  144. return 0;
  145. }
  146. static int sdv_gpio_probe(struct pci_dev *pdev,
  147. const struct pci_device_id *pci_id)
  148. {
  149. struct sdv_gpio_chip_data *sd;
  150. int ret;
  151. u32 mux_val;
  152. sd = devm_kzalloc(&pdev->dev, sizeof(*sd), GFP_KERNEL);
  153. if (!sd)
  154. return -ENOMEM;
  155. ret = pcim_enable_device(pdev);
  156. if (ret) {
  157. dev_err(&pdev->dev, "can't enable device.\n");
  158. return ret;
  159. }
  160. ret = pcim_iomap_regions(pdev, 1 << GPIO_BAR, DRV_NAME);
  161. if (ret) {
  162. dev_err(&pdev->dev, "can't alloc PCI BAR #%d\n", GPIO_BAR);
  163. return ret;
  164. }
  165. sd->gpio_pub_base = pcim_iomap_table(pdev)[GPIO_BAR];
  166. ret = of_property_read_u32(pdev->dev.of_node, "intel,muxctl", &mux_val);
  167. if (!ret)
  168. writel(mux_val, sd->gpio_pub_base + GPMUXCTL);
  169. ret = bgpio_init(&sd->chip, &pdev->dev, 4,
  170. sd->gpio_pub_base + GPINR, sd->gpio_pub_base + GPOUTR,
  171. NULL, sd->gpio_pub_base + GPOER, NULL, 0);
  172. if (ret)
  173. return ret;
  174. sd->chip.ngpio = SDV_NUM_PUB_GPIOS;
  175. ret = devm_gpiochip_add_data(&pdev->dev, &sd->chip, sd);
  176. if (ret < 0) {
  177. dev_err(&pdev->dev, "gpiochip_add() failed.\n");
  178. return ret;
  179. }
  180. ret = sdv_register_irqsupport(sd, pdev);
  181. if (ret)
  182. return ret;
  183. pci_set_drvdata(pdev, sd);
  184. dev_info(&pdev->dev, "Sodaville GPIO driver registered.\n");
  185. return 0;
  186. }
  187. static const struct pci_device_id sdv_gpio_pci_ids[] = {
  188. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_SDV_GPIO) },
  189. { 0, },
  190. };
  191. static struct pci_driver sdv_gpio_driver = {
  192. .driver = {
  193. .suppress_bind_attrs = true,
  194. },
  195. .name = DRV_NAME,
  196. .id_table = sdv_gpio_pci_ids,
  197. .probe = sdv_gpio_probe,
  198. };
  199. builtin_pci_driver(sdv_gpio_driver);