gpio-sifive.c 7.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2019 SiFive
  4. */
  5. #include <linux/bitops.h>
  6. #include <linux/device.h>
  7. #include <linux/errno.h>
  8. #include <linux/of_irq.h>
  9. #include <linux/gpio/driver.h>
  10. #include <linux/init.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/slab.h>
  13. #include <linux/spinlock.h>
  14. #include <linux/regmap.h>
  15. #define SIFIVE_GPIO_INPUT_VAL 0x00
  16. #define SIFIVE_GPIO_INPUT_EN 0x04
  17. #define SIFIVE_GPIO_OUTPUT_EN 0x08
  18. #define SIFIVE_GPIO_OUTPUT_VAL 0x0C
  19. #define SIFIVE_GPIO_RISE_IE 0x18
  20. #define SIFIVE_GPIO_RISE_IP 0x1C
  21. #define SIFIVE_GPIO_FALL_IE 0x20
  22. #define SIFIVE_GPIO_FALL_IP 0x24
  23. #define SIFIVE_GPIO_HIGH_IE 0x28
  24. #define SIFIVE_GPIO_HIGH_IP 0x2C
  25. #define SIFIVE_GPIO_LOW_IE 0x30
  26. #define SIFIVE_GPIO_LOW_IP 0x34
  27. #define SIFIVE_GPIO_OUTPUT_XOR 0x40
  28. #define SIFIVE_GPIO_MAX 32
  29. #define SIFIVE_GPIO_IRQ_OFFSET 7
  30. struct sifive_gpio {
  31. void __iomem *base;
  32. struct gpio_chip gc;
  33. struct regmap *regs;
  34. unsigned long irq_state;
  35. unsigned int trigger[SIFIVE_GPIO_MAX];
  36. unsigned int irq_parent[SIFIVE_GPIO_MAX];
  37. };
  38. static void sifive_gpio_set_ie(struct sifive_gpio *chip, unsigned int offset)
  39. {
  40. unsigned long flags;
  41. unsigned int trigger;
  42. spin_lock_irqsave(&chip->gc.bgpio_lock, flags);
  43. trigger = (chip->irq_state & BIT(offset)) ? chip->trigger[offset] : 0;
  44. regmap_update_bits(chip->regs, SIFIVE_GPIO_RISE_IE, BIT(offset),
  45. (trigger & IRQ_TYPE_EDGE_RISING) ? BIT(offset) : 0);
  46. regmap_update_bits(chip->regs, SIFIVE_GPIO_FALL_IE, BIT(offset),
  47. (trigger & IRQ_TYPE_EDGE_FALLING) ? BIT(offset) : 0);
  48. regmap_update_bits(chip->regs, SIFIVE_GPIO_HIGH_IE, BIT(offset),
  49. (trigger & IRQ_TYPE_LEVEL_HIGH) ? BIT(offset) : 0);
  50. regmap_update_bits(chip->regs, SIFIVE_GPIO_LOW_IE, BIT(offset),
  51. (trigger & IRQ_TYPE_LEVEL_LOW) ? BIT(offset) : 0);
  52. spin_unlock_irqrestore(&chip->gc.bgpio_lock, flags);
  53. }
  54. static int sifive_gpio_irq_set_type(struct irq_data *d, unsigned int trigger)
  55. {
  56. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  57. struct sifive_gpio *chip = gpiochip_get_data(gc);
  58. int offset = irqd_to_hwirq(d);
  59. if (offset < 0 || offset >= gc->ngpio)
  60. return -EINVAL;
  61. chip->trigger[offset] = trigger;
  62. sifive_gpio_set_ie(chip, offset);
  63. return 0;
  64. }
  65. static void sifive_gpio_irq_enable(struct irq_data *d)
  66. {
  67. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  68. struct sifive_gpio *chip = gpiochip_get_data(gc);
  69. int offset = irqd_to_hwirq(d) % SIFIVE_GPIO_MAX;
  70. u32 bit = BIT(offset);
  71. unsigned long flags;
  72. irq_chip_enable_parent(d);
  73. /* Switch to input */
  74. gc->direction_input(gc, offset);
  75. spin_lock_irqsave(&gc->bgpio_lock, flags);
  76. /* Clear any sticky pending interrupts */
  77. regmap_write(chip->regs, SIFIVE_GPIO_RISE_IP, bit);
  78. regmap_write(chip->regs, SIFIVE_GPIO_FALL_IP, bit);
  79. regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IP, bit);
  80. regmap_write(chip->regs, SIFIVE_GPIO_LOW_IP, bit);
  81. spin_unlock_irqrestore(&gc->bgpio_lock, flags);
  82. /* Enable interrupts */
  83. assign_bit(offset, &chip->irq_state, 1);
  84. sifive_gpio_set_ie(chip, offset);
  85. }
  86. static void sifive_gpio_irq_disable(struct irq_data *d)
  87. {
  88. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  89. struct sifive_gpio *chip = gpiochip_get_data(gc);
  90. int offset = irqd_to_hwirq(d) % SIFIVE_GPIO_MAX;
  91. assign_bit(offset, &chip->irq_state, 0);
  92. sifive_gpio_set_ie(chip, offset);
  93. irq_chip_disable_parent(d);
  94. }
  95. static void sifive_gpio_irq_eoi(struct irq_data *d)
  96. {
  97. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  98. struct sifive_gpio *chip = gpiochip_get_data(gc);
  99. int offset = irqd_to_hwirq(d) % SIFIVE_GPIO_MAX;
  100. u32 bit = BIT(offset);
  101. unsigned long flags;
  102. spin_lock_irqsave(&gc->bgpio_lock, flags);
  103. /* Clear all pending interrupts */
  104. regmap_write(chip->regs, SIFIVE_GPIO_RISE_IP, bit);
  105. regmap_write(chip->regs, SIFIVE_GPIO_FALL_IP, bit);
  106. regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IP, bit);
  107. regmap_write(chip->regs, SIFIVE_GPIO_LOW_IP, bit);
  108. spin_unlock_irqrestore(&gc->bgpio_lock, flags);
  109. irq_chip_eoi_parent(d);
  110. }
  111. static struct irq_chip sifive_gpio_irqchip = {
  112. .name = "sifive-gpio",
  113. .irq_set_type = sifive_gpio_irq_set_type,
  114. .irq_mask = irq_chip_mask_parent,
  115. .irq_unmask = irq_chip_unmask_parent,
  116. .irq_enable = sifive_gpio_irq_enable,
  117. .irq_disable = sifive_gpio_irq_disable,
  118. .irq_eoi = sifive_gpio_irq_eoi,
  119. };
  120. static int sifive_gpio_child_to_parent_hwirq(struct gpio_chip *gc,
  121. unsigned int child,
  122. unsigned int child_type,
  123. unsigned int *parent,
  124. unsigned int *parent_type)
  125. {
  126. *parent_type = IRQ_TYPE_NONE;
  127. *parent = child + SIFIVE_GPIO_IRQ_OFFSET;
  128. return 0;
  129. }
  130. static const struct regmap_config sifive_gpio_regmap_config = {
  131. .reg_bits = 32,
  132. .reg_stride = 4,
  133. .val_bits = 32,
  134. .fast_io = true,
  135. .disable_locking = true,
  136. };
  137. static int sifive_gpio_probe(struct platform_device *pdev)
  138. {
  139. struct device *dev = &pdev->dev;
  140. struct device_node *node = pdev->dev.of_node;
  141. struct device_node *irq_parent;
  142. struct irq_domain *parent;
  143. struct gpio_irq_chip *girq;
  144. struct sifive_gpio *chip;
  145. int ret, ngpio;
  146. chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
  147. if (!chip)
  148. return -ENOMEM;
  149. chip->base = devm_platform_ioremap_resource(pdev, 0);
  150. if (IS_ERR(chip->base)) {
  151. dev_err(dev, "failed to allocate device memory\n");
  152. return PTR_ERR(chip->base);
  153. }
  154. chip->regs = devm_regmap_init_mmio(dev, chip->base,
  155. &sifive_gpio_regmap_config);
  156. if (IS_ERR(chip->regs))
  157. return PTR_ERR(chip->regs);
  158. ngpio = of_irq_count(node);
  159. if (ngpio > SIFIVE_GPIO_MAX) {
  160. dev_err(dev, "Too many GPIO interrupts (max=%d)\n",
  161. SIFIVE_GPIO_MAX);
  162. return -ENXIO;
  163. }
  164. irq_parent = of_irq_find_parent(node);
  165. if (!irq_parent) {
  166. dev_err(dev, "no IRQ parent node\n");
  167. return -ENODEV;
  168. }
  169. parent = irq_find_host(irq_parent);
  170. if (!parent) {
  171. dev_err(dev, "no IRQ parent domain\n");
  172. return -ENODEV;
  173. }
  174. ret = bgpio_init(&chip->gc, dev, 4,
  175. chip->base + SIFIVE_GPIO_INPUT_VAL,
  176. chip->base + SIFIVE_GPIO_OUTPUT_VAL,
  177. NULL,
  178. chip->base + SIFIVE_GPIO_OUTPUT_EN,
  179. chip->base + SIFIVE_GPIO_INPUT_EN,
  180. BGPIOF_READ_OUTPUT_REG_SET);
  181. if (ret) {
  182. dev_err(dev, "unable to init generic GPIO\n");
  183. return ret;
  184. }
  185. /* Disable all GPIO interrupts before enabling parent interrupts */
  186. regmap_write(chip->regs, SIFIVE_GPIO_RISE_IE, 0);
  187. regmap_write(chip->regs, SIFIVE_GPIO_FALL_IE, 0);
  188. regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IE, 0);
  189. regmap_write(chip->regs, SIFIVE_GPIO_LOW_IE, 0);
  190. chip->irq_state = 0;
  191. chip->gc.base = -1;
  192. chip->gc.ngpio = ngpio;
  193. chip->gc.label = dev_name(dev);
  194. chip->gc.parent = dev;
  195. chip->gc.owner = THIS_MODULE;
  196. girq = &chip->gc.irq;
  197. girq->chip = &sifive_gpio_irqchip;
  198. girq->fwnode = of_node_to_fwnode(node);
  199. girq->parent_domain = parent;
  200. girq->child_to_parent_hwirq = sifive_gpio_child_to_parent_hwirq;
  201. girq->handler = handle_bad_irq;
  202. girq->default_type = IRQ_TYPE_NONE;
  203. platform_set_drvdata(pdev, chip);
  204. return gpiochip_add_data(&chip->gc, chip);
  205. }
  206. static const struct of_device_id sifive_gpio_match[] = {
  207. { .compatible = "sifive,gpio0" },
  208. { .compatible = "sifive,fu540-c000-gpio" },
  209. { },
  210. };
  211. static struct platform_driver sifive_gpio_driver = {
  212. .probe = sifive_gpio_probe,
  213. .driver = {
  214. .name = "sifive_gpio",
  215. .of_match_table = of_match_ptr(sifive_gpio_match),
  216. },
  217. };
  218. builtin_platform_driver(sifive_gpio_driver)