gpio-sa1100.c 7.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * linux/arch/arm/mach-sa1100/gpio.c
  4. *
  5. * Generic SA-1100 GPIO handling
  6. */
  7. #include <linux/gpio/driver.h>
  8. #include <linux/init.h>
  9. #include <linux/module.h>
  10. #include <linux/io.h>
  11. #include <linux/syscore_ops.h>
  12. #include <soc/sa1100/pwer.h>
  13. #include <mach/hardware.h>
  14. #include <mach/irqs.h>
  15. struct sa1100_gpio_chip {
  16. struct gpio_chip chip;
  17. void __iomem *membase;
  18. int irqbase;
  19. u32 irqmask;
  20. u32 irqrising;
  21. u32 irqfalling;
  22. u32 irqwake;
  23. };
  24. #define sa1100_gpio_chip(x) container_of(x, struct sa1100_gpio_chip, chip)
  25. enum {
  26. R_GPLR = 0x00,
  27. R_GPDR = 0x04,
  28. R_GPSR = 0x08,
  29. R_GPCR = 0x0c,
  30. R_GRER = 0x10,
  31. R_GFER = 0x14,
  32. R_GEDR = 0x18,
  33. R_GAFR = 0x1c,
  34. };
  35. static int sa1100_gpio_get(struct gpio_chip *chip, unsigned offset)
  36. {
  37. return readl_relaxed(sa1100_gpio_chip(chip)->membase + R_GPLR) &
  38. BIT(offset);
  39. }
  40. static void sa1100_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
  41. {
  42. int reg = value ? R_GPSR : R_GPCR;
  43. writel_relaxed(BIT(offset), sa1100_gpio_chip(chip)->membase + reg);
  44. }
  45. static int sa1100_get_direction(struct gpio_chip *chip, unsigned offset)
  46. {
  47. void __iomem *gpdr = sa1100_gpio_chip(chip)->membase + R_GPDR;
  48. if (readl_relaxed(gpdr) & BIT(offset))
  49. return GPIO_LINE_DIRECTION_OUT;
  50. return GPIO_LINE_DIRECTION_IN;
  51. }
  52. static int sa1100_direction_input(struct gpio_chip *chip, unsigned offset)
  53. {
  54. void __iomem *gpdr = sa1100_gpio_chip(chip)->membase + R_GPDR;
  55. unsigned long flags;
  56. local_irq_save(flags);
  57. writel_relaxed(readl_relaxed(gpdr) & ~BIT(offset), gpdr);
  58. local_irq_restore(flags);
  59. return 0;
  60. }
  61. static int sa1100_direction_output(struct gpio_chip *chip, unsigned offset, int value)
  62. {
  63. void __iomem *gpdr = sa1100_gpio_chip(chip)->membase + R_GPDR;
  64. unsigned long flags;
  65. local_irq_save(flags);
  66. sa1100_gpio_set(chip, offset, value);
  67. writel_relaxed(readl_relaxed(gpdr) | BIT(offset), gpdr);
  68. local_irq_restore(flags);
  69. return 0;
  70. }
  71. static int sa1100_to_irq(struct gpio_chip *chip, unsigned offset)
  72. {
  73. return sa1100_gpio_chip(chip)->irqbase + offset;
  74. }
  75. static struct sa1100_gpio_chip sa1100_gpio_chip = {
  76. .chip = {
  77. .label = "gpio",
  78. .get_direction = sa1100_get_direction,
  79. .direction_input = sa1100_direction_input,
  80. .direction_output = sa1100_direction_output,
  81. .set = sa1100_gpio_set,
  82. .get = sa1100_gpio_get,
  83. .to_irq = sa1100_to_irq,
  84. .base = 0,
  85. .ngpio = GPIO_MAX + 1,
  86. },
  87. .membase = (void *)&GPLR,
  88. .irqbase = IRQ_GPIO0,
  89. };
  90. /*
  91. * SA1100 GPIO edge detection for IRQs:
  92. * IRQs are generated on Falling-Edge, Rising-Edge, or both.
  93. * Use this instead of directly setting GRER/GFER.
  94. */
  95. static void sa1100_update_edge_regs(struct sa1100_gpio_chip *sgc)
  96. {
  97. void *base = sgc->membase;
  98. u32 grer, gfer;
  99. grer = sgc->irqrising & sgc->irqmask;
  100. gfer = sgc->irqfalling & sgc->irqmask;
  101. writel_relaxed(grer, base + R_GRER);
  102. writel_relaxed(gfer, base + R_GFER);
  103. }
  104. static int sa1100_gpio_type(struct irq_data *d, unsigned int type)
  105. {
  106. struct sa1100_gpio_chip *sgc = irq_data_get_irq_chip_data(d);
  107. unsigned int mask = BIT(d->hwirq);
  108. if (type == IRQ_TYPE_PROBE) {
  109. if ((sgc->irqrising | sgc->irqfalling) & mask)
  110. return 0;
  111. type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
  112. }
  113. if (type & IRQ_TYPE_EDGE_RISING)
  114. sgc->irqrising |= mask;
  115. else
  116. sgc->irqrising &= ~mask;
  117. if (type & IRQ_TYPE_EDGE_FALLING)
  118. sgc->irqfalling |= mask;
  119. else
  120. sgc->irqfalling &= ~mask;
  121. sa1100_update_edge_regs(sgc);
  122. return 0;
  123. }
  124. /*
  125. * GPIO IRQs must be acknowledged.
  126. */
  127. static void sa1100_gpio_ack(struct irq_data *d)
  128. {
  129. struct sa1100_gpio_chip *sgc = irq_data_get_irq_chip_data(d);
  130. writel_relaxed(BIT(d->hwirq), sgc->membase + R_GEDR);
  131. }
  132. static void sa1100_gpio_mask(struct irq_data *d)
  133. {
  134. struct sa1100_gpio_chip *sgc = irq_data_get_irq_chip_data(d);
  135. unsigned int mask = BIT(d->hwirq);
  136. sgc->irqmask &= ~mask;
  137. sa1100_update_edge_regs(sgc);
  138. }
  139. static void sa1100_gpio_unmask(struct irq_data *d)
  140. {
  141. struct sa1100_gpio_chip *sgc = irq_data_get_irq_chip_data(d);
  142. unsigned int mask = BIT(d->hwirq);
  143. sgc->irqmask |= mask;
  144. sa1100_update_edge_regs(sgc);
  145. }
  146. static int sa1100_gpio_wake(struct irq_data *d, unsigned int on)
  147. {
  148. struct sa1100_gpio_chip *sgc = irq_data_get_irq_chip_data(d);
  149. int ret = sa11x0_gpio_set_wake(d->hwirq, on);
  150. if (!ret) {
  151. if (on)
  152. sgc->irqwake |= BIT(d->hwirq);
  153. else
  154. sgc->irqwake &= ~BIT(d->hwirq);
  155. }
  156. return ret;
  157. }
  158. /*
  159. * This is for GPIO IRQs
  160. */
  161. static struct irq_chip sa1100_gpio_irq_chip = {
  162. .name = "GPIO",
  163. .irq_ack = sa1100_gpio_ack,
  164. .irq_mask = sa1100_gpio_mask,
  165. .irq_unmask = sa1100_gpio_unmask,
  166. .irq_set_type = sa1100_gpio_type,
  167. .irq_set_wake = sa1100_gpio_wake,
  168. };
  169. static int sa1100_gpio_irqdomain_map(struct irq_domain *d,
  170. unsigned int irq, irq_hw_number_t hwirq)
  171. {
  172. struct sa1100_gpio_chip *sgc = d->host_data;
  173. irq_set_chip_data(irq, sgc);
  174. irq_set_chip_and_handler(irq, &sa1100_gpio_irq_chip, handle_edge_irq);
  175. irq_set_probe(irq);
  176. return 0;
  177. }
  178. static const struct irq_domain_ops sa1100_gpio_irqdomain_ops = {
  179. .map = sa1100_gpio_irqdomain_map,
  180. .xlate = irq_domain_xlate_onetwocell,
  181. };
  182. static struct irq_domain *sa1100_gpio_irqdomain;
  183. /*
  184. * IRQ 0-11 (GPIO) handler. We enter here with the
  185. * irq_controller_lock held, and IRQs disabled. Decode the IRQ
  186. * and call the handler.
  187. */
  188. static void sa1100_gpio_handler(struct irq_desc *desc)
  189. {
  190. struct sa1100_gpio_chip *sgc = irq_desc_get_handler_data(desc);
  191. unsigned int irq, mask;
  192. void __iomem *gedr = sgc->membase + R_GEDR;
  193. mask = readl_relaxed(gedr);
  194. do {
  195. /*
  196. * clear down all currently active IRQ sources.
  197. * We will be processing them all.
  198. */
  199. writel_relaxed(mask, gedr);
  200. irq = sgc->irqbase;
  201. do {
  202. if (mask & 1)
  203. generic_handle_irq(irq);
  204. mask >>= 1;
  205. irq++;
  206. } while (mask);
  207. mask = readl_relaxed(gedr);
  208. } while (mask);
  209. }
  210. static int sa1100_gpio_suspend(void)
  211. {
  212. struct sa1100_gpio_chip *sgc = &sa1100_gpio_chip;
  213. /*
  214. * Set the appropriate edges for wakeup.
  215. */
  216. writel_relaxed(sgc->irqwake & sgc->irqrising, sgc->membase + R_GRER);
  217. writel_relaxed(sgc->irqwake & sgc->irqfalling, sgc->membase + R_GFER);
  218. /*
  219. * Clear any pending GPIO interrupts.
  220. */
  221. writel_relaxed(readl_relaxed(sgc->membase + R_GEDR),
  222. sgc->membase + R_GEDR);
  223. return 0;
  224. }
  225. static void sa1100_gpio_resume(void)
  226. {
  227. sa1100_update_edge_regs(&sa1100_gpio_chip);
  228. }
  229. static struct syscore_ops sa1100_gpio_syscore_ops = {
  230. .suspend = sa1100_gpio_suspend,
  231. .resume = sa1100_gpio_resume,
  232. };
  233. static int __init sa1100_gpio_init_devicefs(void)
  234. {
  235. register_syscore_ops(&sa1100_gpio_syscore_ops);
  236. return 0;
  237. }
  238. device_initcall(sa1100_gpio_init_devicefs);
  239. static const int sa1100_gpio_irqs[] __initconst = {
  240. /* Install handlers for GPIO 0-10 edge detect interrupts */
  241. IRQ_GPIO0_SC,
  242. IRQ_GPIO1_SC,
  243. IRQ_GPIO2_SC,
  244. IRQ_GPIO3_SC,
  245. IRQ_GPIO4_SC,
  246. IRQ_GPIO5_SC,
  247. IRQ_GPIO6_SC,
  248. IRQ_GPIO7_SC,
  249. IRQ_GPIO8_SC,
  250. IRQ_GPIO9_SC,
  251. IRQ_GPIO10_SC,
  252. /* Install handler for GPIO 11-27 edge detect interrupts */
  253. IRQ_GPIO11_27,
  254. };
  255. void __init sa1100_init_gpio(void)
  256. {
  257. struct sa1100_gpio_chip *sgc = &sa1100_gpio_chip;
  258. int i;
  259. /* clear all GPIO edge detects */
  260. writel_relaxed(0, sgc->membase + R_GFER);
  261. writel_relaxed(0, sgc->membase + R_GRER);
  262. writel_relaxed(-1, sgc->membase + R_GEDR);
  263. gpiochip_add_data(&sa1100_gpio_chip.chip, NULL);
  264. sa1100_gpio_irqdomain = irq_domain_add_simple(NULL,
  265. 28, IRQ_GPIO0,
  266. &sa1100_gpio_irqdomain_ops, sgc);
  267. for (i = 0; i < ARRAY_SIZE(sa1100_gpio_irqs); i++)
  268. irq_set_chained_handler_and_data(sa1100_gpio_irqs[i],
  269. sa1100_gpio_handler, sgc);
  270. }