gpio-rda.c 7.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * RDA Micro GPIO driver
  4. *
  5. * Copyright (C) 2012 RDA Micro Inc.
  6. * Copyright (C) 2019 Manivannan Sadhasivam
  7. */
  8. #include <linux/bitops.h>
  9. #include <linux/gpio/driver.h>
  10. #include <linux/kernel.h>
  11. #include <linux/module.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/spinlock.h>
  14. #define RDA_GPIO_OEN_VAL 0x00
  15. #define RDA_GPIO_OEN_SET_OUT 0x04
  16. #define RDA_GPIO_OEN_SET_IN 0x08
  17. #define RDA_GPIO_VAL 0x0c
  18. #define RDA_GPIO_SET 0x10
  19. #define RDA_GPIO_CLR 0x14
  20. #define RDA_GPIO_INT_CTRL_SET 0x18
  21. #define RDA_GPIO_INT_CTRL_CLR 0x1c
  22. #define RDA_GPIO_INT_CLR 0x20
  23. #define RDA_GPIO_INT_STATUS 0x24
  24. #define RDA_GPIO_IRQ_RISE_SHIFT 0
  25. #define RDA_GPIO_IRQ_FALL_SHIFT 8
  26. #define RDA_GPIO_DEBOUCE_SHIFT 16
  27. #define RDA_GPIO_LEVEL_SHIFT 24
  28. #define RDA_GPIO_IRQ_MASK 0xff
  29. /* Each bank consists of 32 GPIOs */
  30. #define RDA_GPIO_BANK_NR 32
  31. struct rda_gpio {
  32. struct gpio_chip chip;
  33. void __iomem *base;
  34. spinlock_t lock;
  35. struct irq_chip irq_chip;
  36. int irq;
  37. };
  38. static inline void rda_gpio_update(struct gpio_chip *chip, unsigned int offset,
  39. u16 reg, int val)
  40. {
  41. struct rda_gpio *rda_gpio = gpiochip_get_data(chip);
  42. void __iomem *base = rda_gpio->base;
  43. unsigned long flags;
  44. u32 tmp;
  45. spin_lock_irqsave(&rda_gpio->lock, flags);
  46. tmp = readl_relaxed(base + reg);
  47. if (val)
  48. tmp |= BIT(offset);
  49. else
  50. tmp &= ~BIT(offset);
  51. writel_relaxed(tmp, base + reg);
  52. spin_unlock_irqrestore(&rda_gpio->lock, flags);
  53. }
  54. static void rda_gpio_irq_mask(struct irq_data *data)
  55. {
  56. struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
  57. struct rda_gpio *rda_gpio = gpiochip_get_data(chip);
  58. void __iomem *base = rda_gpio->base;
  59. u32 offset = irqd_to_hwirq(data);
  60. u32 value;
  61. value = BIT(offset) << RDA_GPIO_IRQ_RISE_SHIFT;
  62. value |= BIT(offset) << RDA_GPIO_IRQ_FALL_SHIFT;
  63. writel_relaxed(value, base + RDA_GPIO_INT_CTRL_CLR);
  64. }
  65. static void rda_gpio_irq_ack(struct irq_data *data)
  66. {
  67. struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
  68. u32 offset = irqd_to_hwirq(data);
  69. rda_gpio_update(chip, offset, RDA_GPIO_INT_CLR, 1);
  70. }
  71. static int rda_gpio_set_irq(struct gpio_chip *chip, u32 offset,
  72. unsigned int flow_type)
  73. {
  74. struct rda_gpio *rda_gpio = gpiochip_get_data(chip);
  75. void __iomem *base = rda_gpio->base;
  76. u32 value;
  77. switch (flow_type) {
  78. case IRQ_TYPE_EDGE_RISING:
  79. /* Set rising edge trigger */
  80. value = BIT(offset) << RDA_GPIO_IRQ_RISE_SHIFT;
  81. writel_relaxed(value, base + RDA_GPIO_INT_CTRL_SET);
  82. /* Switch to edge trigger interrupt */
  83. value = BIT(offset) << RDA_GPIO_LEVEL_SHIFT;
  84. writel_relaxed(value, base + RDA_GPIO_INT_CTRL_CLR);
  85. break;
  86. case IRQ_TYPE_EDGE_FALLING:
  87. /* Set falling edge trigger */
  88. value = BIT(offset) << RDA_GPIO_IRQ_FALL_SHIFT;
  89. writel_relaxed(value, base + RDA_GPIO_INT_CTRL_SET);
  90. /* Switch to edge trigger interrupt */
  91. value = BIT(offset) << RDA_GPIO_LEVEL_SHIFT;
  92. writel_relaxed(value, base + RDA_GPIO_INT_CTRL_CLR);
  93. break;
  94. case IRQ_TYPE_EDGE_BOTH:
  95. /* Set both edge trigger */
  96. value = BIT(offset) << RDA_GPIO_IRQ_RISE_SHIFT;
  97. value |= BIT(offset) << RDA_GPIO_IRQ_FALL_SHIFT;
  98. writel_relaxed(value, base + RDA_GPIO_INT_CTRL_SET);
  99. /* Switch to edge trigger interrupt */
  100. value = BIT(offset) << RDA_GPIO_LEVEL_SHIFT;
  101. writel_relaxed(value, base + RDA_GPIO_INT_CTRL_CLR);
  102. break;
  103. case IRQ_TYPE_LEVEL_HIGH:
  104. /* Set high level trigger */
  105. value = BIT(offset) << RDA_GPIO_IRQ_RISE_SHIFT;
  106. /* Switch to level trigger interrupt */
  107. value |= BIT(offset) << RDA_GPIO_LEVEL_SHIFT;
  108. writel_relaxed(value, base + RDA_GPIO_INT_CTRL_SET);
  109. break;
  110. case IRQ_TYPE_LEVEL_LOW:
  111. /* Set low level trigger */
  112. value = BIT(offset) << RDA_GPIO_IRQ_FALL_SHIFT;
  113. /* Switch to level trigger interrupt */
  114. value |= BIT(offset) << RDA_GPIO_LEVEL_SHIFT;
  115. writel_relaxed(value, base + RDA_GPIO_INT_CTRL_SET);
  116. break;
  117. default:
  118. return -EINVAL;
  119. }
  120. return 0;
  121. }
  122. static void rda_gpio_irq_unmask(struct irq_data *data)
  123. {
  124. struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
  125. u32 offset = irqd_to_hwirq(data);
  126. u32 trigger = irqd_get_trigger_type(data);
  127. rda_gpio_set_irq(chip, offset, trigger);
  128. }
  129. static int rda_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type)
  130. {
  131. struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
  132. u32 offset = irqd_to_hwirq(data);
  133. int ret;
  134. ret = rda_gpio_set_irq(chip, offset, flow_type);
  135. if (ret)
  136. return ret;
  137. if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
  138. irq_set_handler_locked(data, handle_level_irq);
  139. else if (flow_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
  140. irq_set_handler_locked(data, handle_edge_irq);
  141. return 0;
  142. }
  143. static void rda_gpio_irq_handler(struct irq_desc *desc)
  144. {
  145. struct gpio_chip *chip = irq_desc_get_handler_data(desc);
  146. struct irq_chip *ic = irq_desc_get_chip(desc);
  147. struct rda_gpio *rda_gpio = gpiochip_get_data(chip);
  148. unsigned long status;
  149. u32 n, girq;
  150. chained_irq_enter(ic, desc);
  151. status = readl_relaxed(rda_gpio->base + RDA_GPIO_INT_STATUS);
  152. /* Only lower 8 bits are capable of generating interrupts */
  153. status &= RDA_GPIO_IRQ_MASK;
  154. for_each_set_bit(n, &status, RDA_GPIO_BANK_NR) {
  155. girq = irq_find_mapping(chip->irq.domain, n);
  156. generic_handle_irq(girq);
  157. }
  158. chained_irq_exit(ic, desc);
  159. }
  160. static int rda_gpio_probe(struct platform_device *pdev)
  161. {
  162. struct device_node *np = pdev->dev.of_node;
  163. struct device *dev = &pdev->dev;
  164. struct gpio_irq_chip *girq;
  165. struct rda_gpio *rda_gpio;
  166. u32 ngpios;
  167. int ret;
  168. rda_gpio = devm_kzalloc(dev, sizeof(*rda_gpio), GFP_KERNEL);
  169. if (!rda_gpio)
  170. return -ENOMEM;
  171. ret = device_property_read_u32(dev, "ngpios", &ngpios);
  172. if (ret < 0)
  173. return ret;
  174. /*
  175. * Not all ports have interrupt capability. For instance, on
  176. * RDA8810PL, GPIOC doesn't support interrupt. So we must handle
  177. * those also.
  178. */
  179. rda_gpio->irq = platform_get_irq(pdev, 0);
  180. rda_gpio->base = devm_platform_ioremap_resource(pdev, 0);
  181. if (IS_ERR(rda_gpio->base))
  182. return PTR_ERR(rda_gpio->base);
  183. spin_lock_init(&rda_gpio->lock);
  184. ret = bgpio_init(&rda_gpio->chip, dev, 4,
  185. rda_gpio->base + RDA_GPIO_VAL,
  186. rda_gpio->base + RDA_GPIO_SET,
  187. rda_gpio->base + RDA_GPIO_CLR,
  188. rda_gpio->base + RDA_GPIO_OEN_SET_OUT,
  189. rda_gpio->base + RDA_GPIO_OEN_SET_IN,
  190. BGPIOF_READ_OUTPUT_REG_SET);
  191. if (ret) {
  192. dev_err(dev, "bgpio_init failed\n");
  193. return ret;
  194. }
  195. rda_gpio->chip.label = dev_name(dev);
  196. rda_gpio->chip.ngpio = ngpios;
  197. rda_gpio->chip.base = -1;
  198. rda_gpio->chip.parent = dev;
  199. rda_gpio->chip.of_node = np;
  200. if (rda_gpio->irq >= 0) {
  201. rda_gpio->irq_chip.name = "rda-gpio",
  202. rda_gpio->irq_chip.irq_ack = rda_gpio_irq_ack,
  203. rda_gpio->irq_chip.irq_mask = rda_gpio_irq_mask,
  204. rda_gpio->irq_chip.irq_unmask = rda_gpio_irq_unmask,
  205. rda_gpio->irq_chip.irq_set_type = rda_gpio_irq_set_type,
  206. rda_gpio->irq_chip.flags = IRQCHIP_SKIP_SET_WAKE,
  207. girq = &rda_gpio->chip.irq;
  208. girq->chip = &rda_gpio->irq_chip;
  209. girq->handler = handle_bad_irq;
  210. girq->default_type = IRQ_TYPE_NONE;
  211. girq->parent_handler = rda_gpio_irq_handler;
  212. girq->parent_handler_data = rda_gpio;
  213. girq->num_parents = 1;
  214. girq->parents = devm_kcalloc(dev, 1,
  215. sizeof(*girq->parents),
  216. GFP_KERNEL);
  217. if (!girq->parents)
  218. return -ENOMEM;
  219. girq->parents[0] = rda_gpio->irq;
  220. }
  221. platform_set_drvdata(pdev, rda_gpio);
  222. return devm_gpiochip_add_data(dev, &rda_gpio->chip, rda_gpio);
  223. }
  224. static const struct of_device_id rda_gpio_of_match[] = {
  225. { .compatible = "rda,8810pl-gpio", },
  226. { /* sentinel */ }
  227. };
  228. MODULE_DEVICE_TABLE(of, rda_gpio_of_match);
  229. static struct platform_driver rda_gpio_driver = {
  230. .probe = rda_gpio_probe,
  231. .driver = {
  232. .name = "rda-gpio",
  233. .of_match_table = rda_gpio_of_match,
  234. },
  235. };
  236. module_platform_driver_probe(rda_gpio_driver, rda_gpio_probe);
  237. MODULE_DESCRIPTION("RDA Micro GPIO driver");
  238. MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
  239. MODULE_LICENSE("GPL v2");