gpio-pxa.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * linux/arch/arm/plat-pxa/gpio.c
  4. *
  5. * Generic PXA GPIO handling
  6. *
  7. * Author: Nicolas Pitre
  8. * Created: Jun 15, 2001
  9. * Copyright: MontaVista Software Inc.
  10. */
  11. #include <linux/module.h>
  12. #include <linux/clk.h>
  13. #include <linux/err.h>
  14. #include <linux/gpio/driver.h>
  15. #include <linux/gpio-pxa.h>
  16. #include <linux/init.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/irq.h>
  19. #include <linux/irqdomain.h>
  20. #include <linux/irqchip/chained_irq.h>
  21. #include <linux/io.h>
  22. #include <linux/of.h>
  23. #include <linux/of_device.h>
  24. #include <linux/pinctrl/consumer.h>
  25. #include <linux/platform_device.h>
  26. #include <linux/syscore_ops.h>
  27. #include <linux/slab.h>
  28. /*
  29. * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
  30. * one set of registers. The register offsets are organized below:
  31. *
  32. * GPLR GPDR GPSR GPCR GRER GFER GEDR
  33. * BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048
  34. * BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C
  35. * BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050
  36. *
  37. * BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148
  38. * BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C
  39. * BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150
  40. *
  41. * BANK 6 - 0x0200 0x020C 0x0218 0x0224 0x0230 0x023C 0x0248
  42. *
  43. * NOTE:
  44. * BANK 3 is only available on PXA27x and later processors.
  45. * BANK 4 and 5 are only available on PXA935, PXA1928
  46. * BANK 6 is only available on PXA1928
  47. */
  48. #define GPLR_OFFSET 0x00
  49. #define GPDR_OFFSET 0x0C
  50. #define GPSR_OFFSET 0x18
  51. #define GPCR_OFFSET 0x24
  52. #define GRER_OFFSET 0x30
  53. #define GFER_OFFSET 0x3C
  54. #define GEDR_OFFSET 0x48
  55. #define GAFR_OFFSET 0x54
  56. #define ED_MASK_OFFSET 0x9C /* GPIO edge detection for AP side */
  57. #define BANK_OFF(n) (((n) / 3) << 8) + (((n) % 3) << 2)
  58. int pxa_last_gpio;
  59. static int irq_base;
  60. struct pxa_gpio_bank {
  61. void __iomem *regbase;
  62. unsigned long irq_mask;
  63. unsigned long irq_edge_rise;
  64. unsigned long irq_edge_fall;
  65. #ifdef CONFIG_PM
  66. unsigned long saved_gplr;
  67. unsigned long saved_gpdr;
  68. unsigned long saved_grer;
  69. unsigned long saved_gfer;
  70. #endif
  71. };
  72. struct pxa_gpio_chip {
  73. struct device *dev;
  74. struct gpio_chip chip;
  75. struct pxa_gpio_bank *banks;
  76. struct irq_domain *irqdomain;
  77. int irq0;
  78. int irq1;
  79. int (*set_wake)(unsigned int gpio, unsigned int on);
  80. };
  81. enum pxa_gpio_type {
  82. PXA25X_GPIO = 0,
  83. PXA26X_GPIO,
  84. PXA27X_GPIO,
  85. PXA3XX_GPIO,
  86. PXA93X_GPIO,
  87. MMP_GPIO = 0x10,
  88. MMP2_GPIO,
  89. PXA1928_GPIO,
  90. };
  91. struct pxa_gpio_id {
  92. enum pxa_gpio_type type;
  93. int gpio_nums;
  94. };
  95. static DEFINE_SPINLOCK(gpio_lock);
  96. static struct pxa_gpio_chip *pxa_gpio_chip;
  97. static enum pxa_gpio_type gpio_type;
  98. static struct pxa_gpio_id pxa25x_id = {
  99. .type = PXA25X_GPIO,
  100. .gpio_nums = 85,
  101. };
  102. static struct pxa_gpio_id pxa26x_id = {
  103. .type = PXA26X_GPIO,
  104. .gpio_nums = 90,
  105. };
  106. static struct pxa_gpio_id pxa27x_id = {
  107. .type = PXA27X_GPIO,
  108. .gpio_nums = 121,
  109. };
  110. static struct pxa_gpio_id pxa3xx_id = {
  111. .type = PXA3XX_GPIO,
  112. .gpio_nums = 128,
  113. };
  114. static struct pxa_gpio_id pxa93x_id = {
  115. .type = PXA93X_GPIO,
  116. .gpio_nums = 192,
  117. };
  118. static struct pxa_gpio_id mmp_id = {
  119. .type = MMP_GPIO,
  120. .gpio_nums = 128,
  121. };
  122. static struct pxa_gpio_id mmp2_id = {
  123. .type = MMP2_GPIO,
  124. .gpio_nums = 192,
  125. };
  126. static struct pxa_gpio_id pxa1928_id = {
  127. .type = PXA1928_GPIO,
  128. .gpio_nums = 224,
  129. };
  130. #define for_each_gpio_bank(i, b, pc) \
  131. for (i = 0, b = pc->banks; i <= pxa_last_gpio; i += 32, b++)
  132. static inline struct pxa_gpio_chip *chip_to_pxachip(struct gpio_chip *c)
  133. {
  134. struct pxa_gpio_chip *pxa_chip = gpiochip_get_data(c);
  135. return pxa_chip;
  136. }
  137. static inline void __iomem *gpio_bank_base(struct gpio_chip *c, int gpio)
  138. {
  139. struct pxa_gpio_chip *p = gpiochip_get_data(c);
  140. struct pxa_gpio_bank *bank = p->banks + (gpio / 32);
  141. return bank->regbase;
  142. }
  143. static inline struct pxa_gpio_bank *gpio_to_pxabank(struct gpio_chip *c,
  144. unsigned gpio)
  145. {
  146. return chip_to_pxachip(c)->banks + gpio / 32;
  147. }
  148. static inline int gpio_is_pxa_type(int type)
  149. {
  150. return (type & MMP_GPIO) == 0;
  151. }
  152. static inline int gpio_is_mmp_type(int type)
  153. {
  154. return (type & MMP_GPIO) != 0;
  155. }
  156. /* GPIO86/87/88/89 on PXA26x have their direction bits in PXA_GPDR(2 inverted,
  157. * as well as their Alternate Function value being '1' for GPIO in GAFRx.
  158. */
  159. static inline int __gpio_is_inverted(int gpio)
  160. {
  161. if ((gpio_type == PXA26X_GPIO) && (gpio > 85))
  162. return 1;
  163. return 0;
  164. }
  165. /*
  166. * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate
  167. * function of a GPIO, and GPDRx cannot be altered once configured. It
  168. * is attributed as "occupied" here (I know this terminology isn't
  169. * accurate, you are welcome to propose a better one :-)
  170. */
  171. static inline int __gpio_is_occupied(struct pxa_gpio_chip *pchip, unsigned gpio)
  172. {
  173. void __iomem *base;
  174. unsigned long gafr = 0, gpdr = 0;
  175. int ret, af = 0, dir = 0;
  176. base = gpio_bank_base(&pchip->chip, gpio);
  177. gpdr = readl_relaxed(base + GPDR_OFFSET);
  178. switch (gpio_type) {
  179. case PXA25X_GPIO:
  180. case PXA26X_GPIO:
  181. case PXA27X_GPIO:
  182. gafr = readl_relaxed(base + GAFR_OFFSET);
  183. af = (gafr >> ((gpio & 0xf) * 2)) & 0x3;
  184. dir = gpdr & GPIO_bit(gpio);
  185. if (__gpio_is_inverted(gpio))
  186. ret = (af != 1) || (dir == 0);
  187. else
  188. ret = (af != 0) || (dir != 0);
  189. break;
  190. default:
  191. ret = gpdr & GPIO_bit(gpio);
  192. break;
  193. }
  194. return ret;
  195. }
  196. int pxa_irq_to_gpio(int irq)
  197. {
  198. struct pxa_gpio_chip *pchip = pxa_gpio_chip;
  199. int irq_gpio0;
  200. irq_gpio0 = irq_find_mapping(pchip->irqdomain, 0);
  201. if (irq_gpio0 > 0)
  202. return irq - irq_gpio0;
  203. return irq_gpio0;
  204. }
  205. static bool pxa_gpio_has_pinctrl(void)
  206. {
  207. switch (gpio_type) {
  208. case PXA3XX_GPIO:
  209. case MMP2_GPIO:
  210. return false;
  211. default:
  212. return true;
  213. }
  214. }
  215. static int pxa_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
  216. {
  217. struct pxa_gpio_chip *pchip = chip_to_pxachip(chip);
  218. return irq_find_mapping(pchip->irqdomain, offset);
  219. }
  220. static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
  221. {
  222. void __iomem *base = gpio_bank_base(chip, offset);
  223. uint32_t value, mask = GPIO_bit(offset);
  224. unsigned long flags;
  225. int ret;
  226. if (pxa_gpio_has_pinctrl()) {
  227. ret = pinctrl_gpio_direction_input(chip->base + offset);
  228. if (ret)
  229. return ret;
  230. }
  231. spin_lock_irqsave(&gpio_lock, flags);
  232. value = readl_relaxed(base + GPDR_OFFSET);
  233. if (__gpio_is_inverted(chip->base + offset))
  234. value |= mask;
  235. else
  236. value &= ~mask;
  237. writel_relaxed(value, base + GPDR_OFFSET);
  238. spin_unlock_irqrestore(&gpio_lock, flags);
  239. return 0;
  240. }
  241. static int pxa_gpio_direction_output(struct gpio_chip *chip,
  242. unsigned offset, int value)
  243. {
  244. void __iomem *base = gpio_bank_base(chip, offset);
  245. uint32_t tmp, mask = GPIO_bit(offset);
  246. unsigned long flags;
  247. int ret;
  248. writel_relaxed(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET));
  249. if (pxa_gpio_has_pinctrl()) {
  250. ret = pinctrl_gpio_direction_output(chip->base + offset);
  251. if (ret)
  252. return ret;
  253. }
  254. spin_lock_irqsave(&gpio_lock, flags);
  255. tmp = readl_relaxed(base + GPDR_OFFSET);
  256. if (__gpio_is_inverted(chip->base + offset))
  257. tmp &= ~mask;
  258. else
  259. tmp |= mask;
  260. writel_relaxed(tmp, base + GPDR_OFFSET);
  261. spin_unlock_irqrestore(&gpio_lock, flags);
  262. return 0;
  263. }
  264. static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset)
  265. {
  266. void __iomem *base = gpio_bank_base(chip, offset);
  267. u32 gplr = readl_relaxed(base + GPLR_OFFSET);
  268. return !!(gplr & GPIO_bit(offset));
  269. }
  270. static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
  271. {
  272. void __iomem *base = gpio_bank_base(chip, offset);
  273. writel_relaxed(GPIO_bit(offset),
  274. base + (value ? GPSR_OFFSET : GPCR_OFFSET));
  275. }
  276. #ifdef CONFIG_OF_GPIO
  277. static int pxa_gpio_of_xlate(struct gpio_chip *gc,
  278. const struct of_phandle_args *gpiospec,
  279. u32 *flags)
  280. {
  281. if (gpiospec->args[0] > pxa_last_gpio)
  282. return -EINVAL;
  283. if (flags)
  284. *flags = gpiospec->args[1];
  285. return gpiospec->args[0];
  286. }
  287. #endif
  288. static int pxa_init_gpio_chip(struct pxa_gpio_chip *pchip, int ngpio,
  289. struct device_node *np, void __iomem *regbase)
  290. {
  291. int i, gpio, nbanks = DIV_ROUND_UP(ngpio, 32);
  292. struct pxa_gpio_bank *bank;
  293. pchip->banks = devm_kcalloc(pchip->dev, nbanks, sizeof(*pchip->banks),
  294. GFP_KERNEL);
  295. if (!pchip->banks)
  296. return -ENOMEM;
  297. pchip->chip.label = "gpio-pxa";
  298. pchip->chip.direction_input = pxa_gpio_direction_input;
  299. pchip->chip.direction_output = pxa_gpio_direction_output;
  300. pchip->chip.get = pxa_gpio_get;
  301. pchip->chip.set = pxa_gpio_set;
  302. pchip->chip.to_irq = pxa_gpio_to_irq;
  303. pchip->chip.ngpio = ngpio;
  304. pchip->chip.request = gpiochip_generic_request;
  305. pchip->chip.free = gpiochip_generic_free;
  306. #ifdef CONFIG_OF_GPIO
  307. pchip->chip.of_node = np;
  308. pchip->chip.of_xlate = pxa_gpio_of_xlate;
  309. pchip->chip.of_gpio_n_cells = 2;
  310. #endif
  311. for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) {
  312. bank = pchip->banks + i;
  313. bank->regbase = regbase + BANK_OFF(i);
  314. }
  315. return gpiochip_add_data(&pchip->chip, pchip);
  316. }
  317. /* Update only those GRERx and GFERx edge detection register bits if those
  318. * bits are set in c->irq_mask
  319. */
  320. static inline void update_edge_detect(struct pxa_gpio_bank *c)
  321. {
  322. uint32_t grer, gfer;
  323. grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~c->irq_mask;
  324. gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~c->irq_mask;
  325. grer |= c->irq_edge_rise & c->irq_mask;
  326. gfer |= c->irq_edge_fall & c->irq_mask;
  327. writel_relaxed(grer, c->regbase + GRER_OFFSET);
  328. writel_relaxed(gfer, c->regbase + GFER_OFFSET);
  329. }
  330. static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type)
  331. {
  332. struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
  333. unsigned int gpio = irqd_to_hwirq(d);
  334. struct pxa_gpio_bank *c = gpio_to_pxabank(&pchip->chip, gpio);
  335. unsigned long gpdr, mask = GPIO_bit(gpio);
  336. if (type == IRQ_TYPE_PROBE) {
  337. /* Don't mess with enabled GPIOs using preconfigured edges or
  338. * GPIOs set to alternate function or to output during probe
  339. */
  340. if ((c->irq_edge_rise | c->irq_edge_fall) & GPIO_bit(gpio))
  341. return 0;
  342. if (__gpio_is_occupied(pchip, gpio))
  343. return 0;
  344. type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
  345. }
  346. gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
  347. if (__gpio_is_inverted(gpio))
  348. writel_relaxed(gpdr | mask, c->regbase + GPDR_OFFSET);
  349. else
  350. writel_relaxed(gpdr & ~mask, c->regbase + GPDR_OFFSET);
  351. if (type & IRQ_TYPE_EDGE_RISING)
  352. c->irq_edge_rise |= mask;
  353. else
  354. c->irq_edge_rise &= ~mask;
  355. if (type & IRQ_TYPE_EDGE_FALLING)
  356. c->irq_edge_fall |= mask;
  357. else
  358. c->irq_edge_fall &= ~mask;
  359. update_edge_detect(c);
  360. pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, d->irq, gpio,
  361. ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""),
  362. ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : ""));
  363. return 0;
  364. }
  365. static irqreturn_t pxa_gpio_demux_handler(int in_irq, void *d)
  366. {
  367. int loop, gpio, n, handled = 0;
  368. unsigned long gedr;
  369. struct pxa_gpio_chip *pchip = d;
  370. struct pxa_gpio_bank *c;
  371. do {
  372. loop = 0;
  373. for_each_gpio_bank(gpio, c, pchip) {
  374. gedr = readl_relaxed(c->regbase + GEDR_OFFSET);
  375. gedr = gedr & c->irq_mask;
  376. writel_relaxed(gedr, c->regbase + GEDR_OFFSET);
  377. for_each_set_bit(n, &gedr, BITS_PER_LONG) {
  378. loop = 1;
  379. generic_handle_irq(
  380. irq_find_mapping(pchip->irqdomain,
  381. gpio + n));
  382. }
  383. }
  384. handled += loop;
  385. } while (loop);
  386. return handled ? IRQ_HANDLED : IRQ_NONE;
  387. }
  388. static irqreturn_t pxa_gpio_direct_handler(int in_irq, void *d)
  389. {
  390. struct pxa_gpio_chip *pchip = d;
  391. if (in_irq == pchip->irq0) {
  392. generic_handle_irq(irq_find_mapping(pchip->irqdomain, 0));
  393. } else if (in_irq == pchip->irq1) {
  394. generic_handle_irq(irq_find_mapping(pchip->irqdomain, 1));
  395. } else {
  396. pr_err("%s() unknown irq %d\n", __func__, in_irq);
  397. return IRQ_NONE;
  398. }
  399. return IRQ_HANDLED;
  400. }
  401. static void pxa_ack_muxed_gpio(struct irq_data *d)
  402. {
  403. struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
  404. unsigned int gpio = irqd_to_hwirq(d);
  405. void __iomem *base = gpio_bank_base(&pchip->chip, gpio);
  406. writel_relaxed(GPIO_bit(gpio), base + GEDR_OFFSET);
  407. }
  408. static void pxa_mask_muxed_gpio(struct irq_data *d)
  409. {
  410. struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
  411. unsigned int gpio = irqd_to_hwirq(d);
  412. struct pxa_gpio_bank *b = gpio_to_pxabank(&pchip->chip, gpio);
  413. void __iomem *base = gpio_bank_base(&pchip->chip, gpio);
  414. uint32_t grer, gfer;
  415. b->irq_mask &= ~GPIO_bit(gpio);
  416. grer = readl_relaxed(base + GRER_OFFSET) & ~GPIO_bit(gpio);
  417. gfer = readl_relaxed(base + GFER_OFFSET) & ~GPIO_bit(gpio);
  418. writel_relaxed(grer, base + GRER_OFFSET);
  419. writel_relaxed(gfer, base + GFER_OFFSET);
  420. }
  421. static int pxa_gpio_set_wake(struct irq_data *d, unsigned int on)
  422. {
  423. struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
  424. unsigned int gpio = irqd_to_hwirq(d);
  425. if (pchip->set_wake)
  426. return pchip->set_wake(gpio, on);
  427. else
  428. return 0;
  429. }
  430. static void pxa_unmask_muxed_gpio(struct irq_data *d)
  431. {
  432. struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
  433. unsigned int gpio = irqd_to_hwirq(d);
  434. struct pxa_gpio_bank *c = gpio_to_pxabank(&pchip->chip, gpio);
  435. c->irq_mask |= GPIO_bit(gpio);
  436. update_edge_detect(c);
  437. }
  438. static struct irq_chip pxa_muxed_gpio_chip = {
  439. .name = "GPIO",
  440. .irq_ack = pxa_ack_muxed_gpio,
  441. .irq_mask = pxa_mask_muxed_gpio,
  442. .irq_unmask = pxa_unmask_muxed_gpio,
  443. .irq_set_type = pxa_gpio_irq_type,
  444. .irq_set_wake = pxa_gpio_set_wake,
  445. };
  446. static int pxa_gpio_nums(struct platform_device *pdev)
  447. {
  448. const struct platform_device_id *id = platform_get_device_id(pdev);
  449. struct pxa_gpio_id *pxa_id = (struct pxa_gpio_id *)id->driver_data;
  450. int count = 0;
  451. switch (pxa_id->type) {
  452. case PXA25X_GPIO:
  453. case PXA26X_GPIO:
  454. case PXA27X_GPIO:
  455. case PXA3XX_GPIO:
  456. case PXA93X_GPIO:
  457. case MMP_GPIO:
  458. case MMP2_GPIO:
  459. case PXA1928_GPIO:
  460. gpio_type = pxa_id->type;
  461. count = pxa_id->gpio_nums - 1;
  462. break;
  463. default:
  464. count = -EINVAL;
  465. break;
  466. }
  467. return count;
  468. }
  469. static int pxa_irq_domain_map(struct irq_domain *d, unsigned int irq,
  470. irq_hw_number_t hw)
  471. {
  472. irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
  473. handle_edge_irq);
  474. irq_set_chip_data(irq, d->host_data);
  475. irq_set_noprobe(irq);
  476. return 0;
  477. }
  478. static const struct irq_domain_ops pxa_irq_domain_ops = {
  479. .map = pxa_irq_domain_map,
  480. .xlate = irq_domain_xlate_twocell,
  481. };
  482. #ifdef CONFIG_OF
  483. static const struct of_device_id pxa_gpio_dt_ids[] = {
  484. { .compatible = "intel,pxa25x-gpio", .data = &pxa25x_id, },
  485. { .compatible = "intel,pxa26x-gpio", .data = &pxa26x_id, },
  486. { .compatible = "intel,pxa27x-gpio", .data = &pxa27x_id, },
  487. { .compatible = "intel,pxa3xx-gpio", .data = &pxa3xx_id, },
  488. { .compatible = "marvell,pxa93x-gpio", .data = &pxa93x_id, },
  489. { .compatible = "marvell,mmp-gpio", .data = &mmp_id, },
  490. { .compatible = "marvell,mmp2-gpio", .data = &mmp2_id, },
  491. { .compatible = "marvell,pxa1928-gpio", .data = &pxa1928_id, },
  492. {}
  493. };
  494. static int pxa_gpio_probe_dt(struct platform_device *pdev,
  495. struct pxa_gpio_chip *pchip)
  496. {
  497. int nr_gpios;
  498. const struct pxa_gpio_id *gpio_id;
  499. gpio_id = of_device_get_match_data(&pdev->dev);
  500. gpio_type = gpio_id->type;
  501. nr_gpios = gpio_id->gpio_nums;
  502. pxa_last_gpio = nr_gpios - 1;
  503. irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, nr_gpios, 0);
  504. if (irq_base < 0) {
  505. dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n");
  506. return irq_base;
  507. }
  508. return irq_base;
  509. }
  510. #else
  511. #define pxa_gpio_probe_dt(pdev, pchip) (-1)
  512. #endif
  513. static int pxa_gpio_probe(struct platform_device *pdev)
  514. {
  515. struct pxa_gpio_chip *pchip;
  516. struct pxa_gpio_bank *c;
  517. struct clk *clk;
  518. struct pxa_gpio_platform_data *info;
  519. void __iomem *gpio_reg_base;
  520. int gpio, ret;
  521. int irq0 = 0, irq1 = 0, irq_mux;
  522. pchip = devm_kzalloc(&pdev->dev, sizeof(*pchip), GFP_KERNEL);
  523. if (!pchip)
  524. return -ENOMEM;
  525. pchip->dev = &pdev->dev;
  526. info = dev_get_platdata(&pdev->dev);
  527. if (info) {
  528. irq_base = info->irq_base;
  529. if (irq_base <= 0)
  530. return -EINVAL;
  531. pxa_last_gpio = pxa_gpio_nums(pdev);
  532. pchip->set_wake = info->gpio_set_wake;
  533. } else {
  534. irq_base = pxa_gpio_probe_dt(pdev, pchip);
  535. if (irq_base < 0)
  536. return -EINVAL;
  537. }
  538. if (!pxa_last_gpio)
  539. return -EINVAL;
  540. pchip->irqdomain = irq_domain_add_legacy(pdev->dev.of_node,
  541. pxa_last_gpio + 1, irq_base,
  542. 0, &pxa_irq_domain_ops, pchip);
  543. if (!pchip->irqdomain)
  544. return -ENOMEM;
  545. irq0 = platform_get_irq_byname_optional(pdev, "gpio0");
  546. irq1 = platform_get_irq_byname_optional(pdev, "gpio1");
  547. irq_mux = platform_get_irq_byname(pdev, "gpio_mux");
  548. if ((irq0 > 0 && irq1 <= 0) || (irq0 <= 0 && irq1 > 0)
  549. || (irq_mux <= 0))
  550. return -EINVAL;
  551. pchip->irq0 = irq0;
  552. pchip->irq1 = irq1;
  553. gpio_reg_base = devm_platform_ioremap_resource(pdev, 0);
  554. if (IS_ERR(gpio_reg_base))
  555. return PTR_ERR(gpio_reg_base);
  556. clk = clk_get(&pdev->dev, NULL);
  557. if (IS_ERR(clk)) {
  558. dev_err(&pdev->dev, "Error %ld to get gpio clock\n",
  559. PTR_ERR(clk));
  560. return PTR_ERR(clk);
  561. }
  562. ret = clk_prepare_enable(clk);
  563. if (ret) {
  564. clk_put(clk);
  565. return ret;
  566. }
  567. /* Initialize GPIO chips */
  568. ret = pxa_init_gpio_chip(pchip, pxa_last_gpio + 1, pdev->dev.of_node,
  569. gpio_reg_base);
  570. if (ret) {
  571. clk_put(clk);
  572. return ret;
  573. }
  574. /* clear all GPIO edge detects */
  575. for_each_gpio_bank(gpio, c, pchip) {
  576. writel_relaxed(0, c->regbase + GFER_OFFSET);
  577. writel_relaxed(0, c->regbase + GRER_OFFSET);
  578. writel_relaxed(~0, c->regbase + GEDR_OFFSET);
  579. /* unmask GPIO edge detect for AP side */
  580. if (gpio_is_mmp_type(gpio_type))
  581. writel_relaxed(~0, c->regbase + ED_MASK_OFFSET);
  582. }
  583. if (irq0 > 0) {
  584. ret = devm_request_irq(&pdev->dev,
  585. irq0, pxa_gpio_direct_handler, 0,
  586. "gpio-0", pchip);
  587. if (ret)
  588. dev_err(&pdev->dev, "request of gpio0 irq failed: %d\n",
  589. ret);
  590. }
  591. if (irq1 > 0) {
  592. ret = devm_request_irq(&pdev->dev,
  593. irq1, pxa_gpio_direct_handler, 0,
  594. "gpio-1", pchip);
  595. if (ret)
  596. dev_err(&pdev->dev, "request of gpio1 irq failed: %d\n",
  597. ret);
  598. }
  599. ret = devm_request_irq(&pdev->dev,
  600. irq_mux, pxa_gpio_demux_handler, 0,
  601. "gpio-mux", pchip);
  602. if (ret)
  603. dev_err(&pdev->dev, "request of gpio-mux irq failed: %d\n",
  604. ret);
  605. pxa_gpio_chip = pchip;
  606. return 0;
  607. }
  608. static const struct platform_device_id gpio_id_table[] = {
  609. { "pxa25x-gpio", (unsigned long)&pxa25x_id },
  610. { "pxa26x-gpio", (unsigned long)&pxa26x_id },
  611. { "pxa27x-gpio", (unsigned long)&pxa27x_id },
  612. { "pxa3xx-gpio", (unsigned long)&pxa3xx_id },
  613. { "pxa93x-gpio", (unsigned long)&pxa93x_id },
  614. { "mmp-gpio", (unsigned long)&mmp_id },
  615. { "mmp2-gpio", (unsigned long)&mmp2_id },
  616. { "pxa1928-gpio", (unsigned long)&pxa1928_id },
  617. { },
  618. };
  619. static struct platform_driver pxa_gpio_driver = {
  620. .probe = pxa_gpio_probe,
  621. .driver = {
  622. .name = "pxa-gpio",
  623. .of_match_table = of_match_ptr(pxa_gpio_dt_ids),
  624. },
  625. .id_table = gpio_id_table,
  626. };
  627. static int __init pxa_gpio_legacy_init(void)
  628. {
  629. if (of_have_populated_dt())
  630. return 0;
  631. return platform_driver_register(&pxa_gpio_driver);
  632. }
  633. postcore_initcall(pxa_gpio_legacy_init);
  634. static int __init pxa_gpio_dt_init(void)
  635. {
  636. if (of_have_populated_dt())
  637. return platform_driver_register(&pxa_gpio_driver);
  638. return 0;
  639. }
  640. device_initcall(pxa_gpio_dt_init);
  641. #ifdef CONFIG_PM
  642. static int pxa_gpio_suspend(void)
  643. {
  644. struct pxa_gpio_chip *pchip = pxa_gpio_chip;
  645. struct pxa_gpio_bank *c;
  646. int gpio;
  647. if (!pchip)
  648. return 0;
  649. for_each_gpio_bank(gpio, c, pchip) {
  650. c->saved_gplr = readl_relaxed(c->regbase + GPLR_OFFSET);
  651. c->saved_gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
  652. c->saved_grer = readl_relaxed(c->regbase + GRER_OFFSET);
  653. c->saved_gfer = readl_relaxed(c->regbase + GFER_OFFSET);
  654. /* Clear GPIO transition detect bits */
  655. writel_relaxed(0xffffffff, c->regbase + GEDR_OFFSET);
  656. }
  657. return 0;
  658. }
  659. static void pxa_gpio_resume(void)
  660. {
  661. struct pxa_gpio_chip *pchip = pxa_gpio_chip;
  662. struct pxa_gpio_bank *c;
  663. int gpio;
  664. if (!pchip)
  665. return;
  666. for_each_gpio_bank(gpio, c, pchip) {
  667. /* restore level with set/clear */
  668. writel_relaxed(c->saved_gplr, c->regbase + GPSR_OFFSET);
  669. writel_relaxed(~c->saved_gplr, c->regbase + GPCR_OFFSET);
  670. writel_relaxed(c->saved_grer, c->regbase + GRER_OFFSET);
  671. writel_relaxed(c->saved_gfer, c->regbase + GFER_OFFSET);
  672. writel_relaxed(c->saved_gpdr, c->regbase + GPDR_OFFSET);
  673. }
  674. }
  675. #else
  676. #define pxa_gpio_suspend NULL
  677. #define pxa_gpio_resume NULL
  678. #endif
  679. static struct syscore_ops pxa_gpio_syscore_ops = {
  680. .suspend = pxa_gpio_suspend,
  681. .resume = pxa_gpio_resume,
  682. };
  683. static int __init pxa_gpio_sysinit(void)
  684. {
  685. register_syscore_ops(&pxa_gpio_syscore_ops);
  686. return 0;
  687. }
  688. postcore_initcall(pxa_gpio_sysinit);