gpio-pmic-eic-sprd.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2018 Spreadtrum Communications Inc.
  4. * Copyright (C) 2018 Linaro Ltd.
  5. */
  6. #include <linux/gpio/driver.h>
  7. #include <linux/interrupt.h>
  8. #include <linux/kernel.h>
  9. #include <linux/module.h>
  10. #include <linux/of_device.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/regmap.h>
  13. /* EIC registers definition */
  14. #define SPRD_PMIC_EIC_DATA 0x0
  15. #define SPRD_PMIC_EIC_DMSK 0x4
  16. #define SPRD_PMIC_EIC_IEV 0x14
  17. #define SPRD_PMIC_EIC_IE 0x18
  18. #define SPRD_PMIC_EIC_RIS 0x1c
  19. #define SPRD_PMIC_EIC_MIS 0x20
  20. #define SPRD_PMIC_EIC_IC 0x24
  21. #define SPRD_PMIC_EIC_TRIG 0x28
  22. #define SPRD_PMIC_EIC_CTRL0 0x40
  23. /*
  24. * The PMIC EIC controller only has one bank, and each bank now can contain
  25. * 16 EICs.
  26. */
  27. #define SPRD_PMIC_EIC_PER_BANK_NR 16
  28. #define SPRD_PMIC_EIC_NR SPRD_PMIC_EIC_PER_BANK_NR
  29. #define SPRD_PMIC_EIC_DATA_MASK GENMASK(15, 0)
  30. #define SPRD_PMIC_EIC_BIT(x) ((x) & (SPRD_PMIC_EIC_PER_BANK_NR - 1))
  31. #define SPRD_PMIC_EIC_DBNC_MASK GENMASK(11, 0)
  32. /*
  33. * These registers are modified under the irq bus lock and cached to avoid
  34. * unnecessary writes in bus_sync_unlock.
  35. */
  36. enum {
  37. REG_IEV,
  38. REG_IE,
  39. REG_TRIG,
  40. CACHE_NR_REGS
  41. };
  42. /**
  43. * struct sprd_pmic_eic - PMIC EIC controller
  44. * @chip: the gpio_chip structure.
  45. * @intc: the irq_chip structure.
  46. * @map: the regmap from the parent device.
  47. * @offset: the EIC controller's offset address of the PMIC.
  48. * @reg: the array to cache the EIC registers.
  49. * @buslock: for bus lock/sync and unlock.
  50. * @irq: the interrupt number of the PMIC EIC conteroller.
  51. */
  52. struct sprd_pmic_eic {
  53. struct gpio_chip chip;
  54. struct irq_chip intc;
  55. struct regmap *map;
  56. u32 offset;
  57. u8 reg[CACHE_NR_REGS];
  58. struct mutex buslock;
  59. int irq;
  60. };
  61. static void sprd_pmic_eic_update(struct gpio_chip *chip, unsigned int offset,
  62. u16 reg, unsigned int val)
  63. {
  64. struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
  65. u32 shift = SPRD_PMIC_EIC_BIT(offset);
  66. regmap_update_bits(pmic_eic->map, pmic_eic->offset + reg,
  67. BIT(shift), val << shift);
  68. }
  69. static int sprd_pmic_eic_read(struct gpio_chip *chip, unsigned int offset,
  70. u16 reg)
  71. {
  72. struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
  73. u32 value;
  74. int ret;
  75. ret = regmap_read(pmic_eic->map, pmic_eic->offset + reg, &value);
  76. if (ret)
  77. return ret;
  78. return !!(value & BIT(SPRD_PMIC_EIC_BIT(offset)));
  79. }
  80. static int sprd_pmic_eic_request(struct gpio_chip *chip, unsigned int offset)
  81. {
  82. sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_DMSK, 1);
  83. return 0;
  84. }
  85. static void sprd_pmic_eic_free(struct gpio_chip *chip, unsigned int offset)
  86. {
  87. sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_DMSK, 0);
  88. }
  89. static int sprd_pmic_eic_get(struct gpio_chip *chip, unsigned int offset)
  90. {
  91. return sprd_pmic_eic_read(chip, offset, SPRD_PMIC_EIC_DATA);
  92. }
  93. static int sprd_pmic_eic_direction_input(struct gpio_chip *chip,
  94. unsigned int offset)
  95. {
  96. /* EICs are always input, nothing need to do here. */
  97. return 0;
  98. }
  99. static void sprd_pmic_eic_set(struct gpio_chip *chip, unsigned int offset,
  100. int value)
  101. {
  102. /* EICs are always input, nothing need to do here. */
  103. }
  104. static int sprd_pmic_eic_set_debounce(struct gpio_chip *chip,
  105. unsigned int offset,
  106. unsigned int debounce)
  107. {
  108. struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
  109. u32 reg, value;
  110. int ret;
  111. reg = SPRD_PMIC_EIC_CTRL0 + SPRD_PMIC_EIC_BIT(offset) * 0x4;
  112. ret = regmap_read(pmic_eic->map, pmic_eic->offset + reg, &value);
  113. if (ret)
  114. return ret;
  115. value &= ~SPRD_PMIC_EIC_DBNC_MASK;
  116. value |= (debounce / 1000) & SPRD_PMIC_EIC_DBNC_MASK;
  117. return regmap_write(pmic_eic->map, pmic_eic->offset + reg, value);
  118. }
  119. static int sprd_pmic_eic_set_config(struct gpio_chip *chip, unsigned int offset,
  120. unsigned long config)
  121. {
  122. unsigned long param = pinconf_to_config_param(config);
  123. u32 arg = pinconf_to_config_argument(config);
  124. if (param == PIN_CONFIG_INPUT_DEBOUNCE)
  125. return sprd_pmic_eic_set_debounce(chip, offset, arg);
  126. return -ENOTSUPP;
  127. }
  128. static void sprd_pmic_eic_irq_mask(struct irq_data *data)
  129. {
  130. struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
  131. struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
  132. pmic_eic->reg[REG_IE] = 0;
  133. pmic_eic->reg[REG_TRIG] = 0;
  134. }
  135. static void sprd_pmic_eic_irq_unmask(struct irq_data *data)
  136. {
  137. struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
  138. struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
  139. pmic_eic->reg[REG_IE] = 1;
  140. pmic_eic->reg[REG_TRIG] = 1;
  141. }
  142. static int sprd_pmic_eic_irq_set_type(struct irq_data *data,
  143. unsigned int flow_type)
  144. {
  145. struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
  146. struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
  147. switch (flow_type) {
  148. case IRQ_TYPE_LEVEL_HIGH:
  149. pmic_eic->reg[REG_IEV] = 1;
  150. break;
  151. case IRQ_TYPE_LEVEL_LOW:
  152. pmic_eic->reg[REG_IEV] = 0;
  153. break;
  154. case IRQ_TYPE_EDGE_RISING:
  155. case IRQ_TYPE_EDGE_FALLING:
  156. case IRQ_TYPE_EDGE_BOTH:
  157. /*
  158. * Will set the trigger level according to current EIC level
  159. * in irq_bus_sync_unlock() interface, so here nothing to do.
  160. */
  161. break;
  162. default:
  163. return -ENOTSUPP;
  164. }
  165. return 0;
  166. }
  167. static void sprd_pmic_eic_bus_lock(struct irq_data *data)
  168. {
  169. struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
  170. struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
  171. mutex_lock(&pmic_eic->buslock);
  172. }
  173. static void sprd_pmic_eic_bus_sync_unlock(struct irq_data *data)
  174. {
  175. struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
  176. struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
  177. u32 trigger = irqd_get_trigger_type(data);
  178. u32 offset = irqd_to_hwirq(data);
  179. int state;
  180. /* Set irq type */
  181. if (trigger & IRQ_TYPE_EDGE_BOTH) {
  182. state = sprd_pmic_eic_get(chip, offset);
  183. if (state)
  184. sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, 0);
  185. else
  186. sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, 1);
  187. } else {
  188. sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV,
  189. pmic_eic->reg[REG_IEV]);
  190. }
  191. /* Set irq unmask */
  192. sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IE,
  193. pmic_eic->reg[REG_IE]);
  194. /* Generate trigger start pulse for debounce EIC */
  195. sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_TRIG,
  196. pmic_eic->reg[REG_TRIG]);
  197. mutex_unlock(&pmic_eic->buslock);
  198. }
  199. static void sprd_pmic_eic_toggle_trigger(struct gpio_chip *chip,
  200. unsigned int irq, unsigned int offset)
  201. {
  202. u32 trigger = irq_get_trigger_type(irq);
  203. int state, post_state;
  204. if (!(trigger & IRQ_TYPE_EDGE_BOTH))
  205. return;
  206. state = sprd_pmic_eic_get(chip, offset);
  207. retry:
  208. if (state)
  209. sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, 0);
  210. else
  211. sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, 1);
  212. post_state = sprd_pmic_eic_get(chip, offset);
  213. if (state != post_state) {
  214. dev_warn(chip->parent, "PMIC EIC level was changed.\n");
  215. state = post_state;
  216. goto retry;
  217. }
  218. /* Set irq unmask */
  219. sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IE, 1);
  220. /* Generate trigger start pulse for debounce EIC */
  221. sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_TRIG, 1);
  222. }
  223. static irqreturn_t sprd_pmic_eic_irq_handler(int irq, void *data)
  224. {
  225. struct sprd_pmic_eic *pmic_eic = data;
  226. struct gpio_chip *chip = &pmic_eic->chip;
  227. unsigned long status;
  228. u32 n, girq, val;
  229. int ret;
  230. ret = regmap_read(pmic_eic->map, pmic_eic->offset + SPRD_PMIC_EIC_MIS,
  231. &val);
  232. if (ret)
  233. return IRQ_RETVAL(ret);
  234. status = val & SPRD_PMIC_EIC_DATA_MASK;
  235. for_each_set_bit(n, &status, chip->ngpio) {
  236. /* Clear the interrupt */
  237. sprd_pmic_eic_update(chip, n, SPRD_PMIC_EIC_IC, 1);
  238. girq = irq_find_mapping(chip->irq.domain, n);
  239. handle_nested_irq(girq);
  240. /*
  241. * The PMIC EIC can only support level trigger, so we can
  242. * toggle the level trigger to emulate the edge trigger.
  243. */
  244. sprd_pmic_eic_toggle_trigger(chip, girq, n);
  245. }
  246. return IRQ_HANDLED;
  247. }
  248. static int sprd_pmic_eic_probe(struct platform_device *pdev)
  249. {
  250. struct gpio_irq_chip *irq;
  251. struct sprd_pmic_eic *pmic_eic;
  252. int ret;
  253. pmic_eic = devm_kzalloc(&pdev->dev, sizeof(*pmic_eic), GFP_KERNEL);
  254. if (!pmic_eic)
  255. return -ENOMEM;
  256. mutex_init(&pmic_eic->buslock);
  257. pmic_eic->irq = platform_get_irq(pdev, 0);
  258. if (pmic_eic->irq < 0)
  259. return pmic_eic->irq;
  260. pmic_eic->map = dev_get_regmap(pdev->dev.parent, NULL);
  261. if (!pmic_eic->map)
  262. return -ENODEV;
  263. ret = of_property_read_u32(pdev->dev.of_node, "reg", &pmic_eic->offset);
  264. if (ret) {
  265. dev_err(&pdev->dev, "Failed to get PMIC EIC base address.\n");
  266. return ret;
  267. }
  268. ret = devm_request_threaded_irq(&pdev->dev, pmic_eic->irq, NULL,
  269. sprd_pmic_eic_irq_handler,
  270. IRQF_ONESHOT | IRQF_NO_SUSPEND,
  271. dev_name(&pdev->dev), pmic_eic);
  272. if (ret) {
  273. dev_err(&pdev->dev, "Failed to request PMIC EIC IRQ.\n");
  274. return ret;
  275. }
  276. pmic_eic->chip.label = dev_name(&pdev->dev);
  277. pmic_eic->chip.ngpio = SPRD_PMIC_EIC_NR;
  278. pmic_eic->chip.base = -1;
  279. pmic_eic->chip.parent = &pdev->dev;
  280. pmic_eic->chip.of_node = pdev->dev.of_node;
  281. pmic_eic->chip.direction_input = sprd_pmic_eic_direction_input;
  282. pmic_eic->chip.request = sprd_pmic_eic_request;
  283. pmic_eic->chip.free = sprd_pmic_eic_free;
  284. pmic_eic->chip.set_config = sprd_pmic_eic_set_config;
  285. pmic_eic->chip.set = sprd_pmic_eic_set;
  286. pmic_eic->chip.get = sprd_pmic_eic_get;
  287. pmic_eic->intc.name = dev_name(&pdev->dev);
  288. pmic_eic->intc.irq_mask = sprd_pmic_eic_irq_mask;
  289. pmic_eic->intc.irq_unmask = sprd_pmic_eic_irq_unmask;
  290. pmic_eic->intc.irq_set_type = sprd_pmic_eic_irq_set_type;
  291. pmic_eic->intc.irq_bus_lock = sprd_pmic_eic_bus_lock;
  292. pmic_eic->intc.irq_bus_sync_unlock = sprd_pmic_eic_bus_sync_unlock;
  293. pmic_eic->intc.flags = IRQCHIP_SKIP_SET_WAKE;
  294. irq = &pmic_eic->chip.irq;
  295. irq->chip = &pmic_eic->intc;
  296. irq->threaded = true;
  297. ret = devm_gpiochip_add_data(&pdev->dev, &pmic_eic->chip, pmic_eic);
  298. if (ret < 0) {
  299. dev_err(&pdev->dev, "Could not register gpiochip %d.\n", ret);
  300. return ret;
  301. }
  302. platform_set_drvdata(pdev, pmic_eic);
  303. return 0;
  304. }
  305. static const struct of_device_id sprd_pmic_eic_of_match[] = {
  306. { .compatible = "sprd,sc2731-eic", },
  307. { /* end of list */ }
  308. };
  309. MODULE_DEVICE_TABLE(of, sprd_pmic_eic_of_match);
  310. static struct platform_driver sprd_pmic_eic_driver = {
  311. .probe = sprd_pmic_eic_probe,
  312. .driver = {
  313. .name = "sprd-pmic-eic",
  314. .of_match_table = sprd_pmic_eic_of_match,
  315. },
  316. };
  317. module_platform_driver(sprd_pmic_eic_driver);
  318. MODULE_DESCRIPTION("Spreadtrum PMIC EIC driver");
  319. MODULE_LICENSE("GPL v2");