gpio-pl061.c 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2008, 2009 Provigent Ltd.
  4. *
  5. * Author: Baruch Siach <baruch@tkos.co.il>
  6. *
  7. * Driver for the ARM PrimeCell(tm) General Purpose Input/Output (PL061)
  8. *
  9. * Data sheet: ARM DDI 0190B, September 2000
  10. */
  11. #include <linux/spinlock.h>
  12. #include <linux/errno.h>
  13. #include <linux/init.h>
  14. #include <linux/io.h>
  15. #include <linux/ioport.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/irq.h>
  18. #include <linux/irqchip/chained_irq.h>
  19. #include <linux/module.h>
  20. #include <linux/bitops.h>
  21. #include <linux/gpio/driver.h>
  22. #include <linux/device.h>
  23. #include <linux/amba/bus.h>
  24. #include <linux/slab.h>
  25. #include <linux/pinctrl/consumer.h>
  26. #include <linux/pm.h>
  27. #define GPIODIR 0x400
  28. #define GPIOIS 0x404
  29. #define GPIOIBE 0x408
  30. #define GPIOIEV 0x40C
  31. #define GPIOIE 0x410
  32. #define GPIORIS 0x414
  33. #define GPIOMIS 0x418
  34. #define GPIOIC 0x41C
  35. #define PL061_GPIO_NR 8
  36. #ifdef CONFIG_PM
  37. struct pl061_context_save_regs {
  38. u8 gpio_data;
  39. u8 gpio_dir;
  40. u8 gpio_is;
  41. u8 gpio_ibe;
  42. u8 gpio_iev;
  43. u8 gpio_ie;
  44. };
  45. #endif
  46. struct pl061 {
  47. raw_spinlock_t lock;
  48. void __iomem *base;
  49. struct gpio_chip gc;
  50. struct irq_chip irq_chip;
  51. int parent_irq;
  52. #ifdef CONFIG_PM
  53. struct pl061_context_save_regs csave_regs;
  54. #endif
  55. };
  56. static int pl061_get_direction(struct gpio_chip *gc, unsigned offset)
  57. {
  58. struct pl061 *pl061 = gpiochip_get_data(gc);
  59. if (readb(pl061->base + GPIODIR) & BIT(offset))
  60. return GPIO_LINE_DIRECTION_OUT;
  61. return GPIO_LINE_DIRECTION_IN;
  62. }
  63. static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
  64. {
  65. struct pl061 *pl061 = gpiochip_get_data(gc);
  66. unsigned long flags;
  67. unsigned char gpiodir;
  68. raw_spin_lock_irqsave(&pl061->lock, flags);
  69. gpiodir = readb(pl061->base + GPIODIR);
  70. gpiodir &= ~(BIT(offset));
  71. writeb(gpiodir, pl061->base + GPIODIR);
  72. raw_spin_unlock_irqrestore(&pl061->lock, flags);
  73. return 0;
  74. }
  75. static int pl061_direction_output(struct gpio_chip *gc, unsigned offset,
  76. int value)
  77. {
  78. struct pl061 *pl061 = gpiochip_get_data(gc);
  79. unsigned long flags;
  80. unsigned char gpiodir;
  81. raw_spin_lock_irqsave(&pl061->lock, flags);
  82. writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
  83. gpiodir = readb(pl061->base + GPIODIR);
  84. gpiodir |= BIT(offset);
  85. writeb(gpiodir, pl061->base + GPIODIR);
  86. /*
  87. * gpio value is set again, because pl061 doesn't allow to set value of
  88. * a gpio pin before configuring it in OUT mode.
  89. */
  90. writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
  91. raw_spin_unlock_irqrestore(&pl061->lock, flags);
  92. return 0;
  93. }
  94. static int pl061_get_value(struct gpio_chip *gc, unsigned offset)
  95. {
  96. struct pl061 *pl061 = gpiochip_get_data(gc);
  97. return !!readb(pl061->base + (BIT(offset + 2)));
  98. }
  99. static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value)
  100. {
  101. struct pl061 *pl061 = gpiochip_get_data(gc);
  102. writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
  103. }
  104. static int pl061_irq_type(struct irq_data *d, unsigned trigger)
  105. {
  106. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  107. struct pl061 *pl061 = gpiochip_get_data(gc);
  108. int offset = irqd_to_hwirq(d);
  109. unsigned long flags;
  110. u8 gpiois, gpioibe, gpioiev;
  111. u8 bit = BIT(offset);
  112. if (offset < 0 || offset >= PL061_GPIO_NR)
  113. return -EINVAL;
  114. if ((trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) &&
  115. (trigger & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)))
  116. {
  117. dev_err(gc->parent,
  118. "trying to configure line %d for both level and edge "
  119. "detection, choose one!\n",
  120. offset);
  121. return -EINVAL;
  122. }
  123. raw_spin_lock_irqsave(&pl061->lock, flags);
  124. gpioiev = readb(pl061->base + GPIOIEV);
  125. gpiois = readb(pl061->base + GPIOIS);
  126. gpioibe = readb(pl061->base + GPIOIBE);
  127. if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
  128. bool polarity = trigger & IRQ_TYPE_LEVEL_HIGH;
  129. /* Disable edge detection */
  130. gpioibe &= ~bit;
  131. /* Enable level detection */
  132. gpiois |= bit;
  133. /* Select polarity */
  134. if (polarity)
  135. gpioiev |= bit;
  136. else
  137. gpioiev &= ~bit;
  138. irq_set_handler_locked(d, handle_level_irq);
  139. dev_dbg(gc->parent, "line %d: IRQ on %s level\n",
  140. offset,
  141. polarity ? "HIGH" : "LOW");
  142. } else if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
  143. /* Disable level detection */
  144. gpiois &= ~bit;
  145. /* Select both edges, setting this makes GPIOEV be ignored */
  146. gpioibe |= bit;
  147. irq_set_handler_locked(d, handle_edge_irq);
  148. dev_dbg(gc->parent, "line %d: IRQ on both edges\n", offset);
  149. } else if ((trigger & IRQ_TYPE_EDGE_RISING) ||
  150. (trigger & IRQ_TYPE_EDGE_FALLING)) {
  151. bool rising = trigger & IRQ_TYPE_EDGE_RISING;
  152. /* Disable level detection */
  153. gpiois &= ~bit;
  154. /* Clear detection on both edges */
  155. gpioibe &= ~bit;
  156. /* Select edge */
  157. if (rising)
  158. gpioiev |= bit;
  159. else
  160. gpioiev &= ~bit;
  161. irq_set_handler_locked(d, handle_edge_irq);
  162. dev_dbg(gc->parent, "line %d: IRQ on %s edge\n",
  163. offset,
  164. rising ? "RISING" : "FALLING");
  165. } else {
  166. /* No trigger: disable everything */
  167. gpiois &= ~bit;
  168. gpioibe &= ~bit;
  169. gpioiev &= ~bit;
  170. irq_set_handler_locked(d, handle_bad_irq);
  171. dev_warn(gc->parent, "no trigger selected for line %d\n",
  172. offset);
  173. }
  174. writeb(gpiois, pl061->base + GPIOIS);
  175. writeb(gpioibe, pl061->base + GPIOIBE);
  176. writeb(gpioiev, pl061->base + GPIOIEV);
  177. raw_spin_unlock_irqrestore(&pl061->lock, flags);
  178. return 0;
  179. }
  180. static void pl061_irq_handler(struct irq_desc *desc)
  181. {
  182. unsigned long pending;
  183. int offset;
  184. struct gpio_chip *gc = irq_desc_get_handler_data(desc);
  185. struct pl061 *pl061 = gpiochip_get_data(gc);
  186. struct irq_chip *irqchip = irq_desc_get_chip(desc);
  187. chained_irq_enter(irqchip, desc);
  188. pending = readb(pl061->base + GPIOMIS);
  189. if (pending) {
  190. for_each_set_bit(offset, &pending, PL061_GPIO_NR)
  191. generic_handle_irq(irq_find_mapping(gc->irq.domain,
  192. offset));
  193. }
  194. chained_irq_exit(irqchip, desc);
  195. }
  196. static void pl061_irq_mask(struct irq_data *d)
  197. {
  198. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  199. struct pl061 *pl061 = gpiochip_get_data(gc);
  200. u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
  201. u8 gpioie;
  202. raw_spin_lock(&pl061->lock);
  203. gpioie = readb(pl061->base + GPIOIE) & ~mask;
  204. writeb(gpioie, pl061->base + GPIOIE);
  205. raw_spin_unlock(&pl061->lock);
  206. }
  207. static void pl061_irq_unmask(struct irq_data *d)
  208. {
  209. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  210. struct pl061 *pl061 = gpiochip_get_data(gc);
  211. u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
  212. u8 gpioie;
  213. raw_spin_lock(&pl061->lock);
  214. gpioie = readb(pl061->base + GPIOIE) | mask;
  215. writeb(gpioie, pl061->base + GPIOIE);
  216. raw_spin_unlock(&pl061->lock);
  217. }
  218. /**
  219. * pl061_irq_ack() - ACK an edge IRQ
  220. * @d: IRQ data for this IRQ
  221. *
  222. * This gets called from the edge IRQ handler to ACK the edge IRQ
  223. * in the GPIOIC (interrupt-clear) register. For level IRQs this is
  224. * not needed: these go away when the level signal goes away.
  225. */
  226. static void pl061_irq_ack(struct irq_data *d)
  227. {
  228. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  229. struct pl061 *pl061 = gpiochip_get_data(gc);
  230. u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
  231. raw_spin_lock(&pl061->lock);
  232. writeb(mask, pl061->base + GPIOIC);
  233. raw_spin_unlock(&pl061->lock);
  234. }
  235. static int pl061_irq_set_wake(struct irq_data *d, unsigned int state)
  236. {
  237. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  238. struct pl061 *pl061 = gpiochip_get_data(gc);
  239. return irq_set_irq_wake(pl061->parent_irq, state);
  240. }
  241. static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
  242. {
  243. struct device *dev = &adev->dev;
  244. struct pl061 *pl061;
  245. struct gpio_irq_chip *girq;
  246. int ret, irq;
  247. pl061 = devm_kzalloc(dev, sizeof(*pl061), GFP_KERNEL);
  248. if (pl061 == NULL)
  249. return -ENOMEM;
  250. pl061->base = devm_ioremap_resource(dev, &adev->res);
  251. if (IS_ERR(pl061->base))
  252. return PTR_ERR(pl061->base);
  253. raw_spin_lock_init(&pl061->lock);
  254. pl061->gc.request = gpiochip_generic_request;
  255. pl061->gc.free = gpiochip_generic_free;
  256. pl061->gc.base = -1;
  257. pl061->gc.get_direction = pl061_get_direction;
  258. pl061->gc.direction_input = pl061_direction_input;
  259. pl061->gc.direction_output = pl061_direction_output;
  260. pl061->gc.get = pl061_get_value;
  261. pl061->gc.set = pl061_set_value;
  262. pl061->gc.ngpio = PL061_GPIO_NR;
  263. pl061->gc.label = dev_name(dev);
  264. pl061->gc.parent = dev;
  265. pl061->gc.owner = THIS_MODULE;
  266. /*
  267. * irq_chip support
  268. */
  269. pl061->irq_chip.name = dev_name(dev);
  270. pl061->irq_chip.irq_ack = pl061_irq_ack;
  271. pl061->irq_chip.irq_mask = pl061_irq_mask;
  272. pl061->irq_chip.irq_unmask = pl061_irq_unmask;
  273. pl061->irq_chip.irq_set_type = pl061_irq_type;
  274. pl061->irq_chip.irq_set_wake = pl061_irq_set_wake;
  275. writeb(0, pl061->base + GPIOIE); /* disable irqs */
  276. irq = adev->irq[0];
  277. if (!irq)
  278. dev_warn(&adev->dev, "IRQ support disabled\n");
  279. pl061->parent_irq = irq;
  280. girq = &pl061->gc.irq;
  281. girq->chip = &pl061->irq_chip;
  282. girq->parent_handler = pl061_irq_handler;
  283. girq->num_parents = 1;
  284. girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),
  285. GFP_KERNEL);
  286. if (!girq->parents)
  287. return -ENOMEM;
  288. girq->parents[0] = irq;
  289. girq->default_type = IRQ_TYPE_NONE;
  290. girq->handler = handle_bad_irq;
  291. ret = devm_gpiochip_add_data(dev, &pl061->gc, pl061);
  292. if (ret)
  293. return ret;
  294. amba_set_drvdata(adev, pl061);
  295. dev_info(dev, "PL061 GPIO chip registered\n");
  296. return 0;
  297. }
  298. #ifdef CONFIG_PM
  299. static int pl061_suspend(struct device *dev)
  300. {
  301. struct pl061 *pl061 = dev_get_drvdata(dev);
  302. int offset;
  303. pl061->csave_regs.gpio_data = 0;
  304. pl061->csave_regs.gpio_dir = readb(pl061->base + GPIODIR);
  305. pl061->csave_regs.gpio_is = readb(pl061->base + GPIOIS);
  306. pl061->csave_regs.gpio_ibe = readb(pl061->base + GPIOIBE);
  307. pl061->csave_regs.gpio_iev = readb(pl061->base + GPIOIEV);
  308. pl061->csave_regs.gpio_ie = readb(pl061->base + GPIOIE);
  309. for (offset = 0; offset < PL061_GPIO_NR; offset++) {
  310. if (pl061->csave_regs.gpio_dir & (BIT(offset)))
  311. pl061->csave_regs.gpio_data |=
  312. pl061_get_value(&pl061->gc, offset) << offset;
  313. }
  314. return 0;
  315. }
  316. static int pl061_resume(struct device *dev)
  317. {
  318. struct pl061 *pl061 = dev_get_drvdata(dev);
  319. int offset;
  320. for (offset = 0; offset < PL061_GPIO_NR; offset++) {
  321. if (pl061->csave_regs.gpio_dir & (BIT(offset)))
  322. pl061_direction_output(&pl061->gc, offset,
  323. pl061->csave_regs.gpio_data &
  324. (BIT(offset)));
  325. else
  326. pl061_direction_input(&pl061->gc, offset);
  327. }
  328. writeb(pl061->csave_regs.gpio_is, pl061->base + GPIOIS);
  329. writeb(pl061->csave_regs.gpio_ibe, pl061->base + GPIOIBE);
  330. writeb(pl061->csave_regs.gpio_iev, pl061->base + GPIOIEV);
  331. writeb(pl061->csave_regs.gpio_ie, pl061->base + GPIOIE);
  332. return 0;
  333. }
  334. static const struct dev_pm_ops pl061_dev_pm_ops = {
  335. .suspend = pl061_suspend,
  336. .resume = pl061_resume,
  337. .freeze = pl061_suspend,
  338. .restore = pl061_resume,
  339. };
  340. #endif
  341. static const struct amba_id pl061_ids[] = {
  342. {
  343. .id = 0x00041061,
  344. .mask = 0x000fffff,
  345. },
  346. { 0, 0 },
  347. };
  348. MODULE_DEVICE_TABLE(amba, pl061_ids);
  349. static struct amba_driver pl061_gpio_driver = {
  350. .drv = {
  351. .name = "pl061_gpio",
  352. #ifdef CONFIG_PM
  353. .pm = &pl061_dev_pm_ops,
  354. #endif
  355. },
  356. .id_table = pl061_ids,
  357. .probe = pl061_probe,
  358. };
  359. module_amba_driver(pl061_gpio_driver);
  360. MODULE_LICENSE("GPL v2");