gpio-pcie-idio-24.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * GPIO driver for the ACCES PCIe-IDIO-24 family
  4. * Copyright (C) 2018 William Breathitt Gray
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License, version 2, as
  8. * published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. *
  15. * This driver supports the following ACCES devices: PCIe-IDIO-24,
  16. * PCIe-IDI-24, PCIe-IDO-24, and PCIe-IDIO-12.
  17. */
  18. #include <linux/bitmap.h>
  19. #include <linux/bitops.h>
  20. #include <linux/device.h>
  21. #include <linux/errno.h>
  22. #include <linux/gpio/driver.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/irqdesc.h>
  25. #include <linux/kernel.h>
  26. #include <linux/module.h>
  27. #include <linux/pci.h>
  28. #include <linux/spinlock.h>
  29. #include <linux/types.h>
  30. /*
  31. * PLX PEX8311 PCI LCS_INTCSR Interrupt Control/Status
  32. *
  33. * Bit: Description
  34. * 0: Enable Interrupt Sources (Bit 0)
  35. * 1: Enable Interrupt Sources (Bit 1)
  36. * 2: Generate Internal PCI Bus Internal SERR# Interrupt
  37. * 3: Mailbox Interrupt Enable
  38. * 4: Power Management Interrupt Enable
  39. * 5: Power Management Interrupt
  40. * 6: Slave Read Local Data Parity Check Error Enable
  41. * 7: Slave Read Local Data Parity Check Error Status
  42. * 8: Internal PCI Wire Interrupt Enable
  43. * 9: PCI Express Doorbell Interrupt Enable
  44. * 10: PCI Abort Interrupt Enable
  45. * 11: Local Interrupt Input Enable
  46. * 12: Retry Abort Enable
  47. * 13: PCI Express Doorbell Interrupt Active
  48. * 14: PCI Abort Interrupt Active
  49. * 15: Local Interrupt Input Active
  50. * 16: Local Interrupt Output Enable
  51. * 17: Local Doorbell Interrupt Enable
  52. * 18: DMA Channel 0 Interrupt Enable
  53. * 19: DMA Channel 1 Interrupt Enable
  54. * 20: Local Doorbell Interrupt Active
  55. * 21: DMA Channel 0 Interrupt Active
  56. * 22: DMA Channel 1 Interrupt Active
  57. * 23: Built-In Self-Test (BIST) Interrupt Active
  58. * 24: Direct Master was the Bus Master during a Master or Target Abort
  59. * 25: DMA Channel 0 was the Bus Master during a Master or Target Abort
  60. * 26: DMA Channel 1 was the Bus Master during a Master or Target Abort
  61. * 27: Target Abort after internal 256 consecutive Master Retrys
  62. * 28: PCI Bus wrote data to LCS_MBOX0
  63. * 29: PCI Bus wrote data to LCS_MBOX1
  64. * 30: PCI Bus wrote data to LCS_MBOX2
  65. * 31: PCI Bus wrote data to LCS_MBOX3
  66. */
  67. #define PLX_PEX8311_PCI_LCS_INTCSR 0x68
  68. #define INTCSR_INTERNAL_PCI_WIRE BIT(8)
  69. #define INTCSR_LOCAL_INPUT BIT(11)
  70. /**
  71. * struct idio_24_gpio_reg - GPIO device registers structure
  72. * @out0_7: Read: FET Outputs 0-7
  73. * Write: FET Outputs 0-7
  74. * @out8_15: Read: FET Outputs 8-15
  75. * Write: FET Outputs 8-15
  76. * @out16_23: Read: FET Outputs 16-23
  77. * Write: FET Outputs 16-23
  78. * @ttl_out0_7: Read: TTL/CMOS Outputs 0-7
  79. * Write: TTL/CMOS Outputs 0-7
  80. * @in0_7: Read: Isolated Inputs 0-7
  81. * Write: Reserved
  82. * @in8_15: Read: Isolated Inputs 8-15
  83. * Write: Reserved
  84. * @in16_23: Read: Isolated Inputs 16-23
  85. * Write: Reserved
  86. * @ttl_in0_7: Read: TTL/CMOS Inputs 0-7
  87. * Write: Reserved
  88. * @cos0_7: Read: COS Status Inputs 0-7
  89. * Write: COS Clear Inputs 0-7
  90. * @cos8_15: Read: COS Status Inputs 8-15
  91. * Write: COS Clear Inputs 8-15
  92. * @cos16_23: Read: COS Status Inputs 16-23
  93. * Write: COS Clear Inputs 16-23
  94. * @cos_ttl0_7: Read: COS Status TTL/CMOS 0-7
  95. * Write: COS Clear TTL/CMOS 0-7
  96. * @ctl: Read: Control Register
  97. * Write: Control Register
  98. * @reserved: Read: Reserved
  99. * Write: Reserved
  100. * @cos_enable: Read: COS Enable
  101. * Write: COS Enable
  102. * @soft_reset: Read: IRQ Output Pin Status
  103. * Write: Software Board Reset
  104. */
  105. struct idio_24_gpio_reg {
  106. u8 out0_7;
  107. u8 out8_15;
  108. u8 out16_23;
  109. u8 ttl_out0_7;
  110. u8 in0_7;
  111. u8 in8_15;
  112. u8 in16_23;
  113. u8 ttl_in0_7;
  114. u8 cos0_7;
  115. u8 cos8_15;
  116. u8 cos16_23;
  117. u8 cos_ttl0_7;
  118. u8 ctl;
  119. u8 reserved;
  120. u8 cos_enable;
  121. u8 soft_reset;
  122. };
  123. /**
  124. * struct idio_24_gpio - GPIO device private data structure
  125. * @chip: instance of the gpio_chip
  126. * @lock: synchronization lock to prevent I/O race conditions
  127. * @reg: I/O address offset for the GPIO device registers
  128. * @irq_mask: I/O bits affected by interrupts
  129. */
  130. struct idio_24_gpio {
  131. struct gpio_chip chip;
  132. raw_spinlock_t lock;
  133. __u8 __iomem *plx;
  134. struct idio_24_gpio_reg __iomem *reg;
  135. unsigned long irq_mask;
  136. };
  137. static int idio_24_gpio_get_direction(struct gpio_chip *chip,
  138. unsigned int offset)
  139. {
  140. struct idio_24_gpio *const idio24gpio = gpiochip_get_data(chip);
  141. const unsigned long out_mode_mask = BIT(1);
  142. /* FET Outputs */
  143. if (offset < 24)
  144. return GPIO_LINE_DIRECTION_OUT;
  145. /* Isolated Inputs */
  146. if (offset < 48)
  147. return GPIO_LINE_DIRECTION_IN;
  148. /* TTL/CMOS I/O */
  149. /* OUT MODE = 1 when TTL/CMOS Output Mode is set */
  150. if (ioread8(&idio24gpio->reg->ctl) & out_mode_mask)
  151. return GPIO_LINE_DIRECTION_OUT;
  152. return GPIO_LINE_DIRECTION_IN;
  153. }
  154. static int idio_24_gpio_direction_input(struct gpio_chip *chip,
  155. unsigned int offset)
  156. {
  157. struct idio_24_gpio *const idio24gpio = gpiochip_get_data(chip);
  158. unsigned long flags;
  159. unsigned int ctl_state;
  160. const unsigned long out_mode_mask = BIT(1);
  161. /* TTL/CMOS I/O */
  162. if (offset > 47) {
  163. raw_spin_lock_irqsave(&idio24gpio->lock, flags);
  164. /* Clear TTL/CMOS Output Mode */
  165. ctl_state = ioread8(&idio24gpio->reg->ctl) & ~out_mode_mask;
  166. iowrite8(ctl_state, &idio24gpio->reg->ctl);
  167. raw_spin_unlock_irqrestore(&idio24gpio->lock, flags);
  168. }
  169. return 0;
  170. }
  171. static int idio_24_gpio_direction_output(struct gpio_chip *chip,
  172. unsigned int offset, int value)
  173. {
  174. struct idio_24_gpio *const idio24gpio = gpiochip_get_data(chip);
  175. unsigned long flags;
  176. unsigned int ctl_state;
  177. const unsigned long out_mode_mask = BIT(1);
  178. /* TTL/CMOS I/O */
  179. if (offset > 47) {
  180. raw_spin_lock_irqsave(&idio24gpio->lock, flags);
  181. /* Set TTL/CMOS Output Mode */
  182. ctl_state = ioread8(&idio24gpio->reg->ctl) | out_mode_mask;
  183. iowrite8(ctl_state, &idio24gpio->reg->ctl);
  184. raw_spin_unlock_irqrestore(&idio24gpio->lock, flags);
  185. }
  186. chip->set(chip, offset, value);
  187. return 0;
  188. }
  189. static int idio_24_gpio_get(struct gpio_chip *chip, unsigned int offset)
  190. {
  191. struct idio_24_gpio *const idio24gpio = gpiochip_get_data(chip);
  192. const unsigned long offset_mask = BIT(offset % 8);
  193. const unsigned long out_mode_mask = BIT(1);
  194. /* FET Outputs */
  195. if (offset < 8)
  196. return !!(ioread8(&idio24gpio->reg->out0_7) & offset_mask);
  197. if (offset < 16)
  198. return !!(ioread8(&idio24gpio->reg->out8_15) & offset_mask);
  199. if (offset < 24)
  200. return !!(ioread8(&idio24gpio->reg->out16_23) & offset_mask);
  201. /* Isolated Inputs */
  202. if (offset < 32)
  203. return !!(ioread8(&idio24gpio->reg->in0_7) & offset_mask);
  204. if (offset < 40)
  205. return !!(ioread8(&idio24gpio->reg->in8_15) & offset_mask);
  206. if (offset < 48)
  207. return !!(ioread8(&idio24gpio->reg->in16_23) & offset_mask);
  208. /* TTL/CMOS Outputs */
  209. if (ioread8(&idio24gpio->reg->ctl) & out_mode_mask)
  210. return !!(ioread8(&idio24gpio->reg->ttl_out0_7) & offset_mask);
  211. /* TTL/CMOS Inputs */
  212. return !!(ioread8(&idio24gpio->reg->ttl_in0_7) & offset_mask);
  213. }
  214. static int idio_24_gpio_get_multiple(struct gpio_chip *chip,
  215. unsigned long *mask, unsigned long *bits)
  216. {
  217. struct idio_24_gpio *const idio24gpio = gpiochip_get_data(chip);
  218. unsigned long offset;
  219. unsigned long gpio_mask;
  220. void __iomem *ports[] = {
  221. &idio24gpio->reg->out0_7, &idio24gpio->reg->out8_15,
  222. &idio24gpio->reg->out16_23, &idio24gpio->reg->in0_7,
  223. &idio24gpio->reg->in8_15, &idio24gpio->reg->in16_23,
  224. };
  225. size_t index;
  226. unsigned long port_state;
  227. const unsigned long out_mode_mask = BIT(1);
  228. /* clear bits array to a clean slate */
  229. bitmap_zero(bits, chip->ngpio);
  230. for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) {
  231. index = offset / 8;
  232. /* read bits from current gpio port (port 6 is TTL GPIO) */
  233. if (index < 6)
  234. port_state = ioread8(ports[index]);
  235. else if (ioread8(&idio24gpio->reg->ctl) & out_mode_mask)
  236. port_state = ioread8(&idio24gpio->reg->ttl_out0_7);
  237. else
  238. port_state = ioread8(&idio24gpio->reg->ttl_in0_7);
  239. port_state &= gpio_mask;
  240. bitmap_set_value8(bits, port_state, offset);
  241. }
  242. return 0;
  243. }
  244. static void idio_24_gpio_set(struct gpio_chip *chip, unsigned int offset,
  245. int value)
  246. {
  247. struct idio_24_gpio *const idio24gpio = gpiochip_get_data(chip);
  248. const unsigned long out_mode_mask = BIT(1);
  249. void __iomem *base;
  250. const unsigned int mask = BIT(offset % 8);
  251. unsigned long flags;
  252. unsigned int out_state;
  253. /* Isolated Inputs */
  254. if (offset > 23 && offset < 48)
  255. return;
  256. /* TTL/CMOS Inputs */
  257. if (offset > 47 && !(ioread8(&idio24gpio->reg->ctl) & out_mode_mask))
  258. return;
  259. /* TTL/CMOS Outputs */
  260. if (offset > 47)
  261. base = &idio24gpio->reg->ttl_out0_7;
  262. /* FET Outputs */
  263. else if (offset > 15)
  264. base = &idio24gpio->reg->out16_23;
  265. else if (offset > 7)
  266. base = &idio24gpio->reg->out8_15;
  267. else
  268. base = &idio24gpio->reg->out0_7;
  269. raw_spin_lock_irqsave(&idio24gpio->lock, flags);
  270. if (value)
  271. out_state = ioread8(base) | mask;
  272. else
  273. out_state = ioread8(base) & ~mask;
  274. iowrite8(out_state, base);
  275. raw_spin_unlock_irqrestore(&idio24gpio->lock, flags);
  276. }
  277. static void idio_24_gpio_set_multiple(struct gpio_chip *chip,
  278. unsigned long *mask, unsigned long *bits)
  279. {
  280. struct idio_24_gpio *const idio24gpio = gpiochip_get_data(chip);
  281. unsigned long offset;
  282. unsigned long gpio_mask;
  283. void __iomem *ports[] = {
  284. &idio24gpio->reg->out0_7, &idio24gpio->reg->out8_15,
  285. &idio24gpio->reg->out16_23
  286. };
  287. size_t index;
  288. unsigned long bitmask;
  289. unsigned long flags;
  290. unsigned long out_state;
  291. const unsigned long out_mode_mask = BIT(1);
  292. for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) {
  293. index = offset / 8;
  294. bitmask = bitmap_get_value8(bits, offset) & gpio_mask;
  295. raw_spin_lock_irqsave(&idio24gpio->lock, flags);
  296. /* read bits from current gpio port (port 6 is TTL GPIO) */
  297. if (index < 6) {
  298. out_state = ioread8(ports[index]);
  299. } else if (ioread8(&idio24gpio->reg->ctl) & out_mode_mask) {
  300. out_state = ioread8(&idio24gpio->reg->ttl_out0_7);
  301. } else {
  302. /* skip TTL GPIO if set for input */
  303. raw_spin_unlock_irqrestore(&idio24gpio->lock, flags);
  304. continue;
  305. }
  306. /* set requested bit states */
  307. out_state &= ~gpio_mask;
  308. out_state |= bitmask;
  309. /* write bits for current gpio port (port 6 is TTL GPIO) */
  310. if (index < 6)
  311. iowrite8(out_state, ports[index]);
  312. else
  313. iowrite8(out_state, &idio24gpio->reg->ttl_out0_7);
  314. raw_spin_unlock_irqrestore(&idio24gpio->lock, flags);
  315. }
  316. }
  317. static void idio_24_irq_ack(struct irq_data *data)
  318. {
  319. }
  320. static void idio_24_irq_mask(struct irq_data *data)
  321. {
  322. struct gpio_chip *const chip = irq_data_get_irq_chip_data(data);
  323. struct idio_24_gpio *const idio24gpio = gpiochip_get_data(chip);
  324. unsigned long flags;
  325. const unsigned long bit_offset = irqd_to_hwirq(data) - 24;
  326. unsigned char new_irq_mask;
  327. const unsigned long bank_offset = bit_offset / 8;
  328. unsigned char cos_enable_state;
  329. raw_spin_lock_irqsave(&idio24gpio->lock, flags);
  330. idio24gpio->irq_mask &= ~BIT(bit_offset);
  331. new_irq_mask = idio24gpio->irq_mask >> bank_offset * 8;
  332. if (!new_irq_mask) {
  333. cos_enable_state = ioread8(&idio24gpio->reg->cos_enable);
  334. /* Disable Rising Edge detection */
  335. cos_enable_state &= ~BIT(bank_offset);
  336. /* Disable Falling Edge detection */
  337. cos_enable_state &= ~BIT(bank_offset + 4);
  338. iowrite8(cos_enable_state, &idio24gpio->reg->cos_enable);
  339. }
  340. raw_spin_unlock_irqrestore(&idio24gpio->lock, flags);
  341. }
  342. static void idio_24_irq_unmask(struct irq_data *data)
  343. {
  344. struct gpio_chip *const chip = irq_data_get_irq_chip_data(data);
  345. struct idio_24_gpio *const idio24gpio = gpiochip_get_data(chip);
  346. unsigned long flags;
  347. unsigned char prev_irq_mask;
  348. const unsigned long bit_offset = irqd_to_hwirq(data) - 24;
  349. const unsigned long bank_offset = bit_offset / 8;
  350. unsigned char cos_enable_state;
  351. raw_spin_lock_irqsave(&idio24gpio->lock, flags);
  352. prev_irq_mask = idio24gpio->irq_mask >> bank_offset * 8;
  353. idio24gpio->irq_mask |= BIT(bit_offset);
  354. if (!prev_irq_mask) {
  355. cos_enable_state = ioread8(&idio24gpio->reg->cos_enable);
  356. /* Enable Rising Edge detection */
  357. cos_enable_state |= BIT(bank_offset);
  358. /* Enable Falling Edge detection */
  359. cos_enable_state |= BIT(bank_offset + 4);
  360. iowrite8(cos_enable_state, &idio24gpio->reg->cos_enable);
  361. }
  362. raw_spin_unlock_irqrestore(&idio24gpio->lock, flags);
  363. }
  364. static int idio_24_irq_set_type(struct irq_data *data, unsigned int flow_type)
  365. {
  366. /* The only valid irq types are none and both-edges */
  367. if (flow_type != IRQ_TYPE_NONE &&
  368. (flow_type & IRQ_TYPE_EDGE_BOTH) != IRQ_TYPE_EDGE_BOTH)
  369. return -EINVAL;
  370. return 0;
  371. }
  372. static struct irq_chip idio_24_irqchip = {
  373. .name = "pcie-idio-24",
  374. .irq_ack = idio_24_irq_ack,
  375. .irq_mask = idio_24_irq_mask,
  376. .irq_unmask = idio_24_irq_unmask,
  377. .irq_set_type = idio_24_irq_set_type
  378. };
  379. static irqreturn_t idio_24_irq_handler(int irq, void *dev_id)
  380. {
  381. struct idio_24_gpio *const idio24gpio = dev_id;
  382. unsigned long irq_status;
  383. struct gpio_chip *const chip = &idio24gpio->chip;
  384. unsigned long irq_mask;
  385. int gpio;
  386. raw_spin_lock(&idio24gpio->lock);
  387. /* Read Change-Of-State status */
  388. irq_status = ioread32(&idio24gpio->reg->cos0_7);
  389. raw_spin_unlock(&idio24gpio->lock);
  390. /* Make sure our device generated IRQ */
  391. if (!irq_status)
  392. return IRQ_NONE;
  393. /* Handle only unmasked IRQ */
  394. irq_mask = idio24gpio->irq_mask & irq_status;
  395. for_each_set_bit(gpio, &irq_mask, chip->ngpio - 24)
  396. generic_handle_irq(irq_find_mapping(chip->irq.domain,
  397. gpio + 24));
  398. raw_spin_lock(&idio24gpio->lock);
  399. /* Clear Change-Of-State status */
  400. iowrite32(irq_status, &idio24gpio->reg->cos0_7);
  401. raw_spin_unlock(&idio24gpio->lock);
  402. return IRQ_HANDLED;
  403. }
  404. #define IDIO_24_NGPIO 56
  405. static const char *idio_24_names[IDIO_24_NGPIO] = {
  406. "OUT0", "OUT1", "OUT2", "OUT3", "OUT4", "OUT5", "OUT6", "OUT7",
  407. "OUT8", "OUT9", "OUT10", "OUT11", "OUT12", "OUT13", "OUT14", "OUT15",
  408. "OUT16", "OUT17", "OUT18", "OUT19", "OUT20", "OUT21", "OUT22", "OUT23",
  409. "IIN0", "IIN1", "IIN2", "IIN3", "IIN4", "IIN5", "IIN6", "IIN7",
  410. "IIN8", "IIN9", "IIN10", "IIN11", "IIN12", "IIN13", "IIN14", "IIN15",
  411. "IIN16", "IIN17", "IIN18", "IIN19", "IIN20", "IIN21", "IIN22", "IIN23",
  412. "TTL0", "TTL1", "TTL2", "TTL3", "TTL4", "TTL5", "TTL6", "TTL7"
  413. };
  414. static int idio_24_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  415. {
  416. struct device *const dev = &pdev->dev;
  417. struct idio_24_gpio *idio24gpio;
  418. int err;
  419. const size_t pci_plx_bar_index = 1;
  420. const size_t pci_bar_index = 2;
  421. const char *const name = pci_name(pdev);
  422. struct gpio_irq_chip *girq;
  423. idio24gpio = devm_kzalloc(dev, sizeof(*idio24gpio), GFP_KERNEL);
  424. if (!idio24gpio)
  425. return -ENOMEM;
  426. err = pcim_enable_device(pdev);
  427. if (err) {
  428. dev_err(dev, "Failed to enable PCI device (%d)\n", err);
  429. return err;
  430. }
  431. err = pcim_iomap_regions(pdev, BIT(pci_plx_bar_index) | BIT(pci_bar_index), name);
  432. if (err) {
  433. dev_err(dev, "Unable to map PCI I/O addresses (%d)\n", err);
  434. return err;
  435. }
  436. idio24gpio->plx = pcim_iomap_table(pdev)[pci_plx_bar_index];
  437. idio24gpio->reg = pcim_iomap_table(pdev)[pci_bar_index];
  438. idio24gpio->chip.label = name;
  439. idio24gpio->chip.parent = dev;
  440. idio24gpio->chip.owner = THIS_MODULE;
  441. idio24gpio->chip.base = -1;
  442. idio24gpio->chip.ngpio = IDIO_24_NGPIO;
  443. idio24gpio->chip.names = idio_24_names;
  444. idio24gpio->chip.get_direction = idio_24_gpio_get_direction;
  445. idio24gpio->chip.direction_input = idio_24_gpio_direction_input;
  446. idio24gpio->chip.direction_output = idio_24_gpio_direction_output;
  447. idio24gpio->chip.get = idio_24_gpio_get;
  448. idio24gpio->chip.get_multiple = idio_24_gpio_get_multiple;
  449. idio24gpio->chip.set = idio_24_gpio_set;
  450. idio24gpio->chip.set_multiple = idio_24_gpio_set_multiple;
  451. girq = &idio24gpio->chip.irq;
  452. girq->chip = &idio_24_irqchip;
  453. /* This will let us handle the parent IRQ in the driver */
  454. girq->parent_handler = NULL;
  455. girq->num_parents = 0;
  456. girq->parents = NULL;
  457. girq->default_type = IRQ_TYPE_NONE;
  458. girq->handler = handle_edge_irq;
  459. raw_spin_lock_init(&idio24gpio->lock);
  460. /* Software board reset */
  461. iowrite8(0, &idio24gpio->reg->soft_reset);
  462. /*
  463. * enable PLX PEX8311 internal PCI wire interrupt and local interrupt
  464. * input
  465. */
  466. iowrite8((INTCSR_INTERNAL_PCI_WIRE | INTCSR_LOCAL_INPUT) >> 8,
  467. idio24gpio->plx + PLX_PEX8311_PCI_LCS_INTCSR + 1);
  468. err = devm_gpiochip_add_data(dev, &idio24gpio->chip, idio24gpio);
  469. if (err) {
  470. dev_err(dev, "GPIO registering failed (%d)\n", err);
  471. return err;
  472. }
  473. err = devm_request_irq(dev, pdev->irq, idio_24_irq_handler, IRQF_SHARED,
  474. name, idio24gpio);
  475. if (err) {
  476. dev_err(dev, "IRQ handler registering failed (%d)\n", err);
  477. return err;
  478. }
  479. return 0;
  480. }
  481. static const struct pci_device_id idio_24_pci_dev_id[] = {
  482. { PCI_DEVICE(0x494F, 0x0FD0) }, { PCI_DEVICE(0x494F, 0x0BD0) },
  483. { PCI_DEVICE(0x494F, 0x07D0) }, { PCI_DEVICE(0x494F, 0x0FC0) },
  484. { 0 }
  485. };
  486. MODULE_DEVICE_TABLE(pci, idio_24_pci_dev_id);
  487. static struct pci_driver idio_24_driver = {
  488. .name = "pcie-idio-24",
  489. .id_table = idio_24_pci_dev_id,
  490. .probe = idio_24_probe
  491. };
  492. module_pci_driver(idio_24_driver);
  493. MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
  494. MODULE_DESCRIPTION("ACCES PCIe-IDIO-24 GPIO driver");
  495. MODULE_LICENSE("GPL v2");