gpio-pci-idio-16.c 9.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * GPIO driver for the ACCES PCI-IDIO-16
  4. * Copyright (C) 2017 William Breathitt Gray
  5. */
  6. #include <linux/bitmap.h>
  7. #include <linux/bitops.h>
  8. #include <linux/device.h>
  9. #include <linux/errno.h>
  10. #include <linux/gpio/driver.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/irqdesc.h>
  13. #include <linux/kernel.h>
  14. #include <linux/module.h>
  15. #include <linux/pci.h>
  16. #include <linux/spinlock.h>
  17. #include <linux/types.h>
  18. /**
  19. * struct idio_16_gpio_reg - GPIO device registers structure
  20. * @out0_7: Read: FET Drive Outputs 0-7
  21. * Write: FET Drive Outputs 0-7
  22. * @in0_7: Read: Isolated Inputs 0-7
  23. * Write: Clear Interrupt
  24. * @irq_ctl: Read: Enable IRQ
  25. * Write: Disable IRQ
  26. * @filter_ctl: Read: Activate Input Filters 0-15
  27. * Write: Deactivate Input Filters 0-15
  28. * @out8_15: Read: FET Drive Outputs 8-15
  29. * Write: FET Drive Outputs 8-15
  30. * @in8_15: Read: Isolated Inputs 8-15
  31. * Write: Unused
  32. * @irq_status: Read: Interrupt status
  33. * Write: Unused
  34. */
  35. struct idio_16_gpio_reg {
  36. u8 out0_7;
  37. u8 in0_7;
  38. u8 irq_ctl;
  39. u8 filter_ctl;
  40. u8 out8_15;
  41. u8 in8_15;
  42. u8 irq_status;
  43. };
  44. /**
  45. * struct idio_16_gpio - GPIO device private data structure
  46. * @chip: instance of the gpio_chip
  47. * @lock: synchronization lock to prevent I/O race conditions
  48. * @reg: I/O address offset for the GPIO device registers
  49. * @irq_mask: I/O bits affected by interrupts
  50. */
  51. struct idio_16_gpio {
  52. struct gpio_chip chip;
  53. raw_spinlock_t lock;
  54. struct idio_16_gpio_reg __iomem *reg;
  55. unsigned long irq_mask;
  56. };
  57. static int idio_16_gpio_get_direction(struct gpio_chip *chip,
  58. unsigned int offset)
  59. {
  60. if (offset > 15)
  61. return GPIO_LINE_DIRECTION_IN;
  62. return GPIO_LINE_DIRECTION_OUT;
  63. }
  64. static int idio_16_gpio_direction_input(struct gpio_chip *chip,
  65. unsigned int offset)
  66. {
  67. return 0;
  68. }
  69. static int idio_16_gpio_direction_output(struct gpio_chip *chip,
  70. unsigned int offset, int value)
  71. {
  72. chip->set(chip, offset, value);
  73. return 0;
  74. }
  75. static int idio_16_gpio_get(struct gpio_chip *chip, unsigned int offset)
  76. {
  77. struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
  78. unsigned long mask = BIT(offset);
  79. if (offset < 8)
  80. return !!(ioread8(&idio16gpio->reg->out0_7) & mask);
  81. if (offset < 16)
  82. return !!(ioread8(&idio16gpio->reg->out8_15) & (mask >> 8));
  83. if (offset < 24)
  84. return !!(ioread8(&idio16gpio->reg->in0_7) & (mask >> 16));
  85. return !!(ioread8(&idio16gpio->reg->in8_15) & (mask >> 24));
  86. }
  87. static int idio_16_gpio_get_multiple(struct gpio_chip *chip,
  88. unsigned long *mask, unsigned long *bits)
  89. {
  90. struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
  91. unsigned long offset;
  92. unsigned long gpio_mask;
  93. void __iomem *ports[] = {
  94. &idio16gpio->reg->out0_7, &idio16gpio->reg->out8_15,
  95. &idio16gpio->reg->in0_7, &idio16gpio->reg->in8_15,
  96. };
  97. void __iomem *port_addr;
  98. unsigned long port_state;
  99. /* clear bits array to a clean slate */
  100. bitmap_zero(bits, chip->ngpio);
  101. for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) {
  102. port_addr = ports[offset / 8];
  103. port_state = ioread8(port_addr) & gpio_mask;
  104. bitmap_set_value8(bits, port_state, offset);
  105. }
  106. return 0;
  107. }
  108. static void idio_16_gpio_set(struct gpio_chip *chip, unsigned int offset,
  109. int value)
  110. {
  111. struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
  112. unsigned int mask = BIT(offset);
  113. void __iomem *base;
  114. unsigned long flags;
  115. unsigned int out_state;
  116. if (offset > 15)
  117. return;
  118. if (offset > 7) {
  119. mask >>= 8;
  120. base = &idio16gpio->reg->out8_15;
  121. } else
  122. base = &idio16gpio->reg->out0_7;
  123. raw_spin_lock_irqsave(&idio16gpio->lock, flags);
  124. if (value)
  125. out_state = ioread8(base) | mask;
  126. else
  127. out_state = ioread8(base) & ~mask;
  128. iowrite8(out_state, base);
  129. raw_spin_unlock_irqrestore(&idio16gpio->lock, flags);
  130. }
  131. static void idio_16_gpio_set_multiple(struct gpio_chip *chip,
  132. unsigned long *mask, unsigned long *bits)
  133. {
  134. struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
  135. unsigned long offset;
  136. unsigned long gpio_mask;
  137. void __iomem *ports[] = {
  138. &idio16gpio->reg->out0_7, &idio16gpio->reg->out8_15,
  139. };
  140. size_t index;
  141. void __iomem *port_addr;
  142. unsigned long bitmask;
  143. unsigned long flags;
  144. unsigned long out_state;
  145. for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) {
  146. index = offset / 8;
  147. port_addr = ports[index];
  148. bitmask = bitmap_get_value8(bits, offset) & gpio_mask;
  149. raw_spin_lock_irqsave(&idio16gpio->lock, flags);
  150. out_state = ioread8(port_addr) & ~gpio_mask;
  151. out_state |= bitmask;
  152. iowrite8(out_state, port_addr);
  153. raw_spin_unlock_irqrestore(&idio16gpio->lock, flags);
  154. }
  155. }
  156. static void idio_16_irq_ack(struct irq_data *data)
  157. {
  158. }
  159. static void idio_16_irq_mask(struct irq_data *data)
  160. {
  161. struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
  162. struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
  163. const unsigned long mask = BIT(irqd_to_hwirq(data));
  164. unsigned long flags;
  165. idio16gpio->irq_mask &= ~mask;
  166. if (!idio16gpio->irq_mask) {
  167. raw_spin_lock_irqsave(&idio16gpio->lock, flags);
  168. iowrite8(0, &idio16gpio->reg->irq_ctl);
  169. raw_spin_unlock_irqrestore(&idio16gpio->lock, flags);
  170. }
  171. }
  172. static void idio_16_irq_unmask(struct irq_data *data)
  173. {
  174. struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
  175. struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
  176. const unsigned long mask = BIT(irqd_to_hwirq(data));
  177. const unsigned long prev_irq_mask = idio16gpio->irq_mask;
  178. unsigned long flags;
  179. idio16gpio->irq_mask |= mask;
  180. if (!prev_irq_mask) {
  181. raw_spin_lock_irqsave(&idio16gpio->lock, flags);
  182. ioread8(&idio16gpio->reg->irq_ctl);
  183. raw_spin_unlock_irqrestore(&idio16gpio->lock, flags);
  184. }
  185. }
  186. static int idio_16_irq_set_type(struct irq_data *data, unsigned int flow_type)
  187. {
  188. /* The only valid irq types are none and both-edges */
  189. if (flow_type != IRQ_TYPE_NONE &&
  190. (flow_type & IRQ_TYPE_EDGE_BOTH) != IRQ_TYPE_EDGE_BOTH)
  191. return -EINVAL;
  192. return 0;
  193. }
  194. static struct irq_chip idio_16_irqchip = {
  195. .name = "pci-idio-16",
  196. .irq_ack = idio_16_irq_ack,
  197. .irq_mask = idio_16_irq_mask,
  198. .irq_unmask = idio_16_irq_unmask,
  199. .irq_set_type = idio_16_irq_set_type
  200. };
  201. static irqreturn_t idio_16_irq_handler(int irq, void *dev_id)
  202. {
  203. struct idio_16_gpio *const idio16gpio = dev_id;
  204. unsigned int irq_status;
  205. struct gpio_chip *const chip = &idio16gpio->chip;
  206. int gpio;
  207. raw_spin_lock(&idio16gpio->lock);
  208. irq_status = ioread8(&idio16gpio->reg->irq_status);
  209. raw_spin_unlock(&idio16gpio->lock);
  210. /* Make sure our device generated IRQ */
  211. if (!(irq_status & 0x3) || !(irq_status & 0x4))
  212. return IRQ_NONE;
  213. for_each_set_bit(gpio, &idio16gpio->irq_mask, chip->ngpio)
  214. generic_handle_irq(irq_find_mapping(chip->irq.domain, gpio));
  215. raw_spin_lock(&idio16gpio->lock);
  216. /* Clear interrupt */
  217. iowrite8(0, &idio16gpio->reg->in0_7);
  218. raw_spin_unlock(&idio16gpio->lock);
  219. return IRQ_HANDLED;
  220. }
  221. #define IDIO_16_NGPIO 32
  222. static const char *idio_16_names[IDIO_16_NGPIO] = {
  223. "OUT0", "OUT1", "OUT2", "OUT3", "OUT4", "OUT5", "OUT6", "OUT7",
  224. "OUT8", "OUT9", "OUT10", "OUT11", "OUT12", "OUT13", "OUT14", "OUT15",
  225. "IIN0", "IIN1", "IIN2", "IIN3", "IIN4", "IIN5", "IIN6", "IIN7",
  226. "IIN8", "IIN9", "IIN10", "IIN11", "IIN12", "IIN13", "IIN14", "IIN15"
  227. };
  228. static int idio_16_irq_init_hw(struct gpio_chip *gc)
  229. {
  230. struct idio_16_gpio *const idio16gpio = gpiochip_get_data(gc);
  231. /* Disable IRQ by default and clear any pending interrupt */
  232. iowrite8(0, &idio16gpio->reg->irq_ctl);
  233. iowrite8(0, &idio16gpio->reg->in0_7);
  234. return 0;
  235. }
  236. static int idio_16_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  237. {
  238. struct device *const dev = &pdev->dev;
  239. struct idio_16_gpio *idio16gpio;
  240. int err;
  241. const size_t pci_bar_index = 2;
  242. const char *const name = pci_name(pdev);
  243. struct gpio_irq_chip *girq;
  244. idio16gpio = devm_kzalloc(dev, sizeof(*idio16gpio), GFP_KERNEL);
  245. if (!idio16gpio)
  246. return -ENOMEM;
  247. err = pcim_enable_device(pdev);
  248. if (err) {
  249. dev_err(dev, "Failed to enable PCI device (%d)\n", err);
  250. return err;
  251. }
  252. err = pcim_iomap_regions(pdev, BIT(pci_bar_index), name);
  253. if (err) {
  254. dev_err(dev, "Unable to map PCI I/O addresses (%d)\n", err);
  255. return err;
  256. }
  257. idio16gpio->reg = pcim_iomap_table(pdev)[pci_bar_index];
  258. /* Deactivate input filters */
  259. iowrite8(0, &idio16gpio->reg->filter_ctl);
  260. idio16gpio->chip.label = name;
  261. idio16gpio->chip.parent = dev;
  262. idio16gpio->chip.owner = THIS_MODULE;
  263. idio16gpio->chip.base = -1;
  264. idio16gpio->chip.ngpio = IDIO_16_NGPIO;
  265. idio16gpio->chip.names = idio_16_names;
  266. idio16gpio->chip.get_direction = idio_16_gpio_get_direction;
  267. idio16gpio->chip.direction_input = idio_16_gpio_direction_input;
  268. idio16gpio->chip.direction_output = idio_16_gpio_direction_output;
  269. idio16gpio->chip.get = idio_16_gpio_get;
  270. idio16gpio->chip.get_multiple = idio_16_gpio_get_multiple;
  271. idio16gpio->chip.set = idio_16_gpio_set;
  272. idio16gpio->chip.set_multiple = idio_16_gpio_set_multiple;
  273. girq = &idio16gpio->chip.irq;
  274. girq->chip = &idio_16_irqchip;
  275. /* This will let us handle the parent IRQ in the driver */
  276. girq->parent_handler = NULL;
  277. girq->num_parents = 0;
  278. girq->parents = NULL;
  279. girq->default_type = IRQ_TYPE_NONE;
  280. girq->handler = handle_edge_irq;
  281. girq->init_hw = idio_16_irq_init_hw;
  282. raw_spin_lock_init(&idio16gpio->lock);
  283. err = devm_gpiochip_add_data(dev, &idio16gpio->chip, idio16gpio);
  284. if (err) {
  285. dev_err(dev, "GPIO registering failed (%d)\n", err);
  286. return err;
  287. }
  288. err = devm_request_irq(dev, pdev->irq, idio_16_irq_handler, IRQF_SHARED,
  289. name, idio16gpio);
  290. if (err) {
  291. dev_err(dev, "IRQ handler registering failed (%d)\n", err);
  292. return err;
  293. }
  294. return 0;
  295. }
  296. static const struct pci_device_id idio_16_pci_dev_id[] = {
  297. { PCI_DEVICE(0x494F, 0x0DC8) }, { 0 }
  298. };
  299. MODULE_DEVICE_TABLE(pci, idio_16_pci_dev_id);
  300. static struct pci_driver idio_16_driver = {
  301. .name = "pci-idio-16",
  302. .id_table = idio_16_pci_dev_id,
  303. .probe = idio_16_probe
  304. };
  305. module_pci_driver(idio_16_driver);
  306. MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
  307. MODULE_DESCRIPTION("ACCES PCI-IDIO-16 GPIO driver");
  308. MODULE_LICENSE("GPL v2");