gpio-pcf857x.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Driver for pcf857x, pca857x, and pca967x I2C GPIO expanders
  4. *
  5. * Copyright (C) 2007 David Brownell
  6. */
  7. #include <linux/gpio/driver.h>
  8. #include <linux/i2c.h>
  9. #include <linux/platform_data/pcf857x.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/irq.h>
  12. #include <linux/irqdomain.h>
  13. #include <linux/kernel.h>
  14. #include <linux/module.h>
  15. #include <linux/of.h>
  16. #include <linux/of_device.h>
  17. #include <linux/slab.h>
  18. #include <linux/spinlock.h>
  19. static const struct i2c_device_id pcf857x_id[] = {
  20. { "pcf8574", 8 },
  21. { "pcf8574a", 8 },
  22. { "pca8574", 8 },
  23. { "pca9670", 8 },
  24. { "pca9672", 8 },
  25. { "pca9674", 8 },
  26. { "pcf8575", 16 },
  27. { "pca8575", 16 },
  28. { "pca9671", 16 },
  29. { "pca9673", 16 },
  30. { "pca9675", 16 },
  31. { "max7328", 8 },
  32. { "max7329", 8 },
  33. { }
  34. };
  35. MODULE_DEVICE_TABLE(i2c, pcf857x_id);
  36. #ifdef CONFIG_OF
  37. static const struct of_device_id pcf857x_of_table[] = {
  38. { .compatible = "nxp,pcf8574" },
  39. { .compatible = "nxp,pcf8574a" },
  40. { .compatible = "nxp,pca8574" },
  41. { .compatible = "nxp,pca9670" },
  42. { .compatible = "nxp,pca9672" },
  43. { .compatible = "nxp,pca9674" },
  44. { .compatible = "nxp,pcf8575" },
  45. { .compatible = "nxp,pca8575" },
  46. { .compatible = "nxp,pca9671" },
  47. { .compatible = "nxp,pca9673" },
  48. { .compatible = "nxp,pca9675" },
  49. { .compatible = "maxim,max7328" },
  50. { .compatible = "maxim,max7329" },
  51. { }
  52. };
  53. MODULE_DEVICE_TABLE(of, pcf857x_of_table);
  54. #endif
  55. /*
  56. * The pcf857x, pca857x, and pca967x chips only expose one read and one
  57. * write register. Writing a "one" bit (to match the reset state) lets
  58. * that pin be used as an input; it's not an open-drain model, but acts
  59. * a bit like one. This is described as "quasi-bidirectional"; read the
  60. * chip documentation for details.
  61. *
  62. * Many other I2C GPIO expander chips (like the pca953x models) have
  63. * more complex register models and more conventional circuitry using
  64. * push/pull drivers. They often use the same 0x20..0x27 addresses as
  65. * pcf857x parts, making the "legacy" I2C driver model problematic.
  66. */
  67. struct pcf857x {
  68. struct gpio_chip chip;
  69. struct irq_chip irqchip;
  70. struct i2c_client *client;
  71. struct mutex lock; /* protect 'out' */
  72. unsigned out; /* software latch */
  73. unsigned status; /* current status */
  74. unsigned irq_enabled; /* enabled irqs */
  75. int (*write)(struct i2c_client *client, unsigned data);
  76. int (*read)(struct i2c_client *client);
  77. };
  78. /*-------------------------------------------------------------------------*/
  79. /* Talk to 8-bit I/O expander */
  80. static int i2c_write_le8(struct i2c_client *client, unsigned data)
  81. {
  82. return i2c_smbus_write_byte(client, data);
  83. }
  84. static int i2c_read_le8(struct i2c_client *client)
  85. {
  86. return (int)i2c_smbus_read_byte(client);
  87. }
  88. /* Talk to 16-bit I/O expander */
  89. static int i2c_write_le16(struct i2c_client *client, unsigned word)
  90. {
  91. u8 buf[2] = { word & 0xff, word >> 8, };
  92. int status;
  93. status = i2c_master_send(client, buf, 2);
  94. return (status < 0) ? status : 0;
  95. }
  96. static int i2c_read_le16(struct i2c_client *client)
  97. {
  98. u8 buf[2];
  99. int status;
  100. status = i2c_master_recv(client, buf, 2);
  101. if (status < 0)
  102. return status;
  103. return (buf[1] << 8) | buf[0];
  104. }
  105. /*-------------------------------------------------------------------------*/
  106. static int pcf857x_input(struct gpio_chip *chip, unsigned offset)
  107. {
  108. struct pcf857x *gpio = gpiochip_get_data(chip);
  109. int status;
  110. mutex_lock(&gpio->lock);
  111. gpio->out |= (1 << offset);
  112. status = gpio->write(gpio->client, gpio->out);
  113. mutex_unlock(&gpio->lock);
  114. return status;
  115. }
  116. static int pcf857x_get(struct gpio_chip *chip, unsigned offset)
  117. {
  118. struct pcf857x *gpio = gpiochip_get_data(chip);
  119. int value;
  120. value = gpio->read(gpio->client);
  121. return (value < 0) ? value : !!(value & (1 << offset));
  122. }
  123. static int pcf857x_output(struct gpio_chip *chip, unsigned offset, int value)
  124. {
  125. struct pcf857x *gpio = gpiochip_get_data(chip);
  126. unsigned bit = 1 << offset;
  127. int status;
  128. mutex_lock(&gpio->lock);
  129. if (value)
  130. gpio->out |= bit;
  131. else
  132. gpio->out &= ~bit;
  133. status = gpio->write(gpio->client, gpio->out);
  134. mutex_unlock(&gpio->lock);
  135. return status;
  136. }
  137. static void pcf857x_set(struct gpio_chip *chip, unsigned offset, int value)
  138. {
  139. pcf857x_output(chip, offset, value);
  140. }
  141. /*-------------------------------------------------------------------------*/
  142. static irqreturn_t pcf857x_irq(int irq, void *data)
  143. {
  144. struct pcf857x *gpio = data;
  145. unsigned long change, i, status;
  146. status = gpio->read(gpio->client);
  147. /*
  148. * call the interrupt handler iff gpio is used as
  149. * interrupt source, just to avoid bad irqs
  150. */
  151. mutex_lock(&gpio->lock);
  152. change = (gpio->status ^ status) & gpio->irq_enabled;
  153. gpio->status = status;
  154. mutex_unlock(&gpio->lock);
  155. for_each_set_bit(i, &change, gpio->chip.ngpio)
  156. handle_nested_irq(irq_find_mapping(gpio->chip.irq.domain, i));
  157. return IRQ_HANDLED;
  158. }
  159. /*
  160. * NOP functions
  161. */
  162. static void noop(struct irq_data *data) { }
  163. static int pcf857x_irq_set_wake(struct irq_data *data, unsigned int on)
  164. {
  165. struct pcf857x *gpio = irq_data_get_irq_chip_data(data);
  166. return irq_set_irq_wake(gpio->client->irq, on);
  167. }
  168. static void pcf857x_irq_enable(struct irq_data *data)
  169. {
  170. struct pcf857x *gpio = irq_data_get_irq_chip_data(data);
  171. gpio->irq_enabled |= (1 << data->hwirq);
  172. }
  173. static void pcf857x_irq_disable(struct irq_data *data)
  174. {
  175. struct pcf857x *gpio = irq_data_get_irq_chip_data(data);
  176. gpio->irq_enabled &= ~(1 << data->hwirq);
  177. }
  178. static void pcf857x_irq_bus_lock(struct irq_data *data)
  179. {
  180. struct pcf857x *gpio = irq_data_get_irq_chip_data(data);
  181. mutex_lock(&gpio->lock);
  182. }
  183. static void pcf857x_irq_bus_sync_unlock(struct irq_data *data)
  184. {
  185. struct pcf857x *gpio = irq_data_get_irq_chip_data(data);
  186. mutex_unlock(&gpio->lock);
  187. }
  188. /*-------------------------------------------------------------------------*/
  189. static int pcf857x_probe(struct i2c_client *client,
  190. const struct i2c_device_id *id)
  191. {
  192. struct pcf857x_platform_data *pdata = dev_get_platdata(&client->dev);
  193. struct device_node *np = client->dev.of_node;
  194. struct pcf857x *gpio;
  195. unsigned int n_latch = 0;
  196. int status;
  197. if (IS_ENABLED(CONFIG_OF) && np)
  198. of_property_read_u32(np, "lines-initial-states", &n_latch);
  199. else if (pdata)
  200. n_latch = pdata->n_latch;
  201. else
  202. dev_dbg(&client->dev, "no platform data\n");
  203. /* Allocate, initialize, and register this gpio_chip. */
  204. gpio = devm_kzalloc(&client->dev, sizeof(*gpio), GFP_KERNEL);
  205. if (!gpio)
  206. return -ENOMEM;
  207. mutex_init(&gpio->lock);
  208. gpio->chip.base = pdata ? pdata->gpio_base : -1;
  209. gpio->chip.can_sleep = true;
  210. gpio->chip.parent = &client->dev;
  211. gpio->chip.owner = THIS_MODULE;
  212. gpio->chip.get = pcf857x_get;
  213. gpio->chip.set = pcf857x_set;
  214. gpio->chip.direction_input = pcf857x_input;
  215. gpio->chip.direction_output = pcf857x_output;
  216. gpio->chip.ngpio = id->driver_data;
  217. /* NOTE: the OnSemi jlc1562b is also largely compatible with
  218. * these parts, notably for output. It has a low-resolution
  219. * DAC instead of pin change IRQs; and its inputs can be the
  220. * result of comparators.
  221. */
  222. /* 8574 addresses are 0x20..0x27; 8574a uses 0x38..0x3f;
  223. * 9670, 9672, 9764, and 9764a use quite a variety.
  224. *
  225. * NOTE: we don't distinguish here between *4 and *4a parts.
  226. */
  227. if (gpio->chip.ngpio == 8) {
  228. gpio->write = i2c_write_le8;
  229. gpio->read = i2c_read_le8;
  230. if (!i2c_check_functionality(client->adapter,
  231. I2C_FUNC_SMBUS_BYTE))
  232. status = -EIO;
  233. /* fail if there's no chip present */
  234. else
  235. status = i2c_smbus_read_byte(client);
  236. /* '75/'75c addresses are 0x20..0x27, just like the '74;
  237. * the '75c doesn't have a current source pulling high.
  238. * 9671, 9673, and 9765 use quite a variety of addresses.
  239. *
  240. * NOTE: we don't distinguish here between '75 and '75c parts.
  241. */
  242. } else if (gpio->chip.ngpio == 16) {
  243. gpio->write = i2c_write_le16;
  244. gpio->read = i2c_read_le16;
  245. if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
  246. status = -EIO;
  247. /* fail if there's no chip present */
  248. else
  249. status = i2c_read_le16(client);
  250. } else {
  251. dev_dbg(&client->dev, "unsupported number of gpios\n");
  252. status = -EINVAL;
  253. }
  254. if (status < 0)
  255. goto fail;
  256. gpio->chip.label = client->name;
  257. gpio->client = client;
  258. i2c_set_clientdata(client, gpio);
  259. /* NOTE: these chips have strange "quasi-bidirectional" I/O pins.
  260. * We can't actually know whether a pin is configured (a) as output
  261. * and driving the signal low, or (b) as input and reporting a low
  262. * value ... without knowing the last value written since the chip
  263. * came out of reset (if any). We can't read the latched output.
  264. *
  265. * In short, the only reliable solution for setting up pin direction
  266. * is to do it explicitly. The setup() method can do that, but it
  267. * may cause transient glitching since it can't know the last value
  268. * written (some pins may need to be driven low).
  269. *
  270. * Using n_latch avoids that trouble. When left initialized to zero,
  271. * our software copy of the "latch" then matches the chip's all-ones
  272. * reset state. Otherwise it flags pins to be driven low.
  273. */
  274. gpio->out = ~n_latch;
  275. gpio->status = gpio->read(gpio->client);
  276. /* Enable irqchip if we have an interrupt */
  277. if (client->irq) {
  278. struct gpio_irq_chip *girq;
  279. gpio->irqchip.name = "pcf857x";
  280. gpio->irqchip.irq_enable = pcf857x_irq_enable;
  281. gpio->irqchip.irq_disable = pcf857x_irq_disable;
  282. gpio->irqchip.irq_ack = noop;
  283. gpio->irqchip.irq_mask = noop;
  284. gpio->irqchip.irq_unmask = noop;
  285. gpio->irqchip.irq_set_wake = pcf857x_irq_set_wake;
  286. gpio->irqchip.irq_bus_lock = pcf857x_irq_bus_lock;
  287. gpio->irqchip.irq_bus_sync_unlock = pcf857x_irq_bus_sync_unlock;
  288. status = devm_request_threaded_irq(&client->dev, client->irq,
  289. NULL, pcf857x_irq, IRQF_ONESHOT |
  290. IRQF_TRIGGER_FALLING | IRQF_SHARED,
  291. dev_name(&client->dev), gpio);
  292. if (status)
  293. goto fail;
  294. girq = &gpio->chip.irq;
  295. girq->chip = &gpio->irqchip;
  296. /* This will let us handle the parent IRQ in the driver */
  297. girq->parent_handler = NULL;
  298. girq->num_parents = 0;
  299. girq->parents = NULL;
  300. girq->default_type = IRQ_TYPE_NONE;
  301. girq->handler = handle_level_irq;
  302. girq->threaded = true;
  303. }
  304. status = devm_gpiochip_add_data(&client->dev, &gpio->chip, gpio);
  305. if (status < 0)
  306. goto fail;
  307. /* Let platform code set up the GPIOs and their users.
  308. * Now is the first time anyone could use them.
  309. */
  310. if (pdata && pdata->setup) {
  311. status = pdata->setup(client,
  312. gpio->chip.base, gpio->chip.ngpio,
  313. pdata->context);
  314. if (status < 0)
  315. dev_warn(&client->dev, "setup --> %d\n", status);
  316. }
  317. dev_info(&client->dev, "probed\n");
  318. return 0;
  319. fail:
  320. dev_dbg(&client->dev, "probe error %d for '%s'\n", status,
  321. client->name);
  322. return status;
  323. }
  324. static int pcf857x_remove(struct i2c_client *client)
  325. {
  326. struct pcf857x_platform_data *pdata = dev_get_platdata(&client->dev);
  327. struct pcf857x *gpio = i2c_get_clientdata(client);
  328. int status = 0;
  329. if (pdata && pdata->teardown) {
  330. status = pdata->teardown(client,
  331. gpio->chip.base, gpio->chip.ngpio,
  332. pdata->context);
  333. if (status < 0) {
  334. dev_err(&client->dev, "%s --> %d\n",
  335. "teardown", status);
  336. return status;
  337. }
  338. }
  339. return status;
  340. }
  341. static void pcf857x_shutdown(struct i2c_client *client)
  342. {
  343. struct pcf857x *gpio = i2c_get_clientdata(client);
  344. /* Drive all the I/O lines high */
  345. gpio->write(gpio->client, BIT(gpio->chip.ngpio) - 1);
  346. }
  347. static struct i2c_driver pcf857x_driver = {
  348. .driver = {
  349. .name = "pcf857x",
  350. .of_match_table = of_match_ptr(pcf857x_of_table),
  351. },
  352. .probe = pcf857x_probe,
  353. .remove = pcf857x_remove,
  354. .shutdown = pcf857x_shutdown,
  355. .id_table = pcf857x_id,
  356. };
  357. static int __init pcf857x_init(void)
  358. {
  359. return i2c_add_driver(&pcf857x_driver);
  360. }
  361. /* register after i2c postcore initcall and before
  362. * subsys initcalls that may rely on these GPIOs
  363. */
  364. subsys_initcall(pcf857x_init);
  365. static void __exit pcf857x_exit(void)
  366. {
  367. i2c_del_driver(&pcf857x_driver);
  368. }
  369. module_exit(pcf857x_exit);
  370. MODULE_LICENSE("GPL");
  371. MODULE_AUTHOR("David Brownell");