gpio-pca953x.c 34 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * PCA953x 4/8/16/24/40 bit I/O ports
  4. *
  5. * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com>
  6. * Copyright (C) 2007 Marvell International Ltd.
  7. *
  8. * Derived from drivers/i2c/chips/pca9539.c
  9. */
  10. #include <linux/acpi.h>
  11. #include <linux/bitmap.h>
  12. #include <linux/gpio/driver.h>
  13. #include <linux/gpio/consumer.h>
  14. #include <linux/i2c.h>
  15. #include <linux/init.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/module.h>
  18. #include <linux/of_platform.h>
  19. #include <linux/platform_data/pca953x.h>
  20. #include <linux/regmap.h>
  21. #include <linux/regulator/consumer.h>
  22. #include <linux/slab.h>
  23. #include <asm/unaligned.h>
  24. #define PCA953X_INPUT 0x00
  25. #define PCA953X_OUTPUT 0x01
  26. #define PCA953X_INVERT 0x02
  27. #define PCA953X_DIRECTION 0x03
  28. #define REG_ADDR_MASK GENMASK(5, 0)
  29. #define REG_ADDR_EXT BIT(6)
  30. #define REG_ADDR_AI BIT(7)
  31. #define PCA957X_IN 0x00
  32. #define PCA957X_INVRT 0x01
  33. #define PCA957X_BKEN 0x02
  34. #define PCA957X_PUPD 0x03
  35. #define PCA957X_CFG 0x04
  36. #define PCA957X_OUT 0x05
  37. #define PCA957X_MSK 0x06
  38. #define PCA957X_INTS 0x07
  39. #define PCAL953X_OUT_STRENGTH 0x20
  40. #define PCAL953X_IN_LATCH 0x22
  41. #define PCAL953X_PULL_EN 0x23
  42. #define PCAL953X_PULL_SEL 0x24
  43. #define PCAL953X_INT_MASK 0x25
  44. #define PCAL953X_INT_STAT 0x26
  45. #define PCAL953X_OUT_CONF 0x27
  46. #define PCAL6524_INT_EDGE 0x28
  47. #define PCAL6524_INT_CLR 0x2a
  48. #define PCAL6524_IN_STATUS 0x2b
  49. #define PCAL6524_OUT_INDCONF 0x2c
  50. #define PCAL6524_DEBOUNCE 0x2d
  51. #define PCA_GPIO_MASK GENMASK(7, 0)
  52. #define PCAL_GPIO_MASK GENMASK(4, 0)
  53. #define PCAL_PINCTRL_MASK GENMASK(6, 5)
  54. #define PCA_INT BIT(8)
  55. #define PCA_PCAL BIT(9)
  56. #define PCA_LATCH_INT (PCA_PCAL | PCA_INT)
  57. #define PCA953X_TYPE BIT(12)
  58. #define PCA957X_TYPE BIT(13)
  59. #define PCA_TYPE_MASK GENMASK(15, 12)
  60. #define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK)
  61. static const struct i2c_device_id pca953x_id[] = {
  62. { "pca6416", 16 | PCA953X_TYPE | PCA_INT, },
  63. { "pca9505", 40 | PCA953X_TYPE | PCA_INT, },
  64. { "pca9534", 8 | PCA953X_TYPE | PCA_INT, },
  65. { "pca9535", 16 | PCA953X_TYPE | PCA_INT, },
  66. { "pca9536", 4 | PCA953X_TYPE, },
  67. { "pca9537", 4 | PCA953X_TYPE | PCA_INT, },
  68. { "pca9538", 8 | PCA953X_TYPE | PCA_INT, },
  69. { "pca9539", 16 | PCA953X_TYPE | PCA_INT, },
  70. { "pca9554", 8 | PCA953X_TYPE | PCA_INT, },
  71. { "pca9555", 16 | PCA953X_TYPE | PCA_INT, },
  72. { "pca9556", 8 | PCA953X_TYPE, },
  73. { "pca9557", 8 | PCA953X_TYPE, },
  74. { "pca9574", 8 | PCA957X_TYPE | PCA_INT, },
  75. { "pca9575", 16 | PCA957X_TYPE | PCA_INT, },
  76. { "pca9698", 40 | PCA953X_TYPE, },
  77. { "pcal6416", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
  78. { "pcal6524", 24 | PCA953X_TYPE | PCA_LATCH_INT, },
  79. { "pcal9535", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
  80. { "pcal9554b", 8 | PCA953X_TYPE | PCA_LATCH_INT, },
  81. { "pcal9555a", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
  82. { "max7310", 8 | PCA953X_TYPE, },
  83. { "max7312", 16 | PCA953X_TYPE | PCA_INT, },
  84. { "max7313", 16 | PCA953X_TYPE | PCA_INT, },
  85. { "max7315", 8 | PCA953X_TYPE | PCA_INT, },
  86. { "max7318", 16 | PCA953X_TYPE | PCA_INT, },
  87. { "pca6107", 8 | PCA953X_TYPE | PCA_INT, },
  88. { "tca6408", 8 | PCA953X_TYPE | PCA_INT, },
  89. { "tca6416", 16 | PCA953X_TYPE | PCA_INT, },
  90. { "tca6424", 24 | PCA953X_TYPE | PCA_INT, },
  91. { "tca9539", 16 | PCA953X_TYPE | PCA_INT, },
  92. { "tca9554", 8 | PCA953X_TYPE | PCA_INT, },
  93. { "xra1202", 8 | PCA953X_TYPE },
  94. { }
  95. };
  96. MODULE_DEVICE_TABLE(i2c, pca953x_id);
  97. #ifdef CONFIG_GPIO_PCA953X_IRQ
  98. #include <linux/dmi.h>
  99. static const struct acpi_gpio_params pca953x_irq_gpios = { 0, 0, true };
  100. static const struct acpi_gpio_mapping pca953x_acpi_irq_gpios[] = {
  101. { "irq-gpios", &pca953x_irq_gpios, 1, ACPI_GPIO_QUIRK_ABSOLUTE_NUMBER },
  102. { }
  103. };
  104. static int pca953x_acpi_get_irq(struct device *dev)
  105. {
  106. int ret;
  107. ret = devm_acpi_dev_add_driver_gpios(dev, pca953x_acpi_irq_gpios);
  108. if (ret)
  109. dev_warn(dev, "can't add GPIO ACPI mapping\n");
  110. ret = acpi_dev_gpio_irq_get_by(ACPI_COMPANION(dev), "irq-gpios", 0);
  111. if (ret < 0)
  112. return ret;
  113. dev_info(dev, "ACPI interrupt quirk (IRQ %d)\n", ret);
  114. return ret;
  115. }
  116. static const struct dmi_system_id pca953x_dmi_acpi_irq_info[] = {
  117. {
  118. /*
  119. * On Intel Galileo Gen 2 board the IRQ pin of one of
  120. * the I²C GPIO expanders, which has GpioInt() resource,
  121. * is provided as an absolute number instead of being
  122. * relative. Since first controller (gpio-sch.c) and
  123. * second (gpio-dwapb.c) are at the fixed bases, we may
  124. * safely refer to the number in the global space to get
  125. * an IRQ out of it.
  126. */
  127. .matches = {
  128. DMI_EXACT_MATCH(DMI_BOARD_NAME, "GalileoGen2"),
  129. },
  130. },
  131. {}
  132. };
  133. #endif
  134. static const struct acpi_device_id pca953x_acpi_ids[] = {
  135. { "INT3491", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
  136. { }
  137. };
  138. MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids);
  139. #define MAX_BANK 5
  140. #define BANK_SZ 8
  141. #define MAX_LINE (MAX_BANK * BANK_SZ)
  142. #define NBANK(chip) DIV_ROUND_UP(chip->gpio_chip.ngpio, BANK_SZ)
  143. struct pca953x_reg_config {
  144. int direction;
  145. int output;
  146. int input;
  147. int invert;
  148. };
  149. static const struct pca953x_reg_config pca953x_regs = {
  150. .direction = PCA953X_DIRECTION,
  151. .output = PCA953X_OUTPUT,
  152. .input = PCA953X_INPUT,
  153. .invert = PCA953X_INVERT,
  154. };
  155. static const struct pca953x_reg_config pca957x_regs = {
  156. .direction = PCA957X_CFG,
  157. .output = PCA957X_OUT,
  158. .input = PCA957X_IN,
  159. .invert = PCA957X_INVRT,
  160. };
  161. struct pca953x_chip {
  162. unsigned gpio_start;
  163. struct mutex i2c_lock;
  164. struct regmap *regmap;
  165. #ifdef CONFIG_GPIO_PCA953X_IRQ
  166. struct mutex irq_lock;
  167. DECLARE_BITMAP(irq_mask, MAX_LINE);
  168. DECLARE_BITMAP(irq_stat, MAX_LINE);
  169. DECLARE_BITMAP(irq_trig_raise, MAX_LINE);
  170. DECLARE_BITMAP(irq_trig_fall, MAX_LINE);
  171. struct irq_chip irq_chip;
  172. #endif
  173. atomic_t wakeup_path;
  174. struct i2c_client *client;
  175. struct gpio_chip gpio_chip;
  176. const char *const *names;
  177. unsigned long driver_data;
  178. struct regulator *regulator;
  179. const struct pca953x_reg_config *regs;
  180. };
  181. static int pca953x_bank_shift(struct pca953x_chip *chip)
  182. {
  183. return fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
  184. }
  185. #define PCA953x_BANK_INPUT BIT(0)
  186. #define PCA953x_BANK_OUTPUT BIT(1)
  187. #define PCA953x_BANK_POLARITY BIT(2)
  188. #define PCA953x_BANK_CONFIG BIT(3)
  189. #define PCA957x_BANK_INPUT BIT(0)
  190. #define PCA957x_BANK_POLARITY BIT(1)
  191. #define PCA957x_BANK_BUSHOLD BIT(2)
  192. #define PCA957x_BANK_CONFIG BIT(4)
  193. #define PCA957x_BANK_OUTPUT BIT(5)
  194. #define PCAL9xxx_BANK_IN_LATCH BIT(8 + 2)
  195. #define PCAL9xxx_BANK_PULL_EN BIT(8 + 3)
  196. #define PCAL9xxx_BANK_PULL_SEL BIT(8 + 4)
  197. #define PCAL9xxx_BANK_IRQ_MASK BIT(8 + 5)
  198. #define PCAL9xxx_BANK_IRQ_STAT BIT(8 + 6)
  199. /*
  200. * We care about the following registers:
  201. * - Standard set, below 0x40, each port can be replicated up to 8 times
  202. * - PCA953x standard
  203. * Input port 0x00 + 0 * bank_size R
  204. * Output port 0x00 + 1 * bank_size RW
  205. * Polarity Inversion port 0x00 + 2 * bank_size RW
  206. * Configuration port 0x00 + 3 * bank_size RW
  207. * - PCA957x with mixed up registers
  208. * Input port 0x00 + 0 * bank_size R
  209. * Polarity Inversion port 0x00 + 1 * bank_size RW
  210. * Bus hold port 0x00 + 2 * bank_size RW
  211. * Configuration port 0x00 + 4 * bank_size RW
  212. * Output port 0x00 + 5 * bank_size RW
  213. *
  214. * - Extended set, above 0x40, often chip specific.
  215. * - PCAL6524/PCAL9555A with custom PCAL IRQ handling:
  216. * Input latch register 0x40 + 2 * bank_size RW
  217. * Pull-up/pull-down enable reg 0x40 + 3 * bank_size RW
  218. * Pull-up/pull-down select reg 0x40 + 4 * bank_size RW
  219. * Interrupt mask register 0x40 + 5 * bank_size RW
  220. * Interrupt status register 0x40 + 6 * bank_size R
  221. *
  222. * - Registers with bit 0x80 set, the AI bit
  223. * The bit is cleared and the registers fall into one of the
  224. * categories above.
  225. */
  226. static bool pca953x_check_register(struct pca953x_chip *chip, unsigned int reg,
  227. u32 checkbank)
  228. {
  229. int bank_shift = pca953x_bank_shift(chip);
  230. int bank = (reg & REG_ADDR_MASK) >> bank_shift;
  231. int offset = reg & (BIT(bank_shift) - 1);
  232. /* Special PCAL extended register check. */
  233. if (reg & REG_ADDR_EXT) {
  234. if (!(chip->driver_data & PCA_PCAL))
  235. return false;
  236. bank += 8;
  237. }
  238. /* Register is not in the matching bank. */
  239. if (!(BIT(bank) & checkbank))
  240. return false;
  241. /* Register is not within allowed range of bank. */
  242. if (offset >= NBANK(chip))
  243. return false;
  244. return true;
  245. }
  246. static bool pca953x_readable_register(struct device *dev, unsigned int reg)
  247. {
  248. struct pca953x_chip *chip = dev_get_drvdata(dev);
  249. u32 bank;
  250. if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) {
  251. bank = PCA953x_BANK_INPUT | PCA953x_BANK_OUTPUT |
  252. PCA953x_BANK_POLARITY | PCA953x_BANK_CONFIG;
  253. } else {
  254. bank = PCA957x_BANK_INPUT | PCA957x_BANK_OUTPUT |
  255. PCA957x_BANK_POLARITY | PCA957x_BANK_CONFIG |
  256. PCA957x_BANK_BUSHOLD;
  257. }
  258. if (chip->driver_data & PCA_PCAL) {
  259. bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN |
  260. PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK |
  261. PCAL9xxx_BANK_IRQ_STAT;
  262. }
  263. return pca953x_check_register(chip, reg, bank);
  264. }
  265. static bool pca953x_writeable_register(struct device *dev, unsigned int reg)
  266. {
  267. struct pca953x_chip *chip = dev_get_drvdata(dev);
  268. u32 bank;
  269. if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) {
  270. bank = PCA953x_BANK_OUTPUT | PCA953x_BANK_POLARITY |
  271. PCA953x_BANK_CONFIG;
  272. } else {
  273. bank = PCA957x_BANK_OUTPUT | PCA957x_BANK_POLARITY |
  274. PCA957x_BANK_CONFIG | PCA957x_BANK_BUSHOLD;
  275. }
  276. if (chip->driver_data & PCA_PCAL)
  277. bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN |
  278. PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK;
  279. return pca953x_check_register(chip, reg, bank);
  280. }
  281. static bool pca953x_volatile_register(struct device *dev, unsigned int reg)
  282. {
  283. struct pca953x_chip *chip = dev_get_drvdata(dev);
  284. u32 bank;
  285. if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE)
  286. bank = PCA953x_BANK_INPUT;
  287. else
  288. bank = PCA957x_BANK_INPUT;
  289. if (chip->driver_data & PCA_PCAL)
  290. bank |= PCAL9xxx_BANK_IRQ_STAT;
  291. return pca953x_check_register(chip, reg, bank);
  292. }
  293. static const struct regmap_config pca953x_i2c_regmap = {
  294. .reg_bits = 8,
  295. .val_bits = 8,
  296. .readable_reg = pca953x_readable_register,
  297. .writeable_reg = pca953x_writeable_register,
  298. .volatile_reg = pca953x_volatile_register,
  299. .disable_locking = true,
  300. .cache_type = REGCACHE_RBTREE,
  301. .max_register = 0x7f,
  302. };
  303. static const struct regmap_config pca953x_ai_i2c_regmap = {
  304. .reg_bits = 8,
  305. .val_bits = 8,
  306. .read_flag_mask = REG_ADDR_AI,
  307. .write_flag_mask = REG_ADDR_AI,
  308. .readable_reg = pca953x_readable_register,
  309. .writeable_reg = pca953x_writeable_register,
  310. .volatile_reg = pca953x_volatile_register,
  311. .disable_locking = true,
  312. .cache_type = REGCACHE_RBTREE,
  313. .max_register = 0x7f,
  314. };
  315. static u8 pca953x_recalc_addr(struct pca953x_chip *chip, int reg, int off)
  316. {
  317. int bank_shift = pca953x_bank_shift(chip);
  318. int addr = (reg & PCAL_GPIO_MASK) << bank_shift;
  319. int pinctrl = (reg & PCAL_PINCTRL_MASK) << 1;
  320. u8 regaddr = pinctrl | addr | (off / BANK_SZ);
  321. return regaddr;
  322. }
  323. static int pca953x_write_regs(struct pca953x_chip *chip, int reg, unsigned long *val)
  324. {
  325. u8 regaddr = pca953x_recalc_addr(chip, reg, 0);
  326. u8 value[MAX_BANK];
  327. int i, ret;
  328. for (i = 0; i < NBANK(chip); i++)
  329. value[i] = bitmap_get_value8(val, i * BANK_SZ);
  330. ret = regmap_bulk_write(chip->regmap, regaddr, value, NBANK(chip));
  331. if (ret < 0) {
  332. dev_err(&chip->client->dev, "failed writing register\n");
  333. return ret;
  334. }
  335. return 0;
  336. }
  337. static int pca953x_read_regs(struct pca953x_chip *chip, int reg, unsigned long *val)
  338. {
  339. u8 regaddr = pca953x_recalc_addr(chip, reg, 0);
  340. u8 value[MAX_BANK];
  341. int i, ret;
  342. ret = regmap_bulk_read(chip->regmap, regaddr, value, NBANK(chip));
  343. if (ret < 0) {
  344. dev_err(&chip->client->dev, "failed reading register\n");
  345. return ret;
  346. }
  347. for (i = 0; i < NBANK(chip); i++)
  348. bitmap_set_value8(val, value[i], i * BANK_SZ);
  349. return 0;
  350. }
  351. static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off)
  352. {
  353. struct pca953x_chip *chip = gpiochip_get_data(gc);
  354. u8 dirreg = pca953x_recalc_addr(chip, chip->regs->direction, off);
  355. u8 bit = BIT(off % BANK_SZ);
  356. int ret;
  357. mutex_lock(&chip->i2c_lock);
  358. ret = regmap_write_bits(chip->regmap, dirreg, bit, bit);
  359. mutex_unlock(&chip->i2c_lock);
  360. return ret;
  361. }
  362. static int pca953x_gpio_direction_output(struct gpio_chip *gc,
  363. unsigned off, int val)
  364. {
  365. struct pca953x_chip *chip = gpiochip_get_data(gc);
  366. u8 dirreg = pca953x_recalc_addr(chip, chip->regs->direction, off);
  367. u8 outreg = pca953x_recalc_addr(chip, chip->regs->output, off);
  368. u8 bit = BIT(off % BANK_SZ);
  369. int ret;
  370. mutex_lock(&chip->i2c_lock);
  371. /* set output level */
  372. ret = regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0);
  373. if (ret)
  374. goto exit;
  375. /* then direction */
  376. ret = regmap_write_bits(chip->regmap, dirreg, bit, 0);
  377. exit:
  378. mutex_unlock(&chip->i2c_lock);
  379. return ret;
  380. }
  381. static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off)
  382. {
  383. struct pca953x_chip *chip = gpiochip_get_data(gc);
  384. u8 inreg = pca953x_recalc_addr(chip, chip->regs->input, off);
  385. u8 bit = BIT(off % BANK_SZ);
  386. u32 reg_val;
  387. int ret;
  388. mutex_lock(&chip->i2c_lock);
  389. ret = regmap_read(chip->regmap, inreg, &reg_val);
  390. mutex_unlock(&chip->i2c_lock);
  391. if (ret < 0)
  392. return ret;
  393. return !!(reg_val & bit);
  394. }
  395. static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val)
  396. {
  397. struct pca953x_chip *chip = gpiochip_get_data(gc);
  398. u8 outreg = pca953x_recalc_addr(chip, chip->regs->output, off);
  399. u8 bit = BIT(off % BANK_SZ);
  400. mutex_lock(&chip->i2c_lock);
  401. regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0);
  402. mutex_unlock(&chip->i2c_lock);
  403. }
  404. static int pca953x_gpio_get_direction(struct gpio_chip *gc, unsigned off)
  405. {
  406. struct pca953x_chip *chip = gpiochip_get_data(gc);
  407. u8 dirreg = pca953x_recalc_addr(chip, chip->regs->direction, off);
  408. u8 bit = BIT(off % BANK_SZ);
  409. u32 reg_val;
  410. int ret;
  411. mutex_lock(&chip->i2c_lock);
  412. ret = regmap_read(chip->regmap, dirreg, &reg_val);
  413. mutex_unlock(&chip->i2c_lock);
  414. if (ret < 0)
  415. return ret;
  416. if (reg_val & bit)
  417. return GPIO_LINE_DIRECTION_IN;
  418. return GPIO_LINE_DIRECTION_OUT;
  419. }
  420. static int pca953x_gpio_get_multiple(struct gpio_chip *gc,
  421. unsigned long *mask, unsigned long *bits)
  422. {
  423. struct pca953x_chip *chip = gpiochip_get_data(gc);
  424. DECLARE_BITMAP(reg_val, MAX_LINE);
  425. int ret;
  426. mutex_lock(&chip->i2c_lock);
  427. ret = pca953x_read_regs(chip, chip->regs->input, reg_val);
  428. mutex_unlock(&chip->i2c_lock);
  429. if (ret)
  430. return ret;
  431. bitmap_replace(bits, bits, reg_val, mask, gc->ngpio);
  432. return 0;
  433. }
  434. static void pca953x_gpio_set_multiple(struct gpio_chip *gc,
  435. unsigned long *mask, unsigned long *bits)
  436. {
  437. struct pca953x_chip *chip = gpiochip_get_data(gc);
  438. DECLARE_BITMAP(reg_val, MAX_LINE);
  439. int ret;
  440. mutex_lock(&chip->i2c_lock);
  441. ret = pca953x_read_regs(chip, chip->regs->output, reg_val);
  442. if (ret)
  443. goto exit;
  444. bitmap_replace(reg_val, reg_val, bits, mask, gc->ngpio);
  445. pca953x_write_regs(chip, chip->regs->output, reg_val);
  446. exit:
  447. mutex_unlock(&chip->i2c_lock);
  448. }
  449. static int pca953x_gpio_set_pull_up_down(struct pca953x_chip *chip,
  450. unsigned int offset,
  451. unsigned long config)
  452. {
  453. u8 pull_en_reg = pca953x_recalc_addr(chip, PCAL953X_PULL_EN, offset);
  454. u8 pull_sel_reg = pca953x_recalc_addr(chip, PCAL953X_PULL_SEL, offset);
  455. u8 bit = BIT(offset % BANK_SZ);
  456. int ret;
  457. /*
  458. * pull-up/pull-down configuration requires PCAL extended
  459. * registers
  460. */
  461. if (!(chip->driver_data & PCA_PCAL))
  462. return -ENOTSUPP;
  463. mutex_lock(&chip->i2c_lock);
  464. /* Configure pull-up/pull-down */
  465. if (config == PIN_CONFIG_BIAS_PULL_UP)
  466. ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, bit);
  467. else if (config == PIN_CONFIG_BIAS_PULL_DOWN)
  468. ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, 0);
  469. else
  470. ret = 0;
  471. if (ret)
  472. goto exit;
  473. /* Disable/Enable pull-up/pull-down */
  474. if (config == PIN_CONFIG_BIAS_DISABLE)
  475. ret = regmap_write_bits(chip->regmap, pull_en_reg, bit, 0);
  476. else
  477. ret = regmap_write_bits(chip->regmap, pull_en_reg, bit, bit);
  478. exit:
  479. mutex_unlock(&chip->i2c_lock);
  480. return ret;
  481. }
  482. static int pca953x_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
  483. unsigned long config)
  484. {
  485. struct pca953x_chip *chip = gpiochip_get_data(gc);
  486. switch (pinconf_to_config_param(config)) {
  487. case PIN_CONFIG_BIAS_PULL_UP:
  488. case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
  489. case PIN_CONFIG_BIAS_PULL_DOWN:
  490. case PIN_CONFIG_BIAS_DISABLE:
  491. return pca953x_gpio_set_pull_up_down(chip, offset, config);
  492. default:
  493. return -ENOTSUPP;
  494. }
  495. }
  496. static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios)
  497. {
  498. struct gpio_chip *gc;
  499. gc = &chip->gpio_chip;
  500. gc->direction_input = pca953x_gpio_direction_input;
  501. gc->direction_output = pca953x_gpio_direction_output;
  502. gc->get = pca953x_gpio_get_value;
  503. gc->set = pca953x_gpio_set_value;
  504. gc->get_direction = pca953x_gpio_get_direction;
  505. gc->get_multiple = pca953x_gpio_get_multiple;
  506. gc->set_multiple = pca953x_gpio_set_multiple;
  507. gc->set_config = pca953x_gpio_set_config;
  508. gc->can_sleep = true;
  509. gc->base = chip->gpio_start;
  510. gc->ngpio = gpios;
  511. gc->label = dev_name(&chip->client->dev);
  512. gc->parent = &chip->client->dev;
  513. gc->owner = THIS_MODULE;
  514. gc->names = chip->names;
  515. }
  516. #ifdef CONFIG_GPIO_PCA953X_IRQ
  517. static void pca953x_irq_mask(struct irq_data *d)
  518. {
  519. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  520. struct pca953x_chip *chip = gpiochip_get_data(gc);
  521. irq_hw_number_t hwirq = irqd_to_hwirq(d);
  522. clear_bit(hwirq, chip->irq_mask);
  523. }
  524. static void pca953x_irq_unmask(struct irq_data *d)
  525. {
  526. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  527. struct pca953x_chip *chip = gpiochip_get_data(gc);
  528. irq_hw_number_t hwirq = irqd_to_hwirq(d);
  529. set_bit(hwirq, chip->irq_mask);
  530. }
  531. static int pca953x_irq_set_wake(struct irq_data *d, unsigned int on)
  532. {
  533. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  534. struct pca953x_chip *chip = gpiochip_get_data(gc);
  535. if (on)
  536. atomic_inc(&chip->wakeup_path);
  537. else
  538. atomic_dec(&chip->wakeup_path);
  539. return irq_set_irq_wake(chip->client->irq, on);
  540. }
  541. static void pca953x_irq_bus_lock(struct irq_data *d)
  542. {
  543. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  544. struct pca953x_chip *chip = gpiochip_get_data(gc);
  545. mutex_lock(&chip->irq_lock);
  546. }
  547. static void pca953x_irq_bus_sync_unlock(struct irq_data *d)
  548. {
  549. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  550. struct pca953x_chip *chip = gpiochip_get_data(gc);
  551. DECLARE_BITMAP(irq_mask, MAX_LINE);
  552. DECLARE_BITMAP(reg_direction, MAX_LINE);
  553. int level;
  554. if (chip->driver_data & PCA_PCAL) {
  555. /* Enable latch on interrupt-enabled inputs */
  556. pca953x_write_regs(chip, PCAL953X_IN_LATCH, chip->irq_mask);
  557. bitmap_complement(irq_mask, chip->irq_mask, gc->ngpio);
  558. /* Unmask enabled interrupts */
  559. pca953x_write_regs(chip, PCAL953X_INT_MASK, irq_mask);
  560. }
  561. /* Switch direction to input if needed */
  562. pca953x_read_regs(chip, chip->regs->direction, reg_direction);
  563. bitmap_or(irq_mask, chip->irq_trig_fall, chip->irq_trig_raise, gc->ngpio);
  564. bitmap_complement(reg_direction, reg_direction, gc->ngpio);
  565. bitmap_and(irq_mask, irq_mask, reg_direction, gc->ngpio);
  566. /* Look for any newly setup interrupt */
  567. for_each_set_bit(level, irq_mask, gc->ngpio)
  568. pca953x_gpio_direction_input(&chip->gpio_chip, level);
  569. mutex_unlock(&chip->irq_lock);
  570. }
  571. static int pca953x_irq_set_type(struct irq_data *d, unsigned int type)
  572. {
  573. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  574. struct pca953x_chip *chip = gpiochip_get_data(gc);
  575. irq_hw_number_t hwirq = irqd_to_hwirq(d);
  576. if (!(type & IRQ_TYPE_EDGE_BOTH)) {
  577. dev_err(&chip->client->dev, "irq %d: unsupported type %d\n",
  578. d->irq, type);
  579. return -EINVAL;
  580. }
  581. assign_bit(hwirq, chip->irq_trig_fall, type & IRQ_TYPE_EDGE_FALLING);
  582. assign_bit(hwirq, chip->irq_trig_raise, type & IRQ_TYPE_EDGE_RISING);
  583. return 0;
  584. }
  585. static void pca953x_irq_shutdown(struct irq_data *d)
  586. {
  587. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  588. struct pca953x_chip *chip = gpiochip_get_data(gc);
  589. irq_hw_number_t hwirq = irqd_to_hwirq(d);
  590. clear_bit(hwirq, chip->irq_trig_raise);
  591. clear_bit(hwirq, chip->irq_trig_fall);
  592. }
  593. static bool pca953x_irq_pending(struct pca953x_chip *chip, unsigned long *pending)
  594. {
  595. struct gpio_chip *gc = &chip->gpio_chip;
  596. DECLARE_BITMAP(reg_direction, MAX_LINE);
  597. DECLARE_BITMAP(old_stat, MAX_LINE);
  598. DECLARE_BITMAP(cur_stat, MAX_LINE);
  599. DECLARE_BITMAP(new_stat, MAX_LINE);
  600. DECLARE_BITMAP(trigger, MAX_LINE);
  601. int ret;
  602. if (chip->driver_data & PCA_PCAL) {
  603. /* Read the current interrupt status from the device */
  604. ret = pca953x_read_regs(chip, PCAL953X_INT_STAT, trigger);
  605. if (ret)
  606. return false;
  607. /* Check latched inputs and clear interrupt status */
  608. ret = pca953x_read_regs(chip, chip->regs->input, cur_stat);
  609. if (ret)
  610. return false;
  611. /* Apply filter for rising/falling edge selection */
  612. bitmap_replace(new_stat, chip->irq_trig_fall, chip->irq_trig_raise, cur_stat, gc->ngpio);
  613. bitmap_and(pending, new_stat, trigger, gc->ngpio);
  614. return !bitmap_empty(pending, gc->ngpio);
  615. }
  616. ret = pca953x_read_regs(chip, chip->regs->input, cur_stat);
  617. if (ret)
  618. return false;
  619. /* Remove output pins from the equation */
  620. pca953x_read_regs(chip, chip->regs->direction, reg_direction);
  621. bitmap_copy(old_stat, chip->irq_stat, gc->ngpio);
  622. bitmap_and(new_stat, cur_stat, reg_direction, gc->ngpio);
  623. bitmap_xor(cur_stat, new_stat, old_stat, gc->ngpio);
  624. bitmap_and(trigger, cur_stat, chip->irq_mask, gc->ngpio);
  625. if (bitmap_empty(trigger, gc->ngpio))
  626. return false;
  627. bitmap_copy(chip->irq_stat, new_stat, gc->ngpio);
  628. bitmap_and(cur_stat, chip->irq_trig_fall, old_stat, gc->ngpio);
  629. bitmap_and(old_stat, chip->irq_trig_raise, new_stat, gc->ngpio);
  630. bitmap_or(new_stat, old_stat, cur_stat, gc->ngpio);
  631. bitmap_and(pending, new_stat, trigger, gc->ngpio);
  632. return !bitmap_empty(pending, gc->ngpio);
  633. }
  634. static irqreturn_t pca953x_irq_handler(int irq, void *devid)
  635. {
  636. struct pca953x_chip *chip = devid;
  637. struct gpio_chip *gc = &chip->gpio_chip;
  638. DECLARE_BITMAP(pending, MAX_LINE);
  639. int level;
  640. bool ret;
  641. bitmap_zero(pending, MAX_LINE);
  642. mutex_lock(&chip->i2c_lock);
  643. ret = pca953x_irq_pending(chip, pending);
  644. mutex_unlock(&chip->i2c_lock);
  645. if (ret) {
  646. ret = 0;
  647. for_each_set_bit(level, pending, gc->ngpio) {
  648. int nested_irq = irq_find_mapping(gc->irq.domain, level);
  649. if (unlikely(nested_irq <= 0)) {
  650. dev_warn_ratelimited(gc->parent, "unmapped interrupt %d\n", level);
  651. continue;
  652. }
  653. handle_nested_irq(nested_irq);
  654. ret = 1;
  655. }
  656. }
  657. return IRQ_RETVAL(ret);
  658. }
  659. static int pca953x_irq_setup(struct pca953x_chip *chip, int irq_base)
  660. {
  661. struct i2c_client *client = chip->client;
  662. struct irq_chip *irq_chip = &chip->irq_chip;
  663. DECLARE_BITMAP(reg_direction, MAX_LINE);
  664. DECLARE_BITMAP(irq_stat, MAX_LINE);
  665. struct gpio_irq_chip *girq;
  666. int ret;
  667. if (dmi_first_match(pca953x_dmi_acpi_irq_info)) {
  668. ret = pca953x_acpi_get_irq(&client->dev);
  669. if (ret > 0)
  670. client->irq = ret;
  671. }
  672. if (!client->irq)
  673. return 0;
  674. if (irq_base == -1)
  675. return 0;
  676. if (!(chip->driver_data & PCA_INT))
  677. return 0;
  678. ret = pca953x_read_regs(chip, chip->regs->input, irq_stat);
  679. if (ret)
  680. return ret;
  681. /*
  682. * There is no way to know which GPIO line generated the
  683. * interrupt. We have to rely on the previous read for
  684. * this purpose.
  685. */
  686. pca953x_read_regs(chip, chip->regs->direction, reg_direction);
  687. bitmap_and(chip->irq_stat, irq_stat, reg_direction, chip->gpio_chip.ngpio);
  688. mutex_init(&chip->irq_lock);
  689. irq_chip->name = dev_name(&client->dev);
  690. irq_chip->irq_mask = pca953x_irq_mask;
  691. irq_chip->irq_unmask = pca953x_irq_unmask;
  692. irq_chip->irq_set_wake = pca953x_irq_set_wake;
  693. irq_chip->irq_bus_lock = pca953x_irq_bus_lock;
  694. irq_chip->irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock;
  695. irq_chip->irq_set_type = pca953x_irq_set_type;
  696. irq_chip->irq_shutdown = pca953x_irq_shutdown;
  697. girq = &chip->gpio_chip.irq;
  698. girq->chip = irq_chip;
  699. /* This will let us handle the parent IRQ in the driver */
  700. girq->parent_handler = NULL;
  701. girq->num_parents = 0;
  702. girq->parents = NULL;
  703. girq->default_type = IRQ_TYPE_NONE;
  704. girq->handler = handle_simple_irq;
  705. girq->threaded = true;
  706. girq->first = irq_base; /* FIXME: get rid of this */
  707. ret = devm_request_threaded_irq(&client->dev, client->irq,
  708. NULL, pca953x_irq_handler,
  709. IRQF_ONESHOT | IRQF_SHARED,
  710. dev_name(&client->dev), chip);
  711. if (ret) {
  712. dev_err(&client->dev, "failed to request irq %d\n",
  713. client->irq);
  714. return ret;
  715. }
  716. return 0;
  717. }
  718. #else /* CONFIG_GPIO_PCA953X_IRQ */
  719. static int pca953x_irq_setup(struct pca953x_chip *chip,
  720. int irq_base)
  721. {
  722. struct i2c_client *client = chip->client;
  723. if (client->irq && irq_base != -1 && (chip->driver_data & PCA_INT))
  724. dev_warn(&client->dev, "interrupt support not compiled in\n");
  725. return 0;
  726. }
  727. #endif
  728. static int device_pca95xx_init(struct pca953x_chip *chip, u32 invert)
  729. {
  730. DECLARE_BITMAP(val, MAX_LINE);
  731. int ret;
  732. ret = regcache_sync_region(chip->regmap, chip->regs->output,
  733. chip->regs->output + NBANK(chip));
  734. if (ret)
  735. goto out;
  736. ret = regcache_sync_region(chip->regmap, chip->regs->direction,
  737. chip->regs->direction + NBANK(chip));
  738. if (ret)
  739. goto out;
  740. /* set platform specific polarity inversion */
  741. if (invert)
  742. bitmap_fill(val, MAX_LINE);
  743. else
  744. bitmap_zero(val, MAX_LINE);
  745. ret = pca953x_write_regs(chip, chip->regs->invert, val);
  746. out:
  747. return ret;
  748. }
  749. static int device_pca957x_init(struct pca953x_chip *chip, u32 invert)
  750. {
  751. DECLARE_BITMAP(val, MAX_LINE);
  752. unsigned int i;
  753. int ret;
  754. ret = device_pca95xx_init(chip, invert);
  755. if (ret)
  756. goto out;
  757. /* To enable register 6, 7 to control pull up and pull down */
  758. for (i = 0; i < NBANK(chip); i++)
  759. bitmap_set_value8(val, 0x02, i * BANK_SZ);
  760. ret = pca953x_write_regs(chip, PCA957X_BKEN, val);
  761. if (ret)
  762. goto out;
  763. return 0;
  764. out:
  765. return ret;
  766. }
  767. static int pca953x_probe(struct i2c_client *client,
  768. const struct i2c_device_id *i2c_id)
  769. {
  770. struct pca953x_platform_data *pdata;
  771. struct pca953x_chip *chip;
  772. int irq_base = 0;
  773. int ret;
  774. u32 invert = 0;
  775. struct regulator *reg;
  776. const struct regmap_config *regmap_config;
  777. chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
  778. if (chip == NULL)
  779. return -ENOMEM;
  780. pdata = dev_get_platdata(&client->dev);
  781. if (pdata) {
  782. irq_base = pdata->irq_base;
  783. chip->gpio_start = pdata->gpio_base;
  784. invert = pdata->invert;
  785. chip->names = pdata->names;
  786. } else {
  787. struct gpio_desc *reset_gpio;
  788. chip->gpio_start = -1;
  789. irq_base = 0;
  790. /*
  791. * See if we need to de-assert a reset pin.
  792. *
  793. * There is no known ACPI-enabled platforms that are
  794. * using "reset" GPIO. Otherwise any of those platform
  795. * must use _DSD method with corresponding property.
  796. */
  797. reset_gpio = devm_gpiod_get_optional(&client->dev, "reset",
  798. GPIOD_OUT_LOW);
  799. if (IS_ERR(reset_gpio))
  800. return PTR_ERR(reset_gpio);
  801. }
  802. chip->client = client;
  803. reg = devm_regulator_get(&client->dev, "vcc");
  804. if (IS_ERR(reg))
  805. return dev_err_probe(&client->dev, PTR_ERR(reg), "reg get err\n");
  806. ret = regulator_enable(reg);
  807. if (ret) {
  808. dev_err(&client->dev, "reg en err: %d\n", ret);
  809. return ret;
  810. }
  811. chip->regulator = reg;
  812. if (i2c_id) {
  813. chip->driver_data = i2c_id->driver_data;
  814. } else {
  815. const void *match;
  816. match = device_get_match_data(&client->dev);
  817. if (!match) {
  818. ret = -ENODEV;
  819. goto err_exit;
  820. }
  821. chip->driver_data = (uintptr_t)match;
  822. }
  823. i2c_set_clientdata(client, chip);
  824. pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK);
  825. if (NBANK(chip) > 2 || PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) {
  826. dev_info(&client->dev, "using AI\n");
  827. regmap_config = &pca953x_ai_i2c_regmap;
  828. } else {
  829. dev_info(&client->dev, "using no AI\n");
  830. regmap_config = &pca953x_i2c_regmap;
  831. }
  832. chip->regmap = devm_regmap_init_i2c(client, regmap_config);
  833. if (IS_ERR(chip->regmap)) {
  834. ret = PTR_ERR(chip->regmap);
  835. goto err_exit;
  836. }
  837. regcache_mark_dirty(chip->regmap);
  838. mutex_init(&chip->i2c_lock);
  839. /*
  840. * In case we have an i2c-mux controlled by a GPIO provided by an
  841. * expander using the same driver higher on the device tree, read the
  842. * i2c adapter nesting depth and use the retrieved value as lockdep
  843. * subclass for chip->i2c_lock.
  844. *
  845. * REVISIT: This solution is not complete. It protects us from lockdep
  846. * false positives when the expander controlling the i2c-mux is on
  847. * a different level on the device tree, but not when it's on the same
  848. * level on a different branch (in which case the subclass number
  849. * would be the same).
  850. *
  851. * TODO: Once a correct solution is developed, a similar fix should be
  852. * applied to all other i2c-controlled GPIO expanders (and potentially
  853. * regmap-i2c).
  854. */
  855. lockdep_set_subclass(&chip->i2c_lock,
  856. i2c_adapter_depth(client->adapter));
  857. /* initialize cached registers from their original values.
  858. * we can't share this chip with another i2c master.
  859. */
  860. if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) {
  861. chip->regs = &pca953x_regs;
  862. ret = device_pca95xx_init(chip, invert);
  863. } else {
  864. chip->regs = &pca957x_regs;
  865. ret = device_pca957x_init(chip, invert);
  866. }
  867. if (ret)
  868. goto err_exit;
  869. ret = pca953x_irq_setup(chip, irq_base);
  870. if (ret)
  871. goto err_exit;
  872. ret = devm_gpiochip_add_data(&client->dev, &chip->gpio_chip, chip);
  873. if (ret)
  874. goto err_exit;
  875. if (pdata && pdata->setup) {
  876. ret = pdata->setup(client, chip->gpio_chip.base,
  877. chip->gpio_chip.ngpio, pdata->context);
  878. if (ret < 0)
  879. dev_warn(&client->dev, "setup failed, %d\n", ret);
  880. }
  881. return 0;
  882. err_exit:
  883. regulator_disable(chip->regulator);
  884. return ret;
  885. }
  886. static int pca953x_remove(struct i2c_client *client)
  887. {
  888. struct pca953x_platform_data *pdata = dev_get_platdata(&client->dev);
  889. struct pca953x_chip *chip = i2c_get_clientdata(client);
  890. int ret;
  891. if (pdata && pdata->teardown) {
  892. ret = pdata->teardown(client, chip->gpio_chip.base,
  893. chip->gpio_chip.ngpio, pdata->context);
  894. if (ret < 0)
  895. dev_err(&client->dev, "teardown failed, %d\n", ret);
  896. } else {
  897. ret = 0;
  898. }
  899. regulator_disable(chip->regulator);
  900. return ret;
  901. }
  902. #ifdef CONFIG_PM_SLEEP
  903. static int pca953x_regcache_sync(struct device *dev)
  904. {
  905. struct pca953x_chip *chip = dev_get_drvdata(dev);
  906. int ret;
  907. /*
  908. * The ordering between direction and output is important,
  909. * sync these registers first and only then sync the rest.
  910. */
  911. ret = regcache_sync_region(chip->regmap, chip->regs->direction,
  912. chip->regs->direction + NBANK(chip));
  913. if (ret) {
  914. dev_err(dev, "Failed to sync GPIO dir registers: %d\n", ret);
  915. return ret;
  916. }
  917. ret = regcache_sync_region(chip->regmap, chip->regs->output,
  918. chip->regs->output + NBANK(chip));
  919. if (ret) {
  920. dev_err(dev, "Failed to sync GPIO out registers: %d\n", ret);
  921. return ret;
  922. }
  923. #ifdef CONFIG_GPIO_PCA953X_IRQ
  924. if (chip->driver_data & PCA_PCAL) {
  925. ret = regcache_sync_region(chip->regmap, PCAL953X_IN_LATCH,
  926. PCAL953X_IN_LATCH + NBANK(chip));
  927. if (ret) {
  928. dev_err(dev, "Failed to sync INT latch registers: %d\n",
  929. ret);
  930. return ret;
  931. }
  932. ret = regcache_sync_region(chip->regmap, PCAL953X_INT_MASK,
  933. PCAL953X_INT_MASK + NBANK(chip));
  934. if (ret) {
  935. dev_err(dev, "Failed to sync INT mask registers: %d\n",
  936. ret);
  937. return ret;
  938. }
  939. }
  940. #endif
  941. return 0;
  942. }
  943. static int pca953x_suspend(struct device *dev)
  944. {
  945. struct pca953x_chip *chip = dev_get_drvdata(dev);
  946. regcache_cache_only(chip->regmap, true);
  947. if (atomic_read(&chip->wakeup_path))
  948. device_set_wakeup_path(dev);
  949. else
  950. regulator_disable(chip->regulator);
  951. return 0;
  952. }
  953. static int pca953x_resume(struct device *dev)
  954. {
  955. struct pca953x_chip *chip = dev_get_drvdata(dev);
  956. int ret;
  957. if (!atomic_read(&chip->wakeup_path)) {
  958. ret = regulator_enable(chip->regulator);
  959. if (ret) {
  960. dev_err(dev, "Failed to enable regulator: %d\n", ret);
  961. return 0;
  962. }
  963. }
  964. regcache_cache_only(chip->regmap, false);
  965. regcache_mark_dirty(chip->regmap);
  966. ret = pca953x_regcache_sync(dev);
  967. if (ret)
  968. return ret;
  969. ret = regcache_sync(chip->regmap);
  970. if (ret) {
  971. dev_err(dev, "Failed to restore register map: %d\n", ret);
  972. return ret;
  973. }
  974. return 0;
  975. }
  976. #endif
  977. /* convenience to stop overlong match-table lines */
  978. #define OF_953X(__nrgpio, __int) (void *)(__nrgpio | PCA953X_TYPE | __int)
  979. #define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int)
  980. static const struct of_device_id pca953x_dt_ids[] = {
  981. { .compatible = "nxp,pca6416", .data = OF_953X(16, PCA_INT), },
  982. { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), },
  983. { .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), },
  984. { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), },
  985. { .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), },
  986. { .compatible = "nxp,pca9537", .data = OF_953X( 4, PCA_INT), },
  987. { .compatible = "nxp,pca9538", .data = OF_953X( 8, PCA_INT), },
  988. { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), },
  989. { .compatible = "nxp,pca9554", .data = OF_953X( 8, PCA_INT), },
  990. { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), },
  991. { .compatible = "nxp,pca9556", .data = OF_953X( 8, 0), },
  992. { .compatible = "nxp,pca9557", .data = OF_953X( 8, 0), },
  993. { .compatible = "nxp,pca9574", .data = OF_957X( 8, PCA_INT), },
  994. { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), },
  995. { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), },
  996. { .compatible = "nxp,pcal6416", .data = OF_953X(16, PCA_LATCH_INT), },
  997. { .compatible = "nxp,pcal6524", .data = OF_953X(24, PCA_LATCH_INT), },
  998. { .compatible = "nxp,pcal9535", .data = OF_953X(16, PCA_LATCH_INT), },
  999. { .compatible = "nxp,pcal9554b", .data = OF_953X( 8, PCA_LATCH_INT), },
  1000. { .compatible = "nxp,pcal9555a", .data = OF_953X(16, PCA_LATCH_INT), },
  1001. { .compatible = "maxim,max7310", .data = OF_953X( 8, 0), },
  1002. { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), },
  1003. { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), },
  1004. { .compatible = "maxim,max7315", .data = OF_953X( 8, PCA_INT), },
  1005. { .compatible = "maxim,max7318", .data = OF_953X(16, PCA_INT), },
  1006. { .compatible = "ti,pca6107", .data = OF_953X( 8, PCA_INT), },
  1007. { .compatible = "ti,pca9536", .data = OF_953X( 4, 0), },
  1008. { .compatible = "ti,tca6408", .data = OF_953X( 8, PCA_INT), },
  1009. { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), },
  1010. { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), },
  1011. { .compatible = "ti,tca9539", .data = OF_953X(16, PCA_INT), },
  1012. { .compatible = "onnn,cat9554", .data = OF_953X( 8, PCA_INT), },
  1013. { .compatible = "onnn,pca9654", .data = OF_953X( 8, PCA_INT), },
  1014. { .compatible = "onnn,pca9655", .data = OF_953X(16, PCA_INT), },
  1015. { .compatible = "exar,xra1202", .data = OF_953X( 8, 0), },
  1016. { }
  1017. };
  1018. MODULE_DEVICE_TABLE(of, pca953x_dt_ids);
  1019. static SIMPLE_DEV_PM_OPS(pca953x_pm_ops, pca953x_suspend, pca953x_resume);
  1020. static struct i2c_driver pca953x_driver = {
  1021. .driver = {
  1022. .name = "pca953x",
  1023. .pm = &pca953x_pm_ops,
  1024. .of_match_table = pca953x_dt_ids,
  1025. .acpi_match_table = pca953x_acpi_ids,
  1026. },
  1027. .probe = pca953x_probe,
  1028. .remove = pca953x_remove,
  1029. .id_table = pca953x_id,
  1030. };
  1031. static int __init pca953x_init(void)
  1032. {
  1033. return i2c_add_driver(&pca953x_driver);
  1034. }
  1035. /* register after i2c postcore initcall and before
  1036. * subsys initcalls that may rely on these GPIOs
  1037. */
  1038. subsys_initcall(pca953x_init);
  1039. static void __exit pca953x_exit(void)
  1040. {
  1041. i2c_del_driver(&pca953x_driver);
  1042. }
  1043. module_exit(pca953x_exit);
  1044. MODULE_AUTHOR("eric miao <eric.miao@marvell.com>");
  1045. MODULE_DESCRIPTION("GPIO expander driver for PCA953x");
  1046. MODULE_LICENSE("GPL");