gpio-omap.c 42 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Support functions for OMAP GPIO
  4. *
  5. * Copyright (C) 2003-2005 Nokia Corporation
  6. * Written by Juha Yrjölä <juha.yrjola@nokia.com>
  7. *
  8. * Copyright (C) 2009 Texas Instruments
  9. * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  10. */
  11. #include <linux/init.h>
  12. #include <linux/module.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/syscore_ops.h>
  15. #include <linux/err.h>
  16. #include <linux/clk.h>
  17. #include <linux/io.h>
  18. #include <linux/cpu_pm.h>
  19. #include <linux/device.h>
  20. #include <linux/pm_runtime.h>
  21. #include <linux/pm.h>
  22. #include <linux/of.h>
  23. #include <linux/of_device.h>
  24. #include <linux/gpio/driver.h>
  25. #include <linux/bitops.h>
  26. #include <linux/platform_data/gpio-omap.h>
  27. #define OMAP4_GPIO_DEBOUNCINGTIME_MASK 0xFF
  28. struct gpio_regs {
  29. u32 sysconfig;
  30. u32 irqenable1;
  31. u32 irqenable2;
  32. u32 wake_en;
  33. u32 ctrl;
  34. u32 oe;
  35. u32 leveldetect0;
  36. u32 leveldetect1;
  37. u32 risingdetect;
  38. u32 fallingdetect;
  39. u32 dataout;
  40. u32 debounce;
  41. u32 debounce_en;
  42. };
  43. struct gpio_bank {
  44. void __iomem *base;
  45. const struct omap_gpio_reg_offs *regs;
  46. int irq;
  47. u32 non_wakeup_gpios;
  48. u32 enabled_non_wakeup_gpios;
  49. struct gpio_regs context;
  50. u32 saved_datain;
  51. u32 level_mask;
  52. u32 toggle_mask;
  53. raw_spinlock_t lock;
  54. raw_spinlock_t wa_lock;
  55. struct gpio_chip chip;
  56. struct clk *dbck;
  57. struct notifier_block nb;
  58. unsigned int is_suspended:1;
  59. unsigned int needs_resume:1;
  60. u32 mod_usage;
  61. u32 irq_usage;
  62. u32 dbck_enable_mask;
  63. bool dbck_enabled;
  64. bool is_mpuio;
  65. bool dbck_flag;
  66. bool loses_context;
  67. bool context_valid;
  68. int stride;
  69. u32 width;
  70. int context_loss_count;
  71. void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
  72. int (*get_context_loss_count)(struct device *dev);
  73. };
  74. #define GPIO_MOD_CTRL_BIT BIT(0)
  75. #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)
  76. #define LINE_USED(line, offset) (line & (BIT(offset)))
  77. static void omap_gpio_unmask_irq(struct irq_data *d);
  78. static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d)
  79. {
  80. struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
  81. return gpiochip_get_data(chip);
  82. }
  83. static inline u32 omap_gpio_rmw(void __iomem *reg, u32 mask, bool set)
  84. {
  85. u32 val = readl_relaxed(reg);
  86. if (set)
  87. val |= mask;
  88. else
  89. val &= ~mask;
  90. writel_relaxed(val, reg);
  91. return val;
  92. }
  93. static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio,
  94. int is_input)
  95. {
  96. bank->context.oe = omap_gpio_rmw(bank->base + bank->regs->direction,
  97. BIT(gpio), is_input);
  98. }
  99. /* set data out value using dedicate set/clear register */
  100. static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset,
  101. int enable)
  102. {
  103. void __iomem *reg = bank->base;
  104. u32 l = BIT(offset);
  105. if (enable) {
  106. reg += bank->regs->set_dataout;
  107. bank->context.dataout |= l;
  108. } else {
  109. reg += bank->regs->clr_dataout;
  110. bank->context.dataout &= ~l;
  111. }
  112. writel_relaxed(l, reg);
  113. }
  114. /* set data out value using mask register */
  115. static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset,
  116. int enable)
  117. {
  118. bank->context.dataout = omap_gpio_rmw(bank->base + bank->regs->dataout,
  119. BIT(offset), enable);
  120. }
  121. static inline void omap_gpio_dbck_enable(struct gpio_bank *bank)
  122. {
  123. if (bank->dbck_enable_mask && !bank->dbck_enabled) {
  124. clk_enable(bank->dbck);
  125. bank->dbck_enabled = true;
  126. writel_relaxed(bank->dbck_enable_mask,
  127. bank->base + bank->regs->debounce_en);
  128. }
  129. }
  130. static inline void omap_gpio_dbck_disable(struct gpio_bank *bank)
  131. {
  132. if (bank->dbck_enable_mask && bank->dbck_enabled) {
  133. /*
  134. * Disable debounce before cutting it's clock. If debounce is
  135. * enabled but the clock is not, GPIO module seems to be unable
  136. * to detect events and generate interrupts at least on OMAP3.
  137. */
  138. writel_relaxed(0, bank->base + bank->regs->debounce_en);
  139. clk_disable(bank->dbck);
  140. bank->dbck_enabled = false;
  141. }
  142. }
  143. /**
  144. * omap2_set_gpio_debounce - low level gpio debounce time
  145. * @bank: the gpio bank we're acting upon
  146. * @offset: the gpio number on this @bank
  147. * @debounce: debounce time to use
  148. *
  149. * OMAP's debounce time is in 31us steps
  150. * <debounce time> = (GPIO_DEBOUNCINGTIME[7:0].DEBOUNCETIME + 1) x 31
  151. * so we need to convert and round up to the closest unit.
  152. *
  153. * Return: 0 on success, negative error otherwise.
  154. */
  155. static int omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset,
  156. unsigned debounce)
  157. {
  158. u32 val;
  159. u32 l;
  160. bool enable = !!debounce;
  161. if (!bank->dbck_flag)
  162. return -ENOTSUPP;
  163. if (enable) {
  164. debounce = DIV_ROUND_UP(debounce, 31) - 1;
  165. if ((debounce & OMAP4_GPIO_DEBOUNCINGTIME_MASK) != debounce)
  166. return -EINVAL;
  167. }
  168. l = BIT(offset);
  169. clk_enable(bank->dbck);
  170. writel_relaxed(debounce, bank->base + bank->regs->debounce);
  171. val = omap_gpio_rmw(bank->base + bank->regs->debounce_en, l, enable);
  172. bank->dbck_enable_mask = val;
  173. clk_disable(bank->dbck);
  174. /*
  175. * Enable debounce clock per module.
  176. * This call is mandatory because in omap_gpio_request() when
  177. * *_runtime_get_sync() is called, _gpio_dbck_enable() within
  178. * runtime callbck fails to turn on dbck because dbck_enable_mask
  179. * used within _gpio_dbck_enable() is still not initialized at
  180. * that point. Therefore we have to enable dbck here.
  181. */
  182. omap_gpio_dbck_enable(bank);
  183. if (bank->dbck_enable_mask) {
  184. bank->context.debounce = debounce;
  185. bank->context.debounce_en = val;
  186. }
  187. return 0;
  188. }
  189. /**
  190. * omap_clear_gpio_debounce - clear debounce settings for a gpio
  191. * @bank: the gpio bank we're acting upon
  192. * @offset: the gpio number on this @bank
  193. *
  194. * If a gpio is using debounce, then clear the debounce enable bit and if
  195. * this is the only gpio in this bank using debounce, then clear the debounce
  196. * time too. The debounce clock will also be disabled when calling this function
  197. * if this is the only gpio in the bank using debounce.
  198. */
  199. static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset)
  200. {
  201. u32 gpio_bit = BIT(offset);
  202. if (!bank->dbck_flag)
  203. return;
  204. if (!(bank->dbck_enable_mask & gpio_bit))
  205. return;
  206. bank->dbck_enable_mask &= ~gpio_bit;
  207. bank->context.debounce_en &= ~gpio_bit;
  208. writel_relaxed(bank->context.debounce_en,
  209. bank->base + bank->regs->debounce_en);
  210. if (!bank->dbck_enable_mask) {
  211. bank->context.debounce = 0;
  212. writel_relaxed(bank->context.debounce, bank->base +
  213. bank->regs->debounce);
  214. clk_disable(bank->dbck);
  215. bank->dbck_enabled = false;
  216. }
  217. }
  218. /*
  219. * Off mode wake-up capable GPIOs in bank(s) that are in the wakeup domain.
  220. * See TRM section for GPIO for "Wake-Up Generation" for the list of GPIOs
  221. * in wakeup domain. If bank->non_wakeup_gpios is not configured, assume none
  222. * are capable waking up the system from off mode.
  223. */
  224. static bool omap_gpio_is_off_wakeup_capable(struct gpio_bank *bank, u32 gpio_mask)
  225. {
  226. u32 no_wake = bank->non_wakeup_gpios;
  227. if (no_wake)
  228. return !!(~no_wake & gpio_mask);
  229. return false;
  230. }
  231. static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio,
  232. unsigned trigger)
  233. {
  234. void __iomem *base = bank->base;
  235. u32 gpio_bit = BIT(gpio);
  236. omap_gpio_rmw(base + bank->regs->leveldetect0, gpio_bit,
  237. trigger & IRQ_TYPE_LEVEL_LOW);
  238. omap_gpio_rmw(base + bank->regs->leveldetect1, gpio_bit,
  239. trigger & IRQ_TYPE_LEVEL_HIGH);
  240. /*
  241. * We need the edge detection enabled for to allow the GPIO block
  242. * to be woken from idle state. Set the appropriate edge detection
  243. * in addition to the level detection.
  244. */
  245. omap_gpio_rmw(base + bank->regs->risingdetect, gpio_bit,
  246. trigger & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH));
  247. omap_gpio_rmw(base + bank->regs->fallingdetect, gpio_bit,
  248. trigger & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW));
  249. bank->context.leveldetect0 =
  250. readl_relaxed(bank->base + bank->regs->leveldetect0);
  251. bank->context.leveldetect1 =
  252. readl_relaxed(bank->base + bank->regs->leveldetect1);
  253. bank->context.risingdetect =
  254. readl_relaxed(bank->base + bank->regs->risingdetect);
  255. bank->context.fallingdetect =
  256. readl_relaxed(bank->base + bank->regs->fallingdetect);
  257. bank->level_mask = bank->context.leveldetect0 |
  258. bank->context.leveldetect1;
  259. /* This part needs to be executed always for OMAP{34xx, 44xx} */
  260. if (!bank->regs->irqctrl && !omap_gpio_is_off_wakeup_capable(bank, gpio)) {
  261. /*
  262. * Log the edge gpio and manually trigger the IRQ
  263. * after resume if the input level changes
  264. * to avoid irq lost during PER RET/OFF mode
  265. * Applies for omap2 non-wakeup gpio and all omap3 gpios
  266. */
  267. if (trigger & IRQ_TYPE_EDGE_BOTH)
  268. bank->enabled_non_wakeup_gpios |= gpio_bit;
  269. else
  270. bank->enabled_non_wakeup_gpios &= ~gpio_bit;
  271. }
  272. }
  273. /*
  274. * This only applies to chips that can't do both rising and falling edge
  275. * detection at once. For all other chips, this function is a noop.
  276. */
  277. static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
  278. {
  279. if (IS_ENABLED(CONFIG_ARCH_OMAP1) && bank->regs->irqctrl) {
  280. void __iomem *reg = bank->base + bank->regs->irqctrl;
  281. writel_relaxed(readl_relaxed(reg) ^ BIT(gpio), reg);
  282. }
  283. }
  284. static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio,
  285. unsigned trigger)
  286. {
  287. void __iomem *reg = bank->base;
  288. u32 l = 0;
  289. if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
  290. omap_set_gpio_trigger(bank, gpio, trigger);
  291. } else if (bank->regs->irqctrl) {
  292. reg += bank->regs->irqctrl;
  293. l = readl_relaxed(reg);
  294. if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
  295. bank->toggle_mask |= BIT(gpio);
  296. if (trigger & IRQ_TYPE_EDGE_RISING)
  297. l |= BIT(gpio);
  298. else if (trigger & IRQ_TYPE_EDGE_FALLING)
  299. l &= ~(BIT(gpio));
  300. else
  301. return -EINVAL;
  302. writel_relaxed(l, reg);
  303. } else if (bank->regs->edgectrl1) {
  304. if (gpio & 0x08)
  305. reg += bank->regs->edgectrl2;
  306. else
  307. reg += bank->regs->edgectrl1;
  308. gpio &= 0x07;
  309. l = readl_relaxed(reg);
  310. l &= ~(3 << (gpio << 1));
  311. if (trigger & IRQ_TYPE_EDGE_RISING)
  312. l |= 2 << (gpio << 1);
  313. if (trigger & IRQ_TYPE_EDGE_FALLING)
  314. l |= BIT(gpio << 1);
  315. writel_relaxed(l, reg);
  316. }
  317. return 0;
  318. }
  319. static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset)
  320. {
  321. if (bank->regs->pinctrl) {
  322. void __iomem *reg = bank->base + bank->regs->pinctrl;
  323. /* Claim the pin for MPU */
  324. writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg);
  325. }
  326. if (bank->regs->ctrl && !BANK_USED(bank)) {
  327. void __iomem *reg = bank->base + bank->regs->ctrl;
  328. u32 ctrl;
  329. ctrl = readl_relaxed(reg);
  330. /* Module is enabled, clocks are not gated */
  331. ctrl &= ~GPIO_MOD_CTRL_BIT;
  332. writel_relaxed(ctrl, reg);
  333. bank->context.ctrl = ctrl;
  334. }
  335. }
  336. static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset)
  337. {
  338. if (bank->regs->ctrl && !BANK_USED(bank)) {
  339. void __iomem *reg = bank->base + bank->regs->ctrl;
  340. u32 ctrl;
  341. ctrl = readl_relaxed(reg);
  342. /* Module is disabled, clocks are gated */
  343. ctrl |= GPIO_MOD_CTRL_BIT;
  344. writel_relaxed(ctrl, reg);
  345. bank->context.ctrl = ctrl;
  346. }
  347. }
  348. static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset)
  349. {
  350. void __iomem *reg = bank->base + bank->regs->direction;
  351. return readl_relaxed(reg) & BIT(offset);
  352. }
  353. static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset)
  354. {
  355. if (!LINE_USED(bank->mod_usage, offset)) {
  356. omap_enable_gpio_module(bank, offset);
  357. omap_set_gpio_direction(bank, offset, 1);
  358. }
  359. bank->irq_usage |= BIT(offset);
  360. }
  361. static int omap_gpio_irq_type(struct irq_data *d, unsigned type)
  362. {
  363. struct gpio_bank *bank = omap_irq_data_get_bank(d);
  364. int retval;
  365. unsigned long flags;
  366. unsigned offset = d->hwirq;
  367. if (type & ~IRQ_TYPE_SENSE_MASK)
  368. return -EINVAL;
  369. if (!bank->regs->leveldetect0 &&
  370. (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
  371. return -EINVAL;
  372. raw_spin_lock_irqsave(&bank->lock, flags);
  373. retval = omap_set_gpio_triggering(bank, offset, type);
  374. if (retval) {
  375. raw_spin_unlock_irqrestore(&bank->lock, flags);
  376. goto error;
  377. }
  378. omap_gpio_init_irq(bank, offset);
  379. if (!omap_gpio_is_input(bank, offset)) {
  380. raw_spin_unlock_irqrestore(&bank->lock, flags);
  381. retval = -EINVAL;
  382. goto error;
  383. }
  384. raw_spin_unlock_irqrestore(&bank->lock, flags);
  385. if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
  386. irq_set_handler_locked(d, handle_level_irq);
  387. else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
  388. /*
  389. * Edge IRQs are already cleared/acked in irq_handler and
  390. * not need to be masked, as result handle_edge_irq()
  391. * logic is excessed here and may cause lose of interrupts.
  392. * So just use handle_simple_irq.
  393. */
  394. irq_set_handler_locked(d, handle_simple_irq);
  395. return 0;
  396. error:
  397. return retval;
  398. }
  399. static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
  400. {
  401. void __iomem *reg = bank->base;
  402. reg += bank->regs->irqstatus;
  403. writel_relaxed(gpio_mask, reg);
  404. /* Workaround for clearing DSP GPIO interrupts to allow retention */
  405. if (bank->regs->irqstatus2) {
  406. reg = bank->base + bank->regs->irqstatus2;
  407. writel_relaxed(gpio_mask, reg);
  408. }
  409. /* Flush posted write for the irq status to avoid spurious interrupts */
  410. readl_relaxed(reg);
  411. }
  412. static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank,
  413. unsigned offset)
  414. {
  415. omap_clear_gpio_irqbank(bank, BIT(offset));
  416. }
  417. static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank)
  418. {
  419. void __iomem *reg = bank->base;
  420. u32 l;
  421. u32 mask = (BIT(bank->width)) - 1;
  422. reg += bank->regs->irqenable;
  423. l = readl_relaxed(reg);
  424. if (bank->regs->irqenable_inv)
  425. l = ~l;
  426. l &= mask;
  427. return l;
  428. }
  429. static inline void omap_set_gpio_irqenable(struct gpio_bank *bank,
  430. unsigned offset, int enable)
  431. {
  432. void __iomem *reg = bank->base;
  433. u32 gpio_mask = BIT(offset);
  434. if (bank->regs->set_irqenable && bank->regs->clr_irqenable) {
  435. if (enable) {
  436. reg += bank->regs->set_irqenable;
  437. bank->context.irqenable1 |= gpio_mask;
  438. } else {
  439. reg += bank->regs->clr_irqenable;
  440. bank->context.irqenable1 &= ~gpio_mask;
  441. }
  442. writel_relaxed(gpio_mask, reg);
  443. } else {
  444. bank->context.irqenable1 =
  445. omap_gpio_rmw(reg + bank->regs->irqenable, gpio_mask,
  446. enable ^ bank->regs->irqenable_inv);
  447. }
  448. /*
  449. * Program GPIO wakeup along with IRQ enable to satisfy OMAP4430 TRM
  450. * note requiring correlation between the IRQ enable registers and
  451. * the wakeup registers. In any case, we want wakeup from idle
  452. * enabled for the GPIOs which support this feature.
  453. */
  454. if (bank->regs->wkup_en &&
  455. (bank->regs->edgectrl1 || !(bank->non_wakeup_gpios & gpio_mask))) {
  456. bank->context.wake_en =
  457. omap_gpio_rmw(bank->base + bank->regs->wkup_en,
  458. gpio_mask, enable);
  459. }
  460. }
  461. /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
  462. static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable)
  463. {
  464. struct gpio_bank *bank = omap_irq_data_get_bank(d);
  465. return irq_set_irq_wake(bank->irq, enable);
  466. }
  467. /*
  468. * We need to unmask the GPIO bank interrupt as soon as possible to
  469. * avoid missing GPIO interrupts for other lines in the bank.
  470. * Then we need to mask-read-clear-unmask the triggered GPIO lines
  471. * in the bank to avoid missing nested interrupts for a GPIO line.
  472. * If we wait to unmask individual GPIO lines in the bank after the
  473. * line's interrupt handler has been run, we may miss some nested
  474. * interrupts.
  475. */
  476. static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank)
  477. {
  478. void __iomem *isr_reg = NULL;
  479. u32 enabled, isr, edge;
  480. unsigned int bit;
  481. struct gpio_bank *bank = gpiobank;
  482. unsigned long wa_lock_flags;
  483. unsigned long lock_flags;
  484. isr_reg = bank->base + bank->regs->irqstatus;
  485. if (WARN_ON(!isr_reg))
  486. goto exit;
  487. if (WARN_ONCE(!pm_runtime_active(bank->chip.parent),
  488. "gpio irq%i while runtime suspended?\n", irq))
  489. return IRQ_NONE;
  490. while (1) {
  491. raw_spin_lock_irqsave(&bank->lock, lock_flags);
  492. enabled = omap_get_gpio_irqbank_mask(bank);
  493. isr = readl_relaxed(isr_reg) & enabled;
  494. /*
  495. * Clear edge sensitive interrupts before calling handler(s)
  496. * so subsequent edge transitions are not missed while the
  497. * handlers are running.
  498. */
  499. edge = isr & ~bank->level_mask;
  500. if (edge)
  501. omap_clear_gpio_irqbank(bank, edge);
  502. raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
  503. if (!isr)
  504. break;
  505. while (isr) {
  506. bit = __ffs(isr);
  507. isr &= ~(BIT(bit));
  508. raw_spin_lock_irqsave(&bank->lock, lock_flags);
  509. /*
  510. * Some chips can't respond to both rising and falling
  511. * at the same time. If this irq was requested with
  512. * both flags, we need to flip the ICR data for the IRQ
  513. * to respond to the IRQ for the opposite direction.
  514. * This will be indicated in the bank toggle_mask.
  515. */
  516. if (bank->toggle_mask & (BIT(bit)))
  517. omap_toggle_gpio_edge_triggering(bank, bit);
  518. raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
  519. raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags);
  520. generic_handle_irq(irq_find_mapping(bank->chip.irq.domain,
  521. bit));
  522. raw_spin_unlock_irqrestore(&bank->wa_lock,
  523. wa_lock_flags);
  524. }
  525. }
  526. exit:
  527. return IRQ_HANDLED;
  528. }
  529. static unsigned int omap_gpio_irq_startup(struct irq_data *d)
  530. {
  531. struct gpio_bank *bank = omap_irq_data_get_bank(d);
  532. unsigned long flags;
  533. unsigned offset = d->hwirq;
  534. raw_spin_lock_irqsave(&bank->lock, flags);
  535. if (!LINE_USED(bank->mod_usage, offset))
  536. omap_set_gpio_direction(bank, offset, 1);
  537. omap_enable_gpio_module(bank, offset);
  538. bank->irq_usage |= BIT(offset);
  539. raw_spin_unlock_irqrestore(&bank->lock, flags);
  540. omap_gpio_unmask_irq(d);
  541. return 0;
  542. }
  543. static void omap_gpio_irq_shutdown(struct irq_data *d)
  544. {
  545. struct gpio_bank *bank = omap_irq_data_get_bank(d);
  546. unsigned long flags;
  547. unsigned offset = d->hwirq;
  548. raw_spin_lock_irqsave(&bank->lock, flags);
  549. bank->irq_usage &= ~(BIT(offset));
  550. omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
  551. omap_clear_gpio_irqstatus(bank, offset);
  552. omap_set_gpio_irqenable(bank, offset, 0);
  553. if (!LINE_USED(bank->mod_usage, offset))
  554. omap_clear_gpio_debounce(bank, offset);
  555. omap_disable_gpio_module(bank, offset);
  556. raw_spin_unlock_irqrestore(&bank->lock, flags);
  557. }
  558. static void omap_gpio_irq_bus_lock(struct irq_data *data)
  559. {
  560. struct gpio_bank *bank = omap_irq_data_get_bank(data);
  561. pm_runtime_get_sync(bank->chip.parent);
  562. }
  563. static void gpio_irq_bus_sync_unlock(struct irq_data *data)
  564. {
  565. struct gpio_bank *bank = omap_irq_data_get_bank(data);
  566. pm_runtime_put(bank->chip.parent);
  567. }
  568. static void omap_gpio_mask_irq(struct irq_data *d)
  569. {
  570. struct gpio_bank *bank = omap_irq_data_get_bank(d);
  571. unsigned offset = d->hwirq;
  572. unsigned long flags;
  573. raw_spin_lock_irqsave(&bank->lock, flags);
  574. omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
  575. omap_set_gpio_irqenable(bank, offset, 0);
  576. raw_spin_unlock_irqrestore(&bank->lock, flags);
  577. }
  578. static void omap_gpio_unmask_irq(struct irq_data *d)
  579. {
  580. struct gpio_bank *bank = omap_irq_data_get_bank(d);
  581. unsigned offset = d->hwirq;
  582. u32 trigger = irqd_get_trigger_type(d);
  583. unsigned long flags;
  584. raw_spin_lock_irqsave(&bank->lock, flags);
  585. omap_set_gpio_irqenable(bank, offset, 1);
  586. /*
  587. * For level-triggered GPIOs, clearing must be done after the source
  588. * is cleared, thus after the handler has run. OMAP4 needs this done
  589. * after enabing the interrupt to clear the wakeup status.
  590. */
  591. if (bank->regs->leveldetect0 && bank->regs->wkup_en &&
  592. trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
  593. omap_clear_gpio_irqstatus(bank, offset);
  594. if (trigger)
  595. omap_set_gpio_triggering(bank, offset, trigger);
  596. raw_spin_unlock_irqrestore(&bank->lock, flags);
  597. }
  598. /*---------------------------------------------------------------------*/
  599. static int omap_mpuio_suspend_noirq(struct device *dev)
  600. {
  601. struct gpio_bank *bank = dev_get_drvdata(dev);
  602. void __iomem *mask_reg = bank->base +
  603. OMAP_MPUIO_GPIO_MASKIT / bank->stride;
  604. unsigned long flags;
  605. raw_spin_lock_irqsave(&bank->lock, flags);
  606. writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg);
  607. raw_spin_unlock_irqrestore(&bank->lock, flags);
  608. return 0;
  609. }
  610. static int omap_mpuio_resume_noirq(struct device *dev)
  611. {
  612. struct gpio_bank *bank = dev_get_drvdata(dev);
  613. void __iomem *mask_reg = bank->base +
  614. OMAP_MPUIO_GPIO_MASKIT / bank->stride;
  615. unsigned long flags;
  616. raw_spin_lock_irqsave(&bank->lock, flags);
  617. writel_relaxed(bank->context.wake_en, mask_reg);
  618. raw_spin_unlock_irqrestore(&bank->lock, flags);
  619. return 0;
  620. }
  621. static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
  622. .suspend_noirq = omap_mpuio_suspend_noirq,
  623. .resume_noirq = omap_mpuio_resume_noirq,
  624. };
  625. /* use platform_driver for this. */
  626. static struct platform_driver omap_mpuio_driver = {
  627. .driver = {
  628. .name = "mpuio",
  629. .pm = &omap_mpuio_dev_pm_ops,
  630. },
  631. };
  632. static struct platform_device omap_mpuio_device = {
  633. .name = "mpuio",
  634. .id = -1,
  635. .dev = {
  636. .driver = &omap_mpuio_driver.driver,
  637. }
  638. /* could list the /proc/iomem resources */
  639. };
  640. static inline void omap_mpuio_init(struct gpio_bank *bank)
  641. {
  642. platform_set_drvdata(&omap_mpuio_device, bank);
  643. if (platform_driver_register(&omap_mpuio_driver) == 0)
  644. (void) platform_device_register(&omap_mpuio_device);
  645. }
  646. /*---------------------------------------------------------------------*/
  647. static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
  648. {
  649. struct gpio_bank *bank = gpiochip_get_data(chip);
  650. unsigned long flags;
  651. pm_runtime_get_sync(chip->parent);
  652. raw_spin_lock_irqsave(&bank->lock, flags);
  653. omap_enable_gpio_module(bank, offset);
  654. bank->mod_usage |= BIT(offset);
  655. raw_spin_unlock_irqrestore(&bank->lock, flags);
  656. return 0;
  657. }
  658. static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
  659. {
  660. struct gpio_bank *bank = gpiochip_get_data(chip);
  661. unsigned long flags;
  662. raw_spin_lock_irqsave(&bank->lock, flags);
  663. bank->mod_usage &= ~(BIT(offset));
  664. if (!LINE_USED(bank->irq_usage, offset)) {
  665. omap_set_gpio_direction(bank, offset, 1);
  666. omap_clear_gpio_debounce(bank, offset);
  667. }
  668. omap_disable_gpio_module(bank, offset);
  669. raw_spin_unlock_irqrestore(&bank->lock, flags);
  670. pm_runtime_put(chip->parent);
  671. }
  672. static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
  673. {
  674. struct gpio_bank *bank = gpiochip_get_data(chip);
  675. if (readl_relaxed(bank->base + bank->regs->direction) & BIT(offset))
  676. return GPIO_LINE_DIRECTION_IN;
  677. return GPIO_LINE_DIRECTION_OUT;
  678. }
  679. static int omap_gpio_input(struct gpio_chip *chip, unsigned offset)
  680. {
  681. struct gpio_bank *bank;
  682. unsigned long flags;
  683. bank = gpiochip_get_data(chip);
  684. raw_spin_lock_irqsave(&bank->lock, flags);
  685. omap_set_gpio_direction(bank, offset, 1);
  686. raw_spin_unlock_irqrestore(&bank->lock, flags);
  687. return 0;
  688. }
  689. static int omap_gpio_get(struct gpio_chip *chip, unsigned offset)
  690. {
  691. struct gpio_bank *bank = gpiochip_get_data(chip);
  692. void __iomem *reg;
  693. if (omap_gpio_is_input(bank, offset))
  694. reg = bank->base + bank->regs->datain;
  695. else
  696. reg = bank->base + bank->regs->dataout;
  697. return (readl_relaxed(reg) & BIT(offset)) != 0;
  698. }
  699. static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value)
  700. {
  701. struct gpio_bank *bank;
  702. unsigned long flags;
  703. bank = gpiochip_get_data(chip);
  704. raw_spin_lock_irqsave(&bank->lock, flags);
  705. bank->set_dataout(bank, offset, value);
  706. omap_set_gpio_direction(bank, offset, 0);
  707. raw_spin_unlock_irqrestore(&bank->lock, flags);
  708. return 0;
  709. }
  710. static int omap_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
  711. unsigned long *bits)
  712. {
  713. struct gpio_bank *bank = gpiochip_get_data(chip);
  714. void __iomem *base = bank->base;
  715. u32 direction, m, val = 0;
  716. direction = readl_relaxed(base + bank->regs->direction);
  717. m = direction & *mask;
  718. if (m)
  719. val |= readl_relaxed(base + bank->regs->datain) & m;
  720. m = ~direction & *mask;
  721. if (m)
  722. val |= readl_relaxed(base + bank->regs->dataout) & m;
  723. *bits = val;
  724. return 0;
  725. }
  726. static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset,
  727. unsigned debounce)
  728. {
  729. struct gpio_bank *bank;
  730. unsigned long flags;
  731. int ret;
  732. bank = gpiochip_get_data(chip);
  733. raw_spin_lock_irqsave(&bank->lock, flags);
  734. ret = omap2_set_gpio_debounce(bank, offset, debounce);
  735. raw_spin_unlock_irqrestore(&bank->lock, flags);
  736. if (ret)
  737. dev_info(chip->parent,
  738. "Could not set line %u debounce to %u microseconds (%d)",
  739. offset, debounce, ret);
  740. return ret;
  741. }
  742. static int omap_gpio_set_config(struct gpio_chip *chip, unsigned offset,
  743. unsigned long config)
  744. {
  745. u32 debounce;
  746. int ret = -ENOTSUPP;
  747. switch (pinconf_to_config_param(config)) {
  748. case PIN_CONFIG_BIAS_DISABLE:
  749. case PIN_CONFIG_BIAS_PULL_UP:
  750. case PIN_CONFIG_BIAS_PULL_DOWN:
  751. ret = gpiochip_generic_config(chip, offset, config);
  752. break;
  753. case PIN_CONFIG_INPUT_DEBOUNCE:
  754. debounce = pinconf_to_config_argument(config);
  755. ret = omap_gpio_debounce(chip, offset, debounce);
  756. break;
  757. default:
  758. break;
  759. }
  760. return ret;
  761. }
  762. static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
  763. {
  764. struct gpio_bank *bank;
  765. unsigned long flags;
  766. bank = gpiochip_get_data(chip);
  767. raw_spin_lock_irqsave(&bank->lock, flags);
  768. bank->set_dataout(bank, offset, value);
  769. raw_spin_unlock_irqrestore(&bank->lock, flags);
  770. }
  771. static void omap_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask,
  772. unsigned long *bits)
  773. {
  774. struct gpio_bank *bank = gpiochip_get_data(chip);
  775. void __iomem *reg = bank->base + bank->regs->dataout;
  776. unsigned long flags;
  777. u32 l;
  778. raw_spin_lock_irqsave(&bank->lock, flags);
  779. l = (readl_relaxed(reg) & ~*mask) | (*bits & *mask);
  780. writel_relaxed(l, reg);
  781. bank->context.dataout = l;
  782. raw_spin_unlock_irqrestore(&bank->lock, flags);
  783. }
  784. /*---------------------------------------------------------------------*/
  785. static void omap_gpio_show_rev(struct gpio_bank *bank)
  786. {
  787. static bool called;
  788. u32 rev;
  789. if (called || bank->regs->revision == USHRT_MAX)
  790. return;
  791. rev = readw_relaxed(bank->base + bank->regs->revision);
  792. pr_info("OMAP GPIO hardware version %d.%d\n",
  793. (rev >> 4) & 0x0f, rev & 0x0f);
  794. called = true;
  795. }
  796. static void omap_gpio_mod_init(struct gpio_bank *bank)
  797. {
  798. void __iomem *base = bank->base;
  799. u32 l = 0xffffffff;
  800. if (bank->width == 16)
  801. l = 0xffff;
  802. if (bank->is_mpuio) {
  803. writel_relaxed(l, bank->base + bank->regs->irqenable);
  804. return;
  805. }
  806. omap_gpio_rmw(base + bank->regs->irqenable, l,
  807. bank->regs->irqenable_inv);
  808. omap_gpio_rmw(base + bank->regs->irqstatus, l,
  809. !bank->regs->irqenable_inv);
  810. if (bank->regs->debounce_en)
  811. writel_relaxed(0, base + bank->regs->debounce_en);
  812. /* Save OE default value (0xffffffff) in the context */
  813. bank->context.oe = readl_relaxed(bank->base + bank->regs->direction);
  814. /* Initialize interface clk ungated, module enabled */
  815. if (bank->regs->ctrl)
  816. writel_relaxed(0, base + bank->regs->ctrl);
  817. }
  818. static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc)
  819. {
  820. struct gpio_irq_chip *irq;
  821. static int gpio;
  822. const char *label;
  823. int irq_base = 0;
  824. int ret;
  825. /*
  826. * REVISIT eventually switch from OMAP-specific gpio structs
  827. * over to the generic ones
  828. */
  829. bank->chip.request = omap_gpio_request;
  830. bank->chip.free = omap_gpio_free;
  831. bank->chip.get_direction = omap_gpio_get_direction;
  832. bank->chip.direction_input = omap_gpio_input;
  833. bank->chip.get = omap_gpio_get;
  834. bank->chip.get_multiple = omap_gpio_get_multiple;
  835. bank->chip.direction_output = omap_gpio_output;
  836. bank->chip.set_config = omap_gpio_set_config;
  837. bank->chip.set = omap_gpio_set;
  838. bank->chip.set_multiple = omap_gpio_set_multiple;
  839. if (bank->is_mpuio) {
  840. bank->chip.label = "mpuio";
  841. if (bank->regs->wkup_en)
  842. bank->chip.parent = &omap_mpuio_device.dev;
  843. bank->chip.base = OMAP_MPUIO(0);
  844. } else {
  845. label = devm_kasprintf(bank->chip.parent, GFP_KERNEL, "gpio-%d-%d",
  846. gpio, gpio + bank->width - 1);
  847. if (!label)
  848. return -ENOMEM;
  849. bank->chip.label = label;
  850. bank->chip.base = gpio;
  851. }
  852. bank->chip.ngpio = bank->width;
  853. #ifdef CONFIG_ARCH_OMAP1
  854. /*
  855. * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop
  856. * irq_alloc_descs() since a base IRQ offset will no longer be needed.
  857. */
  858. irq_base = devm_irq_alloc_descs(bank->chip.parent,
  859. -1, 0, bank->width, 0);
  860. if (irq_base < 0) {
  861. dev_err(bank->chip.parent, "Couldn't allocate IRQ numbers\n");
  862. return -ENODEV;
  863. }
  864. #endif
  865. /* MPUIO is a bit different, reading IRQ status clears it */
  866. if (bank->is_mpuio && !bank->regs->wkup_en)
  867. irqc->irq_set_wake = NULL;
  868. irq = &bank->chip.irq;
  869. irq->chip = irqc;
  870. irq->handler = handle_bad_irq;
  871. irq->default_type = IRQ_TYPE_NONE;
  872. irq->num_parents = 1;
  873. irq->parents = &bank->irq;
  874. irq->first = irq_base;
  875. ret = gpiochip_add_data(&bank->chip, bank);
  876. if (ret) {
  877. dev_err(bank->chip.parent,
  878. "Could not register gpio chip %d\n", ret);
  879. return ret;
  880. }
  881. ret = devm_request_irq(bank->chip.parent, bank->irq,
  882. omap_gpio_irq_handler,
  883. 0, dev_name(bank->chip.parent), bank);
  884. if (ret)
  885. gpiochip_remove(&bank->chip);
  886. if (!bank->is_mpuio)
  887. gpio += bank->width;
  888. return ret;
  889. }
  890. static void omap_gpio_init_context(struct gpio_bank *p)
  891. {
  892. const struct omap_gpio_reg_offs *regs = p->regs;
  893. void __iomem *base = p->base;
  894. p->context.sysconfig = readl_relaxed(base + regs->sysconfig);
  895. p->context.ctrl = readl_relaxed(base + regs->ctrl);
  896. p->context.oe = readl_relaxed(base + regs->direction);
  897. p->context.wake_en = readl_relaxed(base + regs->wkup_en);
  898. p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0);
  899. p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1);
  900. p->context.risingdetect = readl_relaxed(base + regs->risingdetect);
  901. p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect);
  902. p->context.irqenable1 = readl_relaxed(base + regs->irqenable);
  903. p->context.irqenable2 = readl_relaxed(base + regs->irqenable2);
  904. p->context.dataout = readl_relaxed(base + regs->dataout);
  905. p->context_valid = true;
  906. }
  907. static void omap_gpio_restore_context(struct gpio_bank *bank)
  908. {
  909. const struct omap_gpio_reg_offs *regs = bank->regs;
  910. void __iomem *base = bank->base;
  911. writel_relaxed(bank->context.sysconfig, base + regs->sysconfig);
  912. writel_relaxed(bank->context.wake_en, base + regs->wkup_en);
  913. writel_relaxed(bank->context.ctrl, base + regs->ctrl);
  914. writel_relaxed(bank->context.leveldetect0, base + regs->leveldetect0);
  915. writel_relaxed(bank->context.leveldetect1, base + regs->leveldetect1);
  916. writel_relaxed(bank->context.risingdetect, base + regs->risingdetect);
  917. writel_relaxed(bank->context.fallingdetect, base + regs->fallingdetect);
  918. writel_relaxed(bank->context.dataout, base + regs->dataout);
  919. writel_relaxed(bank->context.oe, base + regs->direction);
  920. if (bank->dbck_enable_mask) {
  921. writel_relaxed(bank->context.debounce, base + regs->debounce);
  922. writel_relaxed(bank->context.debounce_en,
  923. base + regs->debounce_en);
  924. }
  925. writel_relaxed(bank->context.irqenable1, base + regs->irqenable);
  926. writel_relaxed(bank->context.irqenable2, base + regs->irqenable2);
  927. }
  928. static void omap_gpio_idle(struct gpio_bank *bank, bool may_lose_context)
  929. {
  930. struct device *dev = bank->chip.parent;
  931. void __iomem *base = bank->base;
  932. u32 mask, nowake;
  933. bank->saved_datain = readl_relaxed(base + bank->regs->datain);
  934. /* Save syconfig, it's runtime value can be different from init value */
  935. if (bank->loses_context)
  936. bank->context.sysconfig = readl_relaxed(base + bank->regs->sysconfig);
  937. if (!bank->enabled_non_wakeup_gpios)
  938. goto update_gpio_context_count;
  939. /* Check for pending EDGE_FALLING, ignore EDGE_BOTH */
  940. mask = bank->enabled_non_wakeup_gpios & bank->context.fallingdetect;
  941. mask &= ~bank->context.risingdetect;
  942. bank->saved_datain |= mask;
  943. /* Check for pending EDGE_RISING, ignore EDGE_BOTH */
  944. mask = bank->enabled_non_wakeup_gpios & bank->context.risingdetect;
  945. mask &= ~bank->context.fallingdetect;
  946. bank->saved_datain &= ~mask;
  947. if (!may_lose_context)
  948. goto update_gpio_context_count;
  949. /*
  950. * If going to OFF, remove triggering for all wkup domain
  951. * non-wakeup GPIOs. Otherwise spurious IRQs will be
  952. * generated. See OMAP2420 Errata item 1.101.
  953. */
  954. if (!bank->loses_context && bank->enabled_non_wakeup_gpios) {
  955. nowake = bank->enabled_non_wakeup_gpios;
  956. omap_gpio_rmw(base + bank->regs->fallingdetect, nowake, ~nowake);
  957. omap_gpio_rmw(base + bank->regs->risingdetect, nowake, ~nowake);
  958. }
  959. update_gpio_context_count:
  960. if (bank->get_context_loss_count)
  961. bank->context_loss_count =
  962. bank->get_context_loss_count(dev);
  963. omap_gpio_dbck_disable(bank);
  964. }
  965. static void omap_gpio_unidle(struct gpio_bank *bank)
  966. {
  967. struct device *dev = bank->chip.parent;
  968. u32 l = 0, gen, gen0, gen1;
  969. int c;
  970. /*
  971. * On the first resume during the probe, the context has not
  972. * been initialised and so initialise it now. Also initialise
  973. * the context loss count.
  974. */
  975. if (bank->loses_context && !bank->context_valid) {
  976. omap_gpio_init_context(bank);
  977. if (bank->get_context_loss_count)
  978. bank->context_loss_count =
  979. bank->get_context_loss_count(dev);
  980. }
  981. omap_gpio_dbck_enable(bank);
  982. if (bank->loses_context) {
  983. if (!bank->get_context_loss_count) {
  984. omap_gpio_restore_context(bank);
  985. } else {
  986. c = bank->get_context_loss_count(dev);
  987. if (c != bank->context_loss_count) {
  988. omap_gpio_restore_context(bank);
  989. } else {
  990. return;
  991. }
  992. }
  993. } else {
  994. /* Restore changes done for OMAP2420 errata 1.101 */
  995. writel_relaxed(bank->context.fallingdetect,
  996. bank->base + bank->regs->fallingdetect);
  997. writel_relaxed(bank->context.risingdetect,
  998. bank->base + bank->regs->risingdetect);
  999. }
  1000. l = readl_relaxed(bank->base + bank->regs->datain);
  1001. /*
  1002. * Check if any of the non-wakeup interrupt GPIOs have changed
  1003. * state. If so, generate an IRQ by software. This is
  1004. * horribly racy, but it's the best we can do to work around
  1005. * this silicon bug.
  1006. */
  1007. l ^= bank->saved_datain;
  1008. l &= bank->enabled_non_wakeup_gpios;
  1009. /*
  1010. * No need to generate IRQs for the rising edge for gpio IRQs
  1011. * configured with falling edge only; and vice versa.
  1012. */
  1013. gen0 = l & bank->context.fallingdetect;
  1014. gen0 &= bank->saved_datain;
  1015. gen1 = l & bank->context.risingdetect;
  1016. gen1 &= ~(bank->saved_datain);
  1017. /* FIXME: Consider GPIO IRQs with level detections properly! */
  1018. gen = l & (~(bank->context.fallingdetect) &
  1019. ~(bank->context.risingdetect));
  1020. /* Consider all GPIO IRQs needed to be updated */
  1021. gen |= gen0 | gen1;
  1022. if (gen) {
  1023. u32 old0, old1;
  1024. old0 = readl_relaxed(bank->base + bank->regs->leveldetect0);
  1025. old1 = readl_relaxed(bank->base + bank->regs->leveldetect1);
  1026. if (!bank->regs->irqstatus_raw0) {
  1027. writel_relaxed(old0 | gen, bank->base +
  1028. bank->regs->leveldetect0);
  1029. writel_relaxed(old1 | gen, bank->base +
  1030. bank->regs->leveldetect1);
  1031. }
  1032. if (bank->regs->irqstatus_raw0) {
  1033. writel_relaxed(old0 | l, bank->base +
  1034. bank->regs->leveldetect0);
  1035. writel_relaxed(old1 | l, bank->base +
  1036. bank->regs->leveldetect1);
  1037. }
  1038. writel_relaxed(old0, bank->base + bank->regs->leveldetect0);
  1039. writel_relaxed(old1, bank->base + bank->regs->leveldetect1);
  1040. }
  1041. }
  1042. static int gpio_omap_cpu_notifier(struct notifier_block *nb,
  1043. unsigned long cmd, void *v)
  1044. {
  1045. struct gpio_bank *bank;
  1046. unsigned long flags;
  1047. int ret = NOTIFY_OK;
  1048. u32 isr, mask;
  1049. bank = container_of(nb, struct gpio_bank, nb);
  1050. raw_spin_lock_irqsave(&bank->lock, flags);
  1051. if (bank->is_suspended)
  1052. goto out_unlock;
  1053. switch (cmd) {
  1054. case CPU_CLUSTER_PM_ENTER:
  1055. mask = omap_get_gpio_irqbank_mask(bank);
  1056. isr = readl_relaxed(bank->base + bank->regs->irqstatus) & mask;
  1057. if (isr) {
  1058. ret = NOTIFY_BAD;
  1059. break;
  1060. }
  1061. omap_gpio_idle(bank, true);
  1062. break;
  1063. case CPU_CLUSTER_PM_ENTER_FAILED:
  1064. case CPU_CLUSTER_PM_EXIT:
  1065. omap_gpio_unidle(bank);
  1066. break;
  1067. }
  1068. out_unlock:
  1069. raw_spin_unlock_irqrestore(&bank->lock, flags);
  1070. return ret;
  1071. }
  1072. static const struct omap_gpio_reg_offs omap2_gpio_regs = {
  1073. .revision = OMAP24XX_GPIO_REVISION,
  1074. .sysconfig = OMAP24XX_GPIO_SYSCONFIG,
  1075. .direction = OMAP24XX_GPIO_OE,
  1076. .datain = OMAP24XX_GPIO_DATAIN,
  1077. .dataout = OMAP24XX_GPIO_DATAOUT,
  1078. .set_dataout = OMAP24XX_GPIO_SETDATAOUT,
  1079. .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT,
  1080. .irqstatus = OMAP24XX_GPIO_IRQSTATUS1,
  1081. .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2,
  1082. .irqenable = OMAP24XX_GPIO_IRQENABLE1,
  1083. .irqenable2 = OMAP24XX_GPIO_IRQENABLE2,
  1084. .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1,
  1085. .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1,
  1086. .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL,
  1087. .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN,
  1088. .ctrl = OMAP24XX_GPIO_CTRL,
  1089. .wkup_en = OMAP24XX_GPIO_WAKE_EN,
  1090. .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0,
  1091. .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1,
  1092. .risingdetect = OMAP24XX_GPIO_RISINGDETECT,
  1093. .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT,
  1094. };
  1095. static const struct omap_gpio_reg_offs omap4_gpio_regs = {
  1096. .revision = OMAP4_GPIO_REVISION,
  1097. .sysconfig = OMAP4_GPIO_SYSCONFIG,
  1098. .direction = OMAP4_GPIO_OE,
  1099. .datain = OMAP4_GPIO_DATAIN,
  1100. .dataout = OMAP4_GPIO_DATAOUT,
  1101. .set_dataout = OMAP4_GPIO_SETDATAOUT,
  1102. .clr_dataout = OMAP4_GPIO_CLEARDATAOUT,
  1103. .irqstatus = OMAP4_GPIO_IRQSTATUS0,
  1104. .irqstatus2 = OMAP4_GPIO_IRQSTATUS1,
  1105. .irqstatus_raw0 = OMAP4_GPIO_IRQSTATUSRAW0,
  1106. .irqstatus_raw1 = OMAP4_GPIO_IRQSTATUSRAW1,
  1107. .irqenable = OMAP4_GPIO_IRQSTATUSSET0,
  1108. .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1,
  1109. .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0,
  1110. .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0,
  1111. .debounce = OMAP4_GPIO_DEBOUNCINGTIME,
  1112. .debounce_en = OMAP4_GPIO_DEBOUNCENABLE,
  1113. .ctrl = OMAP4_GPIO_CTRL,
  1114. .wkup_en = OMAP4_GPIO_IRQWAKEN0,
  1115. .leveldetect0 = OMAP4_GPIO_LEVELDETECT0,
  1116. .leveldetect1 = OMAP4_GPIO_LEVELDETECT1,
  1117. .risingdetect = OMAP4_GPIO_RISINGDETECT,
  1118. .fallingdetect = OMAP4_GPIO_FALLINGDETECT,
  1119. };
  1120. static const struct omap_gpio_platform_data omap2_pdata = {
  1121. .regs = &omap2_gpio_regs,
  1122. .bank_width = 32,
  1123. .dbck_flag = false,
  1124. };
  1125. static const struct omap_gpio_platform_data omap3_pdata = {
  1126. .regs = &omap2_gpio_regs,
  1127. .bank_width = 32,
  1128. .dbck_flag = true,
  1129. };
  1130. static const struct omap_gpio_platform_data omap4_pdata = {
  1131. .regs = &omap4_gpio_regs,
  1132. .bank_width = 32,
  1133. .dbck_flag = true,
  1134. };
  1135. static const struct of_device_id omap_gpio_match[] = {
  1136. {
  1137. .compatible = "ti,omap4-gpio",
  1138. .data = &omap4_pdata,
  1139. },
  1140. {
  1141. .compatible = "ti,omap3-gpio",
  1142. .data = &omap3_pdata,
  1143. },
  1144. {
  1145. .compatible = "ti,omap2-gpio",
  1146. .data = &omap2_pdata,
  1147. },
  1148. { },
  1149. };
  1150. MODULE_DEVICE_TABLE(of, omap_gpio_match);
  1151. static int omap_gpio_probe(struct platform_device *pdev)
  1152. {
  1153. struct device *dev = &pdev->dev;
  1154. struct device_node *node = dev->of_node;
  1155. const struct of_device_id *match;
  1156. const struct omap_gpio_platform_data *pdata;
  1157. struct gpio_bank *bank;
  1158. struct irq_chip *irqc;
  1159. int ret;
  1160. match = of_match_device(of_match_ptr(omap_gpio_match), dev);
  1161. pdata = match ? match->data : dev_get_platdata(dev);
  1162. if (!pdata)
  1163. return -EINVAL;
  1164. bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
  1165. if (!bank)
  1166. return -ENOMEM;
  1167. irqc = devm_kzalloc(dev, sizeof(*irqc), GFP_KERNEL);
  1168. if (!irqc)
  1169. return -ENOMEM;
  1170. irqc->irq_startup = omap_gpio_irq_startup,
  1171. irqc->irq_shutdown = omap_gpio_irq_shutdown,
  1172. irqc->irq_ack = dummy_irq_chip.irq_ack,
  1173. irqc->irq_mask = omap_gpio_mask_irq,
  1174. irqc->irq_unmask = omap_gpio_unmask_irq,
  1175. irqc->irq_set_type = omap_gpio_irq_type,
  1176. irqc->irq_set_wake = omap_gpio_wake_enable,
  1177. irqc->irq_bus_lock = omap_gpio_irq_bus_lock,
  1178. irqc->irq_bus_sync_unlock = gpio_irq_bus_sync_unlock,
  1179. irqc->name = dev_name(&pdev->dev);
  1180. irqc->flags = IRQCHIP_MASK_ON_SUSPEND;
  1181. irqc->parent_device = dev;
  1182. bank->irq = platform_get_irq(pdev, 0);
  1183. if (bank->irq <= 0) {
  1184. if (!bank->irq)
  1185. bank->irq = -ENXIO;
  1186. return dev_err_probe(dev, bank->irq, "can't get irq resource\n");
  1187. }
  1188. bank->chip.parent = dev;
  1189. bank->chip.owner = THIS_MODULE;
  1190. bank->dbck_flag = pdata->dbck_flag;
  1191. bank->stride = pdata->bank_stride;
  1192. bank->width = pdata->bank_width;
  1193. bank->is_mpuio = pdata->is_mpuio;
  1194. bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
  1195. bank->regs = pdata->regs;
  1196. #ifdef CONFIG_OF_GPIO
  1197. bank->chip.of_node = of_node_get(node);
  1198. #endif
  1199. if (node) {
  1200. if (!of_property_read_bool(node, "ti,gpio-always-on"))
  1201. bank->loses_context = true;
  1202. } else {
  1203. bank->loses_context = pdata->loses_context;
  1204. if (bank->loses_context)
  1205. bank->get_context_loss_count =
  1206. pdata->get_context_loss_count;
  1207. }
  1208. if (bank->regs->set_dataout && bank->regs->clr_dataout)
  1209. bank->set_dataout = omap_set_gpio_dataout_reg;
  1210. else
  1211. bank->set_dataout = omap_set_gpio_dataout_mask;
  1212. raw_spin_lock_init(&bank->lock);
  1213. raw_spin_lock_init(&bank->wa_lock);
  1214. /* Static mapping, never released */
  1215. bank->base = devm_platform_ioremap_resource(pdev, 0);
  1216. if (IS_ERR(bank->base)) {
  1217. return PTR_ERR(bank->base);
  1218. }
  1219. if (bank->dbck_flag) {
  1220. bank->dbck = devm_clk_get(dev, "dbclk");
  1221. if (IS_ERR(bank->dbck)) {
  1222. dev_err(dev,
  1223. "Could not get gpio dbck. Disable debounce\n");
  1224. bank->dbck_flag = false;
  1225. } else {
  1226. clk_prepare(bank->dbck);
  1227. }
  1228. }
  1229. platform_set_drvdata(pdev, bank);
  1230. pm_runtime_enable(dev);
  1231. pm_runtime_get_sync(dev);
  1232. if (bank->is_mpuio)
  1233. omap_mpuio_init(bank);
  1234. omap_gpio_mod_init(bank);
  1235. ret = omap_gpio_chip_init(bank, irqc);
  1236. if (ret) {
  1237. pm_runtime_put_sync(dev);
  1238. pm_runtime_disable(dev);
  1239. if (bank->dbck_flag)
  1240. clk_unprepare(bank->dbck);
  1241. return ret;
  1242. }
  1243. omap_gpio_show_rev(bank);
  1244. bank->nb.notifier_call = gpio_omap_cpu_notifier;
  1245. cpu_pm_register_notifier(&bank->nb);
  1246. pm_runtime_put(dev);
  1247. return 0;
  1248. }
  1249. static int omap_gpio_remove(struct platform_device *pdev)
  1250. {
  1251. struct gpio_bank *bank = platform_get_drvdata(pdev);
  1252. cpu_pm_unregister_notifier(&bank->nb);
  1253. gpiochip_remove(&bank->chip);
  1254. pm_runtime_disable(&pdev->dev);
  1255. if (bank->dbck_flag)
  1256. clk_unprepare(bank->dbck);
  1257. return 0;
  1258. }
  1259. static int __maybe_unused omap_gpio_runtime_suspend(struct device *dev)
  1260. {
  1261. struct gpio_bank *bank = dev_get_drvdata(dev);
  1262. unsigned long flags;
  1263. raw_spin_lock_irqsave(&bank->lock, flags);
  1264. omap_gpio_idle(bank, true);
  1265. bank->is_suspended = true;
  1266. raw_spin_unlock_irqrestore(&bank->lock, flags);
  1267. return 0;
  1268. }
  1269. static int __maybe_unused omap_gpio_runtime_resume(struct device *dev)
  1270. {
  1271. struct gpio_bank *bank = dev_get_drvdata(dev);
  1272. unsigned long flags;
  1273. raw_spin_lock_irqsave(&bank->lock, flags);
  1274. omap_gpio_unidle(bank);
  1275. bank->is_suspended = false;
  1276. raw_spin_unlock_irqrestore(&bank->lock, flags);
  1277. return 0;
  1278. }
  1279. static int __maybe_unused omap_gpio_suspend(struct device *dev)
  1280. {
  1281. struct gpio_bank *bank = dev_get_drvdata(dev);
  1282. if (bank->is_suspended)
  1283. return 0;
  1284. bank->needs_resume = 1;
  1285. return omap_gpio_runtime_suspend(dev);
  1286. }
  1287. static int __maybe_unused omap_gpio_resume(struct device *dev)
  1288. {
  1289. struct gpio_bank *bank = dev_get_drvdata(dev);
  1290. if (!bank->needs_resume)
  1291. return 0;
  1292. bank->needs_resume = 0;
  1293. return omap_gpio_runtime_resume(dev);
  1294. }
  1295. static const struct dev_pm_ops gpio_pm_ops = {
  1296. SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
  1297. NULL)
  1298. SET_LATE_SYSTEM_SLEEP_PM_OPS(omap_gpio_suspend, omap_gpio_resume)
  1299. };
  1300. static struct platform_driver omap_gpio_driver = {
  1301. .probe = omap_gpio_probe,
  1302. .remove = omap_gpio_remove,
  1303. .driver = {
  1304. .name = "omap_gpio",
  1305. .pm = &gpio_pm_ops,
  1306. .of_match_table = omap_gpio_match,
  1307. },
  1308. };
  1309. /*
  1310. * gpio driver register needs to be done before
  1311. * machine_init functions access gpio APIs.
  1312. * Hence omap_gpio_drv_reg() is a postcore_initcall.
  1313. */
  1314. static int __init omap_gpio_drv_reg(void)
  1315. {
  1316. return platform_driver_register(&omap_gpio_driver);
  1317. }
  1318. postcore_initcall(omap_gpio_drv_reg);
  1319. static void __exit omap_gpio_exit(void)
  1320. {
  1321. platform_driver_unregister(&omap_gpio_driver);
  1322. }
  1323. module_exit(omap_gpio_exit);
  1324. MODULE_DESCRIPTION("omap gpio driver");
  1325. MODULE_ALIAS("platform:gpio-omap");
  1326. MODULE_LICENSE("GPL v2");