gpio-octeon.c 3.2 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (C) 2011, 2012 Cavium Inc.
  7. */
  8. #include <linux/platform_device.h>
  9. #include <linux/kernel.h>
  10. #include <linux/module.h>
  11. #include <linux/gpio/driver.h>
  12. #include <linux/io.h>
  13. #include <asm/octeon/octeon.h>
  14. #include <asm/octeon/cvmx-gpio-defs.h>
  15. #define RX_DAT 0x80
  16. #define TX_SET 0x88
  17. #define TX_CLEAR 0x90
  18. /*
  19. * The address offset of the GPIO configuration register for a given
  20. * line.
  21. */
  22. static unsigned int bit_cfg_reg(unsigned int offset)
  23. {
  24. /*
  25. * The register stride is 8, with a discontinuity after the
  26. * first 16.
  27. */
  28. if (offset < 16)
  29. return 8 * offset;
  30. else
  31. return 8 * (offset - 16) + 0x100;
  32. }
  33. struct octeon_gpio {
  34. struct gpio_chip chip;
  35. u64 register_base;
  36. };
  37. static int octeon_gpio_dir_in(struct gpio_chip *chip, unsigned offset)
  38. {
  39. struct octeon_gpio *gpio = gpiochip_get_data(chip);
  40. cvmx_write_csr(gpio->register_base + bit_cfg_reg(offset), 0);
  41. return 0;
  42. }
  43. static void octeon_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
  44. {
  45. struct octeon_gpio *gpio = gpiochip_get_data(chip);
  46. u64 mask = 1ull << offset;
  47. u64 reg = gpio->register_base + (value ? TX_SET : TX_CLEAR);
  48. cvmx_write_csr(reg, mask);
  49. }
  50. static int octeon_gpio_dir_out(struct gpio_chip *chip, unsigned offset,
  51. int value)
  52. {
  53. struct octeon_gpio *gpio = gpiochip_get_data(chip);
  54. union cvmx_gpio_bit_cfgx cfgx;
  55. octeon_gpio_set(chip, offset, value);
  56. cfgx.u64 = 0;
  57. cfgx.s.tx_oe = 1;
  58. cvmx_write_csr(gpio->register_base + bit_cfg_reg(offset), cfgx.u64);
  59. return 0;
  60. }
  61. static int octeon_gpio_get(struct gpio_chip *chip, unsigned offset)
  62. {
  63. struct octeon_gpio *gpio = gpiochip_get_data(chip);
  64. u64 read_bits = cvmx_read_csr(gpio->register_base + RX_DAT);
  65. return ((1ull << offset) & read_bits) != 0;
  66. }
  67. static int octeon_gpio_probe(struct platform_device *pdev)
  68. {
  69. struct octeon_gpio *gpio;
  70. struct gpio_chip *chip;
  71. void __iomem *reg_base;
  72. int err = 0;
  73. gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
  74. if (!gpio)
  75. return -ENOMEM;
  76. chip = &gpio->chip;
  77. reg_base = devm_platform_ioremap_resource(pdev, 0);
  78. if (IS_ERR(reg_base))
  79. return PTR_ERR(reg_base);
  80. gpio->register_base = (u64)reg_base;
  81. pdev->dev.platform_data = chip;
  82. chip->label = "octeon-gpio";
  83. chip->parent = &pdev->dev;
  84. chip->owner = THIS_MODULE;
  85. chip->base = 0;
  86. chip->can_sleep = false;
  87. chip->ngpio = 20;
  88. chip->direction_input = octeon_gpio_dir_in;
  89. chip->get = octeon_gpio_get;
  90. chip->direction_output = octeon_gpio_dir_out;
  91. chip->set = octeon_gpio_set;
  92. err = devm_gpiochip_add_data(&pdev->dev, chip, gpio);
  93. if (err)
  94. return err;
  95. dev_info(&pdev->dev, "OCTEON GPIO driver probed.\n");
  96. return 0;
  97. }
  98. static const struct of_device_id octeon_gpio_match[] = {
  99. {
  100. .compatible = "cavium,octeon-3860-gpio",
  101. },
  102. {},
  103. };
  104. MODULE_DEVICE_TABLE(of, octeon_gpio_match);
  105. static struct platform_driver octeon_gpio_driver = {
  106. .driver = {
  107. .name = "octeon_gpio",
  108. .of_match_table = octeon_gpio_match,
  109. },
  110. .probe = octeon_gpio_probe,
  111. };
  112. module_platform_driver(octeon_gpio_driver);
  113. MODULE_DESCRIPTION("Cavium Inc. OCTEON GPIO Driver");
  114. MODULE_AUTHOR("David Daney");
  115. MODULE_LICENSE("GPL");