gpio-mxs.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. //
  3. // MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
  4. // Copyright 2008 Juergen Beisert, kernel@pengutronix.de
  5. //
  6. // Based on code from Freescale,
  7. // Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  8. #include <linux/err.h>
  9. #include <linux/init.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/io.h>
  12. #include <linux/irq.h>
  13. #include <linux/irqdomain.h>
  14. #include <linux/of.h>
  15. #include <linux/of_address.h>
  16. #include <linux/of_device.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/slab.h>
  19. #include <linux/gpio/driver.h>
  20. #include <linux/module.h>
  21. #define MXS_SET 0x4
  22. #define MXS_CLR 0x8
  23. #define PINCTRL_DOUT(p) ((is_imx23_gpio(p) ? 0x0500 : 0x0700) + (p->id) * 0x10)
  24. #define PINCTRL_DIN(p) ((is_imx23_gpio(p) ? 0x0600 : 0x0900) + (p->id) * 0x10)
  25. #define PINCTRL_DOE(p) ((is_imx23_gpio(p) ? 0x0700 : 0x0b00) + (p->id) * 0x10)
  26. #define PINCTRL_PIN2IRQ(p) ((is_imx23_gpio(p) ? 0x0800 : 0x1000) + (p->id) * 0x10)
  27. #define PINCTRL_IRQEN(p) ((is_imx23_gpio(p) ? 0x0900 : 0x1100) + (p->id) * 0x10)
  28. #define PINCTRL_IRQLEV(p) ((is_imx23_gpio(p) ? 0x0a00 : 0x1200) + (p->id) * 0x10)
  29. #define PINCTRL_IRQPOL(p) ((is_imx23_gpio(p) ? 0x0b00 : 0x1300) + (p->id) * 0x10)
  30. #define PINCTRL_IRQSTAT(p) ((is_imx23_gpio(p) ? 0x0c00 : 0x1400) + (p->id) * 0x10)
  31. #define GPIO_INT_FALL_EDGE 0x0
  32. #define GPIO_INT_LOW_LEV 0x1
  33. #define GPIO_INT_RISE_EDGE 0x2
  34. #define GPIO_INT_HIGH_LEV 0x3
  35. #define GPIO_INT_LEV_MASK (1 << 0)
  36. #define GPIO_INT_POL_MASK (1 << 1)
  37. enum mxs_gpio_id {
  38. IMX23_GPIO,
  39. IMX28_GPIO,
  40. };
  41. struct mxs_gpio_port {
  42. void __iomem *base;
  43. int id;
  44. int irq;
  45. struct irq_domain *domain;
  46. struct gpio_chip gc;
  47. struct device *dev;
  48. enum mxs_gpio_id devid;
  49. u32 both_edges;
  50. };
  51. static inline int is_imx23_gpio(struct mxs_gpio_port *port)
  52. {
  53. return port->devid == IMX23_GPIO;
  54. }
  55. static inline int is_imx28_gpio(struct mxs_gpio_port *port)
  56. {
  57. return port->devid == IMX28_GPIO;
  58. }
  59. /* Note: This driver assumes 32 GPIOs are handled in one register */
  60. static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
  61. {
  62. u32 val;
  63. u32 pin_mask = 1 << d->hwirq;
  64. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  65. struct irq_chip_type *ct = irq_data_get_chip_type(d);
  66. struct mxs_gpio_port *port = gc->private;
  67. void __iomem *pin_addr;
  68. int edge;
  69. if (!(ct->type & type))
  70. if (irq_setup_alt_chip(d, type))
  71. return -EINVAL;
  72. port->both_edges &= ~pin_mask;
  73. switch (type) {
  74. case IRQ_TYPE_EDGE_BOTH:
  75. val = readl(port->base + PINCTRL_DIN(port)) & pin_mask;
  76. if (val)
  77. edge = GPIO_INT_FALL_EDGE;
  78. else
  79. edge = GPIO_INT_RISE_EDGE;
  80. port->both_edges |= pin_mask;
  81. break;
  82. case IRQ_TYPE_EDGE_RISING:
  83. edge = GPIO_INT_RISE_EDGE;
  84. break;
  85. case IRQ_TYPE_EDGE_FALLING:
  86. edge = GPIO_INT_FALL_EDGE;
  87. break;
  88. case IRQ_TYPE_LEVEL_LOW:
  89. edge = GPIO_INT_LOW_LEV;
  90. break;
  91. case IRQ_TYPE_LEVEL_HIGH:
  92. edge = GPIO_INT_HIGH_LEV;
  93. break;
  94. default:
  95. return -EINVAL;
  96. }
  97. /* set level or edge */
  98. pin_addr = port->base + PINCTRL_IRQLEV(port);
  99. if (edge & GPIO_INT_LEV_MASK) {
  100. writel(pin_mask, pin_addr + MXS_SET);
  101. writel(pin_mask, port->base + PINCTRL_IRQEN(port) + MXS_SET);
  102. } else {
  103. writel(pin_mask, pin_addr + MXS_CLR);
  104. writel(pin_mask, port->base + PINCTRL_PIN2IRQ(port) + MXS_SET);
  105. }
  106. /* set polarity */
  107. pin_addr = port->base + PINCTRL_IRQPOL(port);
  108. if (edge & GPIO_INT_POL_MASK)
  109. writel(pin_mask, pin_addr + MXS_SET);
  110. else
  111. writel(pin_mask, pin_addr + MXS_CLR);
  112. writel(pin_mask, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
  113. return 0;
  114. }
  115. static void mxs_flip_edge(struct mxs_gpio_port *port, u32 gpio)
  116. {
  117. u32 bit, val, edge;
  118. void __iomem *pin_addr;
  119. bit = 1 << gpio;
  120. pin_addr = port->base + PINCTRL_IRQPOL(port);
  121. val = readl(pin_addr);
  122. edge = val & bit;
  123. if (edge)
  124. writel(bit, pin_addr + MXS_CLR);
  125. else
  126. writel(bit, pin_addr + MXS_SET);
  127. }
  128. /* MXS has one interrupt *per* gpio port */
  129. static void mxs_gpio_irq_handler(struct irq_desc *desc)
  130. {
  131. u32 irq_stat;
  132. struct mxs_gpio_port *port = irq_desc_get_handler_data(desc);
  133. desc->irq_data.chip->irq_ack(&desc->irq_data);
  134. irq_stat = readl(port->base + PINCTRL_IRQSTAT(port)) &
  135. readl(port->base + PINCTRL_IRQEN(port));
  136. while (irq_stat != 0) {
  137. int irqoffset = fls(irq_stat) - 1;
  138. if (port->both_edges & (1 << irqoffset))
  139. mxs_flip_edge(port, irqoffset);
  140. generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
  141. irq_stat &= ~(1 << irqoffset);
  142. }
  143. }
  144. /*
  145. * Set interrupt number "irq" in the GPIO as a wake-up source.
  146. * While system is running, all registered GPIO interrupts need to have
  147. * wake-up enabled. When system is suspended, only selected GPIO interrupts
  148. * need to have wake-up enabled.
  149. * @param irq interrupt source number
  150. * @param enable enable as wake-up if equal to non-zero
  151. * @return This function returns 0 on success.
  152. */
  153. static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
  154. {
  155. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  156. struct mxs_gpio_port *port = gc->private;
  157. if (enable)
  158. enable_irq_wake(port->irq);
  159. else
  160. disable_irq_wake(port->irq);
  161. return 0;
  162. }
  163. static int mxs_gpio_init_gc(struct mxs_gpio_port *port, int irq_base)
  164. {
  165. struct irq_chip_generic *gc;
  166. struct irq_chip_type *ct;
  167. int rv;
  168. gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxs", 2, irq_base,
  169. port->base, handle_level_irq);
  170. if (!gc)
  171. return -ENOMEM;
  172. gc->private = port;
  173. ct = &gc->chip_types[0];
  174. ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
  175. ct->chip.irq_ack = irq_gc_ack_set_bit;
  176. ct->chip.irq_mask = irq_gc_mask_disable_reg;
  177. ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
  178. ct->chip.irq_set_type = mxs_gpio_set_irq_type;
  179. ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
  180. ct->chip.flags = IRQCHIP_SET_TYPE_MASKED;
  181. ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
  182. ct->regs.enable = PINCTRL_PIN2IRQ(port) + MXS_SET;
  183. ct->regs.disable = PINCTRL_PIN2IRQ(port) + MXS_CLR;
  184. ct = &gc->chip_types[1];
  185. ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
  186. ct->chip.irq_ack = irq_gc_ack_set_bit;
  187. ct->chip.irq_mask = irq_gc_mask_disable_reg;
  188. ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
  189. ct->chip.irq_set_type = mxs_gpio_set_irq_type;
  190. ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
  191. ct->chip.flags = IRQCHIP_SET_TYPE_MASKED;
  192. ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
  193. ct->regs.enable = PINCTRL_IRQEN(port) + MXS_SET;
  194. ct->regs.disable = PINCTRL_IRQEN(port) + MXS_CLR;
  195. ct->handler = handle_level_irq;
  196. rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32),
  197. IRQ_GC_INIT_NESTED_LOCK,
  198. IRQ_NOREQUEST, 0);
  199. return rv;
  200. }
  201. static int mxs_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
  202. {
  203. struct mxs_gpio_port *port = gpiochip_get_data(gc);
  204. return irq_find_mapping(port->domain, offset);
  205. }
  206. static int mxs_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
  207. {
  208. struct mxs_gpio_port *port = gpiochip_get_data(gc);
  209. u32 mask = 1 << offset;
  210. u32 dir;
  211. dir = readl(port->base + PINCTRL_DOE(port));
  212. if (dir & mask)
  213. return GPIO_LINE_DIRECTION_OUT;
  214. return GPIO_LINE_DIRECTION_IN;
  215. }
  216. static const struct platform_device_id mxs_gpio_ids[] = {
  217. {
  218. .name = "imx23-gpio",
  219. .driver_data = IMX23_GPIO,
  220. }, {
  221. .name = "imx28-gpio",
  222. .driver_data = IMX28_GPIO,
  223. }, {
  224. /* sentinel */
  225. }
  226. };
  227. MODULE_DEVICE_TABLE(platform, mxs_gpio_ids);
  228. static const struct of_device_id mxs_gpio_dt_ids[] = {
  229. { .compatible = "fsl,imx23-gpio", .data = (void *) IMX23_GPIO, },
  230. { .compatible = "fsl,imx28-gpio", .data = (void *) IMX28_GPIO, },
  231. { /* sentinel */ }
  232. };
  233. MODULE_DEVICE_TABLE(of, mxs_gpio_dt_ids);
  234. static int mxs_gpio_probe(struct platform_device *pdev)
  235. {
  236. struct device_node *np = pdev->dev.of_node;
  237. struct device_node *parent;
  238. static void __iomem *base;
  239. struct mxs_gpio_port *port;
  240. int irq_base;
  241. int err;
  242. port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
  243. if (!port)
  244. return -ENOMEM;
  245. port->id = of_alias_get_id(np, "gpio");
  246. if (port->id < 0)
  247. return port->id;
  248. port->devid = (enum mxs_gpio_id)of_device_get_match_data(&pdev->dev);
  249. port->dev = &pdev->dev;
  250. port->irq = platform_get_irq(pdev, 0);
  251. if (port->irq < 0)
  252. return port->irq;
  253. /*
  254. * map memory region only once, as all the gpio ports
  255. * share the same one
  256. */
  257. if (!base) {
  258. parent = of_get_parent(np);
  259. base = of_iomap(parent, 0);
  260. of_node_put(parent);
  261. if (!base)
  262. return -EADDRNOTAVAIL;
  263. }
  264. port->base = base;
  265. /* initially disable the interrupts */
  266. writel(0, port->base + PINCTRL_PIN2IRQ(port));
  267. writel(0, port->base + PINCTRL_IRQEN(port));
  268. /* clear address has to be used to clear IRQSTAT bits */
  269. writel(~0U, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
  270. irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 32, numa_node_id());
  271. if (irq_base < 0) {
  272. err = irq_base;
  273. goto out_iounmap;
  274. }
  275. port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
  276. &irq_domain_simple_ops, NULL);
  277. if (!port->domain) {
  278. err = -ENODEV;
  279. goto out_iounmap;
  280. }
  281. /* gpio-mxs can be a generic irq chip */
  282. err = mxs_gpio_init_gc(port, irq_base);
  283. if (err < 0)
  284. goto out_irqdomain_remove;
  285. /* setup one handler for each entry */
  286. irq_set_chained_handler_and_data(port->irq, mxs_gpio_irq_handler,
  287. port);
  288. err = bgpio_init(&port->gc, &pdev->dev, 4,
  289. port->base + PINCTRL_DIN(port),
  290. port->base + PINCTRL_DOUT(port) + MXS_SET,
  291. port->base + PINCTRL_DOUT(port) + MXS_CLR,
  292. port->base + PINCTRL_DOE(port), NULL, 0);
  293. if (err)
  294. goto out_irqdomain_remove;
  295. port->gc.to_irq = mxs_gpio_to_irq;
  296. port->gc.get_direction = mxs_gpio_get_direction;
  297. port->gc.base = port->id * 32;
  298. err = gpiochip_add_data(&port->gc, port);
  299. if (err)
  300. goto out_irqdomain_remove;
  301. return 0;
  302. out_irqdomain_remove:
  303. irq_domain_remove(port->domain);
  304. out_iounmap:
  305. iounmap(port->base);
  306. return err;
  307. }
  308. static struct platform_driver mxs_gpio_driver = {
  309. .driver = {
  310. .name = "gpio-mxs",
  311. .of_match_table = mxs_gpio_dt_ids,
  312. .suppress_bind_attrs = true,
  313. },
  314. .probe = mxs_gpio_probe,
  315. .id_table = mxs_gpio_ids,
  316. };
  317. static int __init mxs_gpio_init(void)
  318. {
  319. return platform_driver_register(&mxs_gpio_driver);
  320. }
  321. postcore_initcall(mxs_gpio_init);
  322. MODULE_AUTHOR("Freescale Semiconductor, "
  323. "Daniel Mack <danielncaiaq.de>, "
  324. "Juergen Beisert <kernel@pengutronix.de>");
  325. MODULE_DESCRIPTION("Freescale MXS GPIO");
  326. MODULE_LICENSE("GPL");