gpio-mxc.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. //
  3. // MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
  4. // Copyright 2008 Juergen Beisert, kernel@pengutronix.de
  5. //
  6. // Based on code from Freescale Semiconductor,
  7. // Authors: Daniel Mack, Juergen Beisert.
  8. // Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  9. #include <linux/clk.h>
  10. #include <linux/err.h>
  11. #include <linux/init.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/io.h>
  14. #include <linux/irq.h>
  15. #include <linux/irqdomain.h>
  16. #include <linux/irqchip/chained_irq.h>
  17. #include <linux/module.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/slab.h>
  20. #include <linux/syscore_ops.h>
  21. #include <linux/gpio/driver.h>
  22. #include <linux/of.h>
  23. #include <linux/of_device.h>
  24. #include <linux/bug.h>
  25. enum mxc_gpio_hwtype {
  26. IMX1_GPIO, /* runs on i.mx1 */
  27. IMX21_GPIO, /* runs on i.mx21 and i.mx27 */
  28. IMX31_GPIO, /* runs on i.mx31 */
  29. IMX35_GPIO, /* runs on all other i.mx */
  30. };
  31. /* device type dependent stuff */
  32. struct mxc_gpio_hwdata {
  33. unsigned dr_reg;
  34. unsigned gdir_reg;
  35. unsigned psr_reg;
  36. unsigned icr1_reg;
  37. unsigned icr2_reg;
  38. unsigned imr_reg;
  39. unsigned isr_reg;
  40. int edge_sel_reg;
  41. unsigned low_level;
  42. unsigned high_level;
  43. unsigned rise_edge;
  44. unsigned fall_edge;
  45. };
  46. struct mxc_gpio_reg_saved {
  47. u32 icr1;
  48. u32 icr2;
  49. u32 imr;
  50. u32 gdir;
  51. u32 edge_sel;
  52. u32 dr;
  53. };
  54. struct mxc_gpio_port {
  55. struct list_head node;
  56. void __iomem *base;
  57. struct clk *clk;
  58. int irq;
  59. int irq_high;
  60. struct irq_domain *domain;
  61. struct gpio_chip gc;
  62. struct device *dev;
  63. u32 both_edges;
  64. struct mxc_gpio_reg_saved gpio_saved_reg;
  65. bool power_off;
  66. };
  67. static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = {
  68. .dr_reg = 0x1c,
  69. .gdir_reg = 0x00,
  70. .psr_reg = 0x24,
  71. .icr1_reg = 0x28,
  72. .icr2_reg = 0x2c,
  73. .imr_reg = 0x30,
  74. .isr_reg = 0x34,
  75. .edge_sel_reg = -EINVAL,
  76. .low_level = 0x03,
  77. .high_level = 0x02,
  78. .rise_edge = 0x00,
  79. .fall_edge = 0x01,
  80. };
  81. static struct mxc_gpio_hwdata imx31_gpio_hwdata = {
  82. .dr_reg = 0x00,
  83. .gdir_reg = 0x04,
  84. .psr_reg = 0x08,
  85. .icr1_reg = 0x0c,
  86. .icr2_reg = 0x10,
  87. .imr_reg = 0x14,
  88. .isr_reg = 0x18,
  89. .edge_sel_reg = -EINVAL,
  90. .low_level = 0x00,
  91. .high_level = 0x01,
  92. .rise_edge = 0x02,
  93. .fall_edge = 0x03,
  94. };
  95. static struct mxc_gpio_hwdata imx35_gpio_hwdata = {
  96. .dr_reg = 0x00,
  97. .gdir_reg = 0x04,
  98. .psr_reg = 0x08,
  99. .icr1_reg = 0x0c,
  100. .icr2_reg = 0x10,
  101. .imr_reg = 0x14,
  102. .isr_reg = 0x18,
  103. .edge_sel_reg = 0x1c,
  104. .low_level = 0x00,
  105. .high_level = 0x01,
  106. .rise_edge = 0x02,
  107. .fall_edge = 0x03,
  108. };
  109. static enum mxc_gpio_hwtype mxc_gpio_hwtype;
  110. static struct mxc_gpio_hwdata *mxc_gpio_hwdata;
  111. #define GPIO_DR (mxc_gpio_hwdata->dr_reg)
  112. #define GPIO_GDIR (mxc_gpio_hwdata->gdir_reg)
  113. #define GPIO_PSR (mxc_gpio_hwdata->psr_reg)
  114. #define GPIO_ICR1 (mxc_gpio_hwdata->icr1_reg)
  115. #define GPIO_ICR2 (mxc_gpio_hwdata->icr2_reg)
  116. #define GPIO_IMR (mxc_gpio_hwdata->imr_reg)
  117. #define GPIO_ISR (mxc_gpio_hwdata->isr_reg)
  118. #define GPIO_EDGE_SEL (mxc_gpio_hwdata->edge_sel_reg)
  119. #define GPIO_INT_LOW_LEV (mxc_gpio_hwdata->low_level)
  120. #define GPIO_INT_HIGH_LEV (mxc_gpio_hwdata->high_level)
  121. #define GPIO_INT_RISE_EDGE (mxc_gpio_hwdata->rise_edge)
  122. #define GPIO_INT_FALL_EDGE (mxc_gpio_hwdata->fall_edge)
  123. #define GPIO_INT_BOTH_EDGES 0x4
  124. static const struct platform_device_id mxc_gpio_devtype[] = {
  125. {
  126. .name = "imx1-gpio",
  127. .driver_data = IMX1_GPIO,
  128. }, {
  129. .name = "imx21-gpio",
  130. .driver_data = IMX21_GPIO,
  131. }, {
  132. .name = "imx31-gpio",
  133. .driver_data = IMX31_GPIO,
  134. }, {
  135. .name = "imx35-gpio",
  136. .driver_data = IMX35_GPIO,
  137. }, {
  138. /* sentinel */
  139. }
  140. };
  141. static const struct of_device_id mxc_gpio_dt_ids[] = {
  142. { .compatible = "fsl,imx1-gpio", .data = &mxc_gpio_devtype[IMX1_GPIO], },
  143. { .compatible = "fsl,imx21-gpio", .data = &mxc_gpio_devtype[IMX21_GPIO], },
  144. { .compatible = "fsl,imx31-gpio", .data = &mxc_gpio_devtype[IMX31_GPIO], },
  145. { .compatible = "fsl,imx35-gpio", .data = &mxc_gpio_devtype[IMX35_GPIO], },
  146. { .compatible = "fsl,imx7d-gpio", .data = &mxc_gpio_devtype[IMX35_GPIO], },
  147. { /* sentinel */ }
  148. };
  149. MODULE_DEVICE_TABLE(of, mxc_gpio_dt_ids);
  150. /*
  151. * MX2 has one interrupt *for all* gpio ports. The list is used
  152. * to save the references to all ports, so that mx2_gpio_irq_handler
  153. * can walk through all interrupt status registers.
  154. */
  155. static LIST_HEAD(mxc_gpio_ports);
  156. /* Note: This driver assumes 32 GPIOs are handled in one register */
  157. static int gpio_set_irq_type(struct irq_data *d, u32 type)
  158. {
  159. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  160. struct mxc_gpio_port *port = gc->private;
  161. u32 bit, val;
  162. u32 gpio_idx = d->hwirq;
  163. int edge;
  164. void __iomem *reg = port->base;
  165. port->both_edges &= ~(1 << gpio_idx);
  166. switch (type) {
  167. case IRQ_TYPE_EDGE_RISING:
  168. edge = GPIO_INT_RISE_EDGE;
  169. break;
  170. case IRQ_TYPE_EDGE_FALLING:
  171. edge = GPIO_INT_FALL_EDGE;
  172. break;
  173. case IRQ_TYPE_EDGE_BOTH:
  174. if (GPIO_EDGE_SEL >= 0) {
  175. edge = GPIO_INT_BOTH_EDGES;
  176. } else {
  177. val = port->gc.get(&port->gc, gpio_idx);
  178. if (val) {
  179. edge = GPIO_INT_LOW_LEV;
  180. pr_debug("mxc: set GPIO %d to low trigger\n", gpio_idx);
  181. } else {
  182. edge = GPIO_INT_HIGH_LEV;
  183. pr_debug("mxc: set GPIO %d to high trigger\n", gpio_idx);
  184. }
  185. port->both_edges |= 1 << gpio_idx;
  186. }
  187. break;
  188. case IRQ_TYPE_LEVEL_LOW:
  189. edge = GPIO_INT_LOW_LEV;
  190. break;
  191. case IRQ_TYPE_LEVEL_HIGH:
  192. edge = GPIO_INT_HIGH_LEV;
  193. break;
  194. default:
  195. return -EINVAL;
  196. }
  197. if (GPIO_EDGE_SEL >= 0) {
  198. val = readl(port->base + GPIO_EDGE_SEL);
  199. if (edge == GPIO_INT_BOTH_EDGES)
  200. writel(val | (1 << gpio_idx),
  201. port->base + GPIO_EDGE_SEL);
  202. else
  203. writel(val & ~(1 << gpio_idx),
  204. port->base + GPIO_EDGE_SEL);
  205. }
  206. if (edge != GPIO_INT_BOTH_EDGES) {
  207. reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper register */
  208. bit = gpio_idx & 0xf;
  209. val = readl(reg) & ~(0x3 << (bit << 1));
  210. writel(val | (edge << (bit << 1)), reg);
  211. }
  212. writel(1 << gpio_idx, port->base + GPIO_ISR);
  213. return 0;
  214. }
  215. static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
  216. {
  217. void __iomem *reg = port->base;
  218. u32 bit, val;
  219. int edge;
  220. reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
  221. bit = gpio & 0xf;
  222. val = readl(reg);
  223. edge = (val >> (bit << 1)) & 3;
  224. val &= ~(0x3 << (bit << 1));
  225. if (edge == GPIO_INT_HIGH_LEV) {
  226. edge = GPIO_INT_LOW_LEV;
  227. pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
  228. } else if (edge == GPIO_INT_LOW_LEV) {
  229. edge = GPIO_INT_HIGH_LEV;
  230. pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
  231. } else {
  232. pr_err("mxc: invalid configuration for GPIO %d: %x\n",
  233. gpio, edge);
  234. return;
  235. }
  236. writel(val | (edge << (bit << 1)), reg);
  237. }
  238. /* handle 32 interrupts in one status register */
  239. static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
  240. {
  241. while (irq_stat != 0) {
  242. int irqoffset = fls(irq_stat) - 1;
  243. if (port->both_edges & (1 << irqoffset))
  244. mxc_flip_edge(port, irqoffset);
  245. generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
  246. irq_stat &= ~(1 << irqoffset);
  247. }
  248. }
  249. /* MX1 and MX3 has one interrupt *per* gpio port */
  250. static void mx3_gpio_irq_handler(struct irq_desc *desc)
  251. {
  252. u32 irq_stat;
  253. struct mxc_gpio_port *port = irq_desc_get_handler_data(desc);
  254. struct irq_chip *chip = irq_desc_get_chip(desc);
  255. chained_irq_enter(chip, desc);
  256. irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR);
  257. mxc_gpio_irq_handler(port, irq_stat);
  258. chained_irq_exit(chip, desc);
  259. }
  260. /* MX2 has one interrupt *for all* gpio ports */
  261. static void mx2_gpio_irq_handler(struct irq_desc *desc)
  262. {
  263. u32 irq_msk, irq_stat;
  264. struct mxc_gpio_port *port;
  265. struct irq_chip *chip = irq_desc_get_chip(desc);
  266. chained_irq_enter(chip, desc);
  267. /* walk through all interrupt status registers */
  268. list_for_each_entry(port, &mxc_gpio_ports, node) {
  269. irq_msk = readl(port->base + GPIO_IMR);
  270. if (!irq_msk)
  271. continue;
  272. irq_stat = readl(port->base + GPIO_ISR) & irq_msk;
  273. if (irq_stat)
  274. mxc_gpio_irq_handler(port, irq_stat);
  275. }
  276. chained_irq_exit(chip, desc);
  277. }
  278. /*
  279. * Set interrupt number "irq" in the GPIO as a wake-up source.
  280. * While system is running, all registered GPIO interrupts need to have
  281. * wake-up enabled. When system is suspended, only selected GPIO interrupts
  282. * need to have wake-up enabled.
  283. * @param irq interrupt source number
  284. * @param enable enable as wake-up if equal to non-zero
  285. * @return This function returns 0 on success.
  286. */
  287. static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
  288. {
  289. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  290. struct mxc_gpio_port *port = gc->private;
  291. u32 gpio_idx = d->hwirq;
  292. int ret;
  293. if (enable) {
  294. if (port->irq_high && (gpio_idx >= 16))
  295. ret = enable_irq_wake(port->irq_high);
  296. else
  297. ret = enable_irq_wake(port->irq);
  298. } else {
  299. if (port->irq_high && (gpio_idx >= 16))
  300. ret = disable_irq_wake(port->irq_high);
  301. else
  302. ret = disable_irq_wake(port->irq);
  303. }
  304. return ret;
  305. }
  306. static int mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base)
  307. {
  308. struct irq_chip_generic *gc;
  309. struct irq_chip_type *ct;
  310. int rv;
  311. gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxc", 1, irq_base,
  312. port->base, handle_level_irq);
  313. if (!gc)
  314. return -ENOMEM;
  315. gc->private = port;
  316. ct = gc->chip_types;
  317. ct->chip.irq_ack = irq_gc_ack_set_bit;
  318. ct->chip.irq_mask = irq_gc_mask_clr_bit;
  319. ct->chip.irq_unmask = irq_gc_mask_set_bit;
  320. ct->chip.irq_set_type = gpio_set_irq_type;
  321. ct->chip.irq_set_wake = gpio_set_wake_irq;
  322. ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND;
  323. ct->regs.ack = GPIO_ISR;
  324. ct->regs.mask = GPIO_IMR;
  325. rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32),
  326. IRQ_GC_INIT_NESTED_LOCK,
  327. IRQ_NOREQUEST, 0);
  328. return rv;
  329. }
  330. static void mxc_gpio_get_hw(struct platform_device *pdev)
  331. {
  332. const struct of_device_id *of_id =
  333. of_match_device(mxc_gpio_dt_ids, &pdev->dev);
  334. enum mxc_gpio_hwtype hwtype;
  335. if (of_id)
  336. pdev->id_entry = of_id->data;
  337. hwtype = pdev->id_entry->driver_data;
  338. if (mxc_gpio_hwtype) {
  339. /*
  340. * The driver works with a reasonable presupposition,
  341. * that is all gpio ports must be the same type when
  342. * running on one soc.
  343. */
  344. BUG_ON(mxc_gpio_hwtype != hwtype);
  345. return;
  346. }
  347. if (hwtype == IMX35_GPIO)
  348. mxc_gpio_hwdata = &imx35_gpio_hwdata;
  349. else if (hwtype == IMX31_GPIO)
  350. mxc_gpio_hwdata = &imx31_gpio_hwdata;
  351. else
  352. mxc_gpio_hwdata = &imx1_imx21_gpio_hwdata;
  353. mxc_gpio_hwtype = hwtype;
  354. }
  355. static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
  356. {
  357. struct mxc_gpio_port *port = gpiochip_get_data(gc);
  358. return irq_find_mapping(port->domain, offset);
  359. }
  360. static int mxc_gpio_probe(struct platform_device *pdev)
  361. {
  362. struct device_node *np = pdev->dev.of_node;
  363. struct mxc_gpio_port *port;
  364. int irq_count;
  365. int irq_base;
  366. int err;
  367. mxc_gpio_get_hw(pdev);
  368. port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
  369. if (!port)
  370. return -ENOMEM;
  371. port->dev = &pdev->dev;
  372. port->base = devm_platform_ioremap_resource(pdev, 0);
  373. if (IS_ERR(port->base))
  374. return PTR_ERR(port->base);
  375. irq_count = platform_irq_count(pdev);
  376. if (irq_count < 0)
  377. return irq_count;
  378. if (irq_count > 1) {
  379. port->irq_high = platform_get_irq(pdev, 1);
  380. if (port->irq_high < 0)
  381. port->irq_high = 0;
  382. }
  383. port->irq = platform_get_irq(pdev, 0);
  384. if (port->irq < 0)
  385. return port->irq;
  386. /* the controller clock is optional */
  387. port->clk = devm_clk_get_optional(&pdev->dev, NULL);
  388. if (IS_ERR(port->clk))
  389. return PTR_ERR(port->clk);
  390. err = clk_prepare_enable(port->clk);
  391. if (err) {
  392. dev_err(&pdev->dev, "Unable to enable clock.\n");
  393. return err;
  394. }
  395. if (of_device_is_compatible(np, "fsl,imx7d-gpio"))
  396. port->power_off = true;
  397. /* disable the interrupt and clear the status */
  398. writel(0, port->base + GPIO_IMR);
  399. writel(~0, port->base + GPIO_ISR);
  400. if (mxc_gpio_hwtype == IMX21_GPIO) {
  401. /*
  402. * Setup one handler for all GPIO interrupts. Actually setting
  403. * the handler is needed only once, but doing it for every port
  404. * is more robust and easier.
  405. */
  406. irq_set_chained_handler(port->irq, mx2_gpio_irq_handler);
  407. } else {
  408. /* setup one handler for each entry */
  409. irq_set_chained_handler_and_data(port->irq,
  410. mx3_gpio_irq_handler, port);
  411. if (port->irq_high > 0)
  412. /* setup handler for GPIO 16 to 31 */
  413. irq_set_chained_handler_and_data(port->irq_high,
  414. mx3_gpio_irq_handler,
  415. port);
  416. }
  417. err = bgpio_init(&port->gc, &pdev->dev, 4,
  418. port->base + GPIO_PSR,
  419. port->base + GPIO_DR, NULL,
  420. port->base + GPIO_GDIR, NULL,
  421. BGPIOF_READ_OUTPUT_REG_SET);
  422. if (err)
  423. goto out_bgio;
  424. port->gc.request = gpiochip_generic_request;
  425. port->gc.free = gpiochip_generic_free;
  426. port->gc.to_irq = mxc_gpio_to_irq;
  427. port->gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 :
  428. pdev->id * 32;
  429. err = devm_gpiochip_add_data(&pdev->dev, &port->gc, port);
  430. if (err)
  431. goto out_bgio;
  432. irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 32, numa_node_id());
  433. if (irq_base < 0) {
  434. err = irq_base;
  435. goto out_bgio;
  436. }
  437. port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
  438. &irq_domain_simple_ops, NULL);
  439. if (!port->domain) {
  440. err = -ENODEV;
  441. goto out_bgio;
  442. }
  443. /* gpio-mxc can be a generic irq chip */
  444. err = mxc_gpio_init_gc(port, irq_base);
  445. if (err < 0)
  446. goto out_irqdomain_remove;
  447. list_add_tail(&port->node, &mxc_gpio_ports);
  448. platform_set_drvdata(pdev, port);
  449. return 0;
  450. out_irqdomain_remove:
  451. irq_domain_remove(port->domain);
  452. out_bgio:
  453. clk_disable_unprepare(port->clk);
  454. dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
  455. return err;
  456. }
  457. static void mxc_gpio_save_regs(struct mxc_gpio_port *port)
  458. {
  459. if (!port->power_off)
  460. return;
  461. port->gpio_saved_reg.icr1 = readl(port->base + GPIO_ICR1);
  462. port->gpio_saved_reg.icr2 = readl(port->base + GPIO_ICR2);
  463. port->gpio_saved_reg.imr = readl(port->base + GPIO_IMR);
  464. port->gpio_saved_reg.gdir = readl(port->base + GPIO_GDIR);
  465. port->gpio_saved_reg.edge_sel = readl(port->base + GPIO_EDGE_SEL);
  466. port->gpio_saved_reg.dr = readl(port->base + GPIO_DR);
  467. }
  468. static void mxc_gpio_restore_regs(struct mxc_gpio_port *port)
  469. {
  470. if (!port->power_off)
  471. return;
  472. writel(port->gpio_saved_reg.icr1, port->base + GPIO_ICR1);
  473. writel(port->gpio_saved_reg.icr2, port->base + GPIO_ICR2);
  474. writel(port->gpio_saved_reg.imr, port->base + GPIO_IMR);
  475. writel(port->gpio_saved_reg.gdir, port->base + GPIO_GDIR);
  476. writel(port->gpio_saved_reg.edge_sel, port->base + GPIO_EDGE_SEL);
  477. writel(port->gpio_saved_reg.dr, port->base + GPIO_DR);
  478. }
  479. static int mxc_gpio_syscore_suspend(void)
  480. {
  481. struct mxc_gpio_port *port;
  482. /* walk through all ports */
  483. list_for_each_entry(port, &mxc_gpio_ports, node) {
  484. mxc_gpio_save_regs(port);
  485. clk_disable_unprepare(port->clk);
  486. }
  487. return 0;
  488. }
  489. static void mxc_gpio_syscore_resume(void)
  490. {
  491. struct mxc_gpio_port *port;
  492. int ret;
  493. /* walk through all ports */
  494. list_for_each_entry(port, &mxc_gpio_ports, node) {
  495. ret = clk_prepare_enable(port->clk);
  496. if (ret) {
  497. pr_err("mxc: failed to enable gpio clock %d\n", ret);
  498. return;
  499. }
  500. mxc_gpio_restore_regs(port);
  501. }
  502. }
  503. static struct syscore_ops mxc_gpio_syscore_ops = {
  504. .suspend = mxc_gpio_syscore_suspend,
  505. .resume = mxc_gpio_syscore_resume,
  506. };
  507. static struct platform_driver mxc_gpio_driver = {
  508. .driver = {
  509. .name = "gpio-mxc",
  510. .of_match_table = mxc_gpio_dt_ids,
  511. .suppress_bind_attrs = true,
  512. },
  513. .probe = mxc_gpio_probe,
  514. .id_table = mxc_gpio_devtype,
  515. };
  516. static int __init gpio_mxc_init(void)
  517. {
  518. register_syscore_ops(&mxc_gpio_syscore_ops);
  519. return platform_driver_register(&mxc_gpio_driver);
  520. }
  521. subsys_initcall(gpio_mxc_init);
  522. MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
  523. MODULE_DESCRIPTION("i.MX GPIO Driver");
  524. MODULE_LICENSE("GPL");