gpio-mvebu.c 33 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279
  1. /*
  2. * GPIO driver for Marvell SoCs
  3. *
  4. * Copyright (C) 2012 Marvell
  5. *
  6. * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  7. * Andrew Lunn <andrew@lunn.ch>
  8. * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
  9. *
  10. * This file is licensed under the terms of the GNU General Public
  11. * License version 2. This program is licensed "as is" without any
  12. * warranty of any kind, whether express or implied.
  13. *
  14. * This driver is a fairly straightforward GPIO driver for the
  15. * complete family of Marvell EBU SoC platforms (Orion, Dove,
  16. * Kirkwood, Discovery, Armada 370/XP). The only complexity of this
  17. * driver is the different register layout that exists between the
  18. * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP
  19. * platforms (MV78200 from the Discovery family and the Armada
  20. * XP). Therefore, this driver handles three variants of the GPIO
  21. * block:
  22. * - the basic variant, called "orion-gpio", with the simplest
  23. * register set. Used on Orion, Dove, Kirkwoord, Armada 370 and
  24. * non-SMP Discovery systems
  25. * - the mv78200 variant for MV78200 Discovery systems. This variant
  26. * turns the edge mask and level mask registers into CPU0 edge
  27. * mask/level mask registers, and adds CPU1 edge mask/level mask
  28. * registers.
  29. * - the armadaxp variant for Armada XP systems. This variant keeps
  30. * the normal cause/edge mask/level mask registers when the global
  31. * interrupts are used, but adds per-CPU cause/edge mask/level mask
  32. * registers n a separate memory area for the per-CPU GPIO
  33. * interrupts.
  34. */
  35. #include <linux/bitops.h>
  36. #include <linux/clk.h>
  37. #include <linux/err.h>
  38. #include <linux/gpio/driver.h>
  39. #include <linux/gpio/consumer.h>
  40. #include <linux/gpio/machine.h>
  41. #include <linux/init.h>
  42. #include <linux/io.h>
  43. #include <linux/irq.h>
  44. #include <linux/irqchip/chained_irq.h>
  45. #include <linux/irqdomain.h>
  46. #include <linux/mfd/syscon.h>
  47. #include <linux/of_device.h>
  48. #include <linux/pinctrl/consumer.h>
  49. #include <linux/platform_device.h>
  50. #include <linux/pwm.h>
  51. #include <linux/regmap.h>
  52. #include <linux/slab.h>
  53. /*
  54. * GPIO unit register offsets.
  55. */
  56. #define GPIO_OUT_OFF 0x0000
  57. #define GPIO_IO_CONF_OFF 0x0004
  58. #define GPIO_BLINK_EN_OFF 0x0008
  59. #define GPIO_IN_POL_OFF 0x000c
  60. #define GPIO_DATA_IN_OFF 0x0010
  61. #define GPIO_EDGE_CAUSE_OFF 0x0014
  62. #define GPIO_EDGE_MASK_OFF 0x0018
  63. #define GPIO_LEVEL_MASK_OFF 0x001c
  64. #define GPIO_BLINK_CNT_SELECT_OFF 0x0020
  65. /*
  66. * PWM register offsets.
  67. */
  68. #define PWM_BLINK_ON_DURATION_OFF 0x0
  69. #define PWM_BLINK_OFF_DURATION_OFF 0x4
  70. /* The MV78200 has per-CPU registers for edge mask and level mask */
  71. #define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18)
  72. #define GPIO_LEVEL_MASK_MV78200_OFF(cpu) ((cpu) ? 0x34 : 0x1C)
  73. /*
  74. * The Armada XP has per-CPU registers for interrupt cause, interrupt
  75. * mask and interrupt level mask. Those are relative to the
  76. * percpu_membase.
  77. */
  78. #define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4)
  79. #define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu) (0x10 + (cpu) * 0x4)
  80. #define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4)
  81. #define MVEBU_GPIO_SOC_VARIANT_ORION 0x1
  82. #define MVEBU_GPIO_SOC_VARIANT_MV78200 0x2
  83. #define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3
  84. #define MVEBU_GPIO_SOC_VARIANT_A8K 0x4
  85. #define MVEBU_MAX_GPIO_PER_BANK 32
  86. struct mvebu_pwm {
  87. void __iomem *membase;
  88. unsigned long clk_rate;
  89. struct gpio_desc *gpiod;
  90. struct pwm_chip chip;
  91. spinlock_t lock;
  92. struct mvebu_gpio_chip *mvchip;
  93. /* Used to preserve GPIO/PWM registers across suspend/resume */
  94. u32 blink_select;
  95. u32 blink_on_duration;
  96. u32 blink_off_duration;
  97. };
  98. struct mvebu_gpio_chip {
  99. struct gpio_chip chip;
  100. struct regmap *regs;
  101. u32 offset;
  102. struct regmap *percpu_regs;
  103. int irqbase;
  104. struct irq_domain *domain;
  105. int soc_variant;
  106. /* Used for PWM support */
  107. struct clk *clk;
  108. struct mvebu_pwm *mvpwm;
  109. /* Used to preserve GPIO registers across suspend/resume */
  110. u32 out_reg;
  111. u32 io_conf_reg;
  112. u32 blink_en_reg;
  113. u32 in_pol_reg;
  114. u32 edge_mask_regs[4];
  115. u32 level_mask_regs[4];
  116. };
  117. /*
  118. * Functions returning addresses of individual registers for a given
  119. * GPIO controller.
  120. */
  121. static void mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip,
  122. struct regmap **map, unsigned int *offset)
  123. {
  124. int cpu;
  125. switch (mvchip->soc_variant) {
  126. case MVEBU_GPIO_SOC_VARIANT_ORION:
  127. case MVEBU_GPIO_SOC_VARIANT_MV78200:
  128. case MVEBU_GPIO_SOC_VARIANT_A8K:
  129. *map = mvchip->regs;
  130. *offset = GPIO_EDGE_CAUSE_OFF + mvchip->offset;
  131. break;
  132. case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
  133. cpu = smp_processor_id();
  134. *map = mvchip->percpu_regs;
  135. *offset = GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu);
  136. break;
  137. default:
  138. BUG();
  139. }
  140. }
  141. static u32
  142. mvebu_gpio_read_edge_cause(struct mvebu_gpio_chip *mvchip)
  143. {
  144. struct regmap *map;
  145. unsigned int offset;
  146. u32 val;
  147. mvebu_gpioreg_edge_cause(mvchip, &map, &offset);
  148. regmap_read(map, offset, &val);
  149. return val;
  150. }
  151. static void
  152. mvebu_gpio_write_edge_cause(struct mvebu_gpio_chip *mvchip, u32 val)
  153. {
  154. struct regmap *map;
  155. unsigned int offset;
  156. mvebu_gpioreg_edge_cause(mvchip, &map, &offset);
  157. regmap_write(map, offset, val);
  158. }
  159. static inline void
  160. mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip,
  161. struct regmap **map, unsigned int *offset)
  162. {
  163. int cpu;
  164. switch (mvchip->soc_variant) {
  165. case MVEBU_GPIO_SOC_VARIANT_ORION:
  166. case MVEBU_GPIO_SOC_VARIANT_A8K:
  167. *map = mvchip->regs;
  168. *offset = GPIO_EDGE_MASK_OFF + mvchip->offset;
  169. break;
  170. case MVEBU_GPIO_SOC_VARIANT_MV78200:
  171. cpu = smp_processor_id();
  172. *map = mvchip->regs;
  173. *offset = GPIO_EDGE_MASK_MV78200_OFF(cpu);
  174. break;
  175. case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
  176. cpu = smp_processor_id();
  177. *map = mvchip->percpu_regs;
  178. *offset = GPIO_EDGE_MASK_ARMADAXP_OFF(cpu);
  179. break;
  180. default:
  181. BUG();
  182. }
  183. }
  184. static u32
  185. mvebu_gpio_read_edge_mask(struct mvebu_gpio_chip *mvchip)
  186. {
  187. struct regmap *map;
  188. unsigned int offset;
  189. u32 val;
  190. mvebu_gpioreg_edge_mask(mvchip, &map, &offset);
  191. regmap_read(map, offset, &val);
  192. return val;
  193. }
  194. static void
  195. mvebu_gpio_write_edge_mask(struct mvebu_gpio_chip *mvchip, u32 val)
  196. {
  197. struct regmap *map;
  198. unsigned int offset;
  199. mvebu_gpioreg_edge_mask(mvchip, &map, &offset);
  200. regmap_write(map, offset, val);
  201. }
  202. static void
  203. mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip,
  204. struct regmap **map, unsigned int *offset)
  205. {
  206. int cpu;
  207. switch (mvchip->soc_variant) {
  208. case MVEBU_GPIO_SOC_VARIANT_ORION:
  209. case MVEBU_GPIO_SOC_VARIANT_A8K:
  210. *map = mvchip->regs;
  211. *offset = GPIO_LEVEL_MASK_OFF + mvchip->offset;
  212. break;
  213. case MVEBU_GPIO_SOC_VARIANT_MV78200:
  214. cpu = smp_processor_id();
  215. *map = mvchip->regs;
  216. *offset = GPIO_LEVEL_MASK_MV78200_OFF(cpu);
  217. break;
  218. case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
  219. cpu = smp_processor_id();
  220. *map = mvchip->percpu_regs;
  221. *offset = GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu);
  222. break;
  223. default:
  224. BUG();
  225. }
  226. }
  227. static u32
  228. mvebu_gpio_read_level_mask(struct mvebu_gpio_chip *mvchip)
  229. {
  230. struct regmap *map;
  231. unsigned int offset;
  232. u32 val;
  233. mvebu_gpioreg_level_mask(mvchip, &map, &offset);
  234. regmap_read(map, offset, &val);
  235. return val;
  236. }
  237. static void
  238. mvebu_gpio_write_level_mask(struct mvebu_gpio_chip *mvchip, u32 val)
  239. {
  240. struct regmap *map;
  241. unsigned int offset;
  242. mvebu_gpioreg_level_mask(mvchip, &map, &offset);
  243. regmap_write(map, offset, val);
  244. }
  245. /*
  246. * Functions returning addresses of individual registers for a given
  247. * PWM controller.
  248. */
  249. static void __iomem *mvebu_pwmreg_blink_on_duration(struct mvebu_pwm *mvpwm)
  250. {
  251. return mvpwm->membase + PWM_BLINK_ON_DURATION_OFF;
  252. }
  253. static void __iomem *mvebu_pwmreg_blink_off_duration(struct mvebu_pwm *mvpwm)
  254. {
  255. return mvpwm->membase + PWM_BLINK_OFF_DURATION_OFF;
  256. }
  257. /*
  258. * Functions implementing the gpio_chip methods
  259. */
  260. static void mvebu_gpio_set(struct gpio_chip *chip, unsigned int pin, int value)
  261. {
  262. struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
  263. regmap_update_bits(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
  264. BIT(pin), value ? BIT(pin) : 0);
  265. }
  266. static int mvebu_gpio_get(struct gpio_chip *chip, unsigned int pin)
  267. {
  268. struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
  269. u32 u;
  270. regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
  271. if (u & BIT(pin)) {
  272. u32 data_in, in_pol;
  273. regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset,
  274. &data_in);
  275. regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
  276. &in_pol);
  277. u = data_in ^ in_pol;
  278. } else {
  279. regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &u);
  280. }
  281. return (u >> pin) & 1;
  282. }
  283. static void mvebu_gpio_blink(struct gpio_chip *chip, unsigned int pin,
  284. int value)
  285. {
  286. struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
  287. regmap_update_bits(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
  288. BIT(pin), value ? BIT(pin) : 0);
  289. }
  290. static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned int pin)
  291. {
  292. struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
  293. int ret;
  294. /*
  295. * Check with the pinctrl driver whether this pin is usable as
  296. * an input GPIO
  297. */
  298. ret = pinctrl_gpio_direction_input(chip->base + pin);
  299. if (ret)
  300. return ret;
  301. regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
  302. BIT(pin), BIT(pin));
  303. return 0;
  304. }
  305. static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned int pin,
  306. int value)
  307. {
  308. struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
  309. int ret;
  310. /*
  311. * Check with the pinctrl driver whether this pin is usable as
  312. * an output GPIO
  313. */
  314. ret = pinctrl_gpio_direction_output(chip->base + pin);
  315. if (ret)
  316. return ret;
  317. mvebu_gpio_blink(chip, pin, 0);
  318. mvebu_gpio_set(chip, pin, value);
  319. regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
  320. BIT(pin), 0);
  321. return 0;
  322. }
  323. static int mvebu_gpio_get_direction(struct gpio_chip *chip, unsigned int pin)
  324. {
  325. struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
  326. u32 u;
  327. regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
  328. if (u & BIT(pin))
  329. return GPIO_LINE_DIRECTION_IN;
  330. return GPIO_LINE_DIRECTION_OUT;
  331. }
  332. static int mvebu_gpio_to_irq(struct gpio_chip *chip, unsigned int pin)
  333. {
  334. struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
  335. return irq_create_mapping(mvchip->domain, pin);
  336. }
  337. /*
  338. * Functions implementing the irq_chip methods
  339. */
  340. static void mvebu_gpio_irq_ack(struct irq_data *d)
  341. {
  342. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  343. struct mvebu_gpio_chip *mvchip = gc->private;
  344. u32 mask = d->mask;
  345. irq_gc_lock(gc);
  346. mvebu_gpio_write_edge_cause(mvchip, ~mask);
  347. irq_gc_unlock(gc);
  348. }
  349. static void mvebu_gpio_edge_irq_mask(struct irq_data *d)
  350. {
  351. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  352. struct mvebu_gpio_chip *mvchip = gc->private;
  353. struct irq_chip_type *ct = irq_data_get_chip_type(d);
  354. u32 mask = d->mask;
  355. irq_gc_lock(gc);
  356. ct->mask_cache_priv &= ~mask;
  357. mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv);
  358. irq_gc_unlock(gc);
  359. }
  360. static void mvebu_gpio_edge_irq_unmask(struct irq_data *d)
  361. {
  362. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  363. struct mvebu_gpio_chip *mvchip = gc->private;
  364. struct irq_chip_type *ct = irq_data_get_chip_type(d);
  365. u32 mask = d->mask;
  366. irq_gc_lock(gc);
  367. mvebu_gpio_write_edge_cause(mvchip, ~mask);
  368. ct->mask_cache_priv |= mask;
  369. mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv);
  370. irq_gc_unlock(gc);
  371. }
  372. static void mvebu_gpio_level_irq_mask(struct irq_data *d)
  373. {
  374. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  375. struct mvebu_gpio_chip *mvchip = gc->private;
  376. struct irq_chip_type *ct = irq_data_get_chip_type(d);
  377. u32 mask = d->mask;
  378. irq_gc_lock(gc);
  379. ct->mask_cache_priv &= ~mask;
  380. mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv);
  381. irq_gc_unlock(gc);
  382. }
  383. static void mvebu_gpio_level_irq_unmask(struct irq_data *d)
  384. {
  385. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  386. struct mvebu_gpio_chip *mvchip = gc->private;
  387. struct irq_chip_type *ct = irq_data_get_chip_type(d);
  388. u32 mask = d->mask;
  389. irq_gc_lock(gc);
  390. ct->mask_cache_priv |= mask;
  391. mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv);
  392. irq_gc_unlock(gc);
  393. }
  394. /*****************************************************************************
  395. * MVEBU GPIO IRQ
  396. *
  397. * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same
  398. * value of the line or the opposite value.
  399. *
  400. * Level IRQ handlers: DATA_IN is used directly as cause register.
  401. * Interrupt are masked by LEVEL_MASK registers.
  402. * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE.
  403. * Interrupt are masked by EDGE_MASK registers.
  404. * Both-edge handlers: Similar to regular Edge handlers, but also swaps
  405. * the polarity to catch the next line transaction.
  406. * This is a race condition that might not perfectly
  407. * work on some use cases.
  408. *
  409. * Every eight GPIO lines are grouped (OR'ed) before going up to main
  410. * cause register.
  411. *
  412. * EDGE cause mask
  413. * data-in /--------| |-----| |----\
  414. * -----| |----- ---- to main cause reg
  415. * X \----------------| |----/
  416. * polarity LEVEL mask
  417. *
  418. ****************************************************************************/
  419. static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type)
  420. {
  421. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  422. struct irq_chip_type *ct = irq_data_get_chip_type(d);
  423. struct mvebu_gpio_chip *mvchip = gc->private;
  424. int pin;
  425. u32 u;
  426. pin = d->hwirq;
  427. regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
  428. if ((u & BIT(pin)) == 0)
  429. return -EINVAL;
  430. type &= IRQ_TYPE_SENSE_MASK;
  431. if (type == IRQ_TYPE_NONE)
  432. return -EINVAL;
  433. /* Check if we need to change chip and handler */
  434. if (!(ct->type & type))
  435. if (irq_setup_alt_chip(d, type))
  436. return -EINVAL;
  437. /*
  438. * Configure interrupt polarity.
  439. */
  440. switch (type) {
  441. case IRQ_TYPE_EDGE_RISING:
  442. case IRQ_TYPE_LEVEL_HIGH:
  443. regmap_update_bits(mvchip->regs,
  444. GPIO_IN_POL_OFF + mvchip->offset,
  445. BIT(pin), 0);
  446. break;
  447. case IRQ_TYPE_EDGE_FALLING:
  448. case IRQ_TYPE_LEVEL_LOW:
  449. regmap_update_bits(mvchip->regs,
  450. GPIO_IN_POL_OFF + mvchip->offset,
  451. BIT(pin), BIT(pin));
  452. break;
  453. case IRQ_TYPE_EDGE_BOTH: {
  454. u32 data_in, in_pol, val;
  455. regmap_read(mvchip->regs,
  456. GPIO_IN_POL_OFF + mvchip->offset, &in_pol);
  457. regmap_read(mvchip->regs,
  458. GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
  459. /*
  460. * set initial polarity based on current input level
  461. */
  462. if ((data_in ^ in_pol) & BIT(pin))
  463. val = BIT(pin); /* falling */
  464. else
  465. val = 0; /* raising */
  466. regmap_update_bits(mvchip->regs,
  467. GPIO_IN_POL_OFF + mvchip->offset,
  468. BIT(pin), val);
  469. break;
  470. }
  471. }
  472. return 0;
  473. }
  474. static void mvebu_gpio_irq_handler(struct irq_desc *desc)
  475. {
  476. struct mvebu_gpio_chip *mvchip = irq_desc_get_handler_data(desc);
  477. struct irq_chip *chip = irq_desc_get_chip(desc);
  478. u32 cause, type, data_in, level_mask, edge_cause, edge_mask;
  479. int i;
  480. if (mvchip == NULL)
  481. return;
  482. chained_irq_enter(chip, desc);
  483. regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
  484. level_mask = mvebu_gpio_read_level_mask(mvchip);
  485. edge_cause = mvebu_gpio_read_edge_cause(mvchip);
  486. edge_mask = mvebu_gpio_read_edge_mask(mvchip);
  487. cause = (data_in & level_mask) | (edge_cause & edge_mask);
  488. for (i = 0; i < mvchip->chip.ngpio; i++) {
  489. int irq;
  490. irq = irq_find_mapping(mvchip->domain, i);
  491. if (!(cause & BIT(i)))
  492. continue;
  493. type = irq_get_trigger_type(irq);
  494. if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
  495. /* Swap polarity (race with GPIO line) */
  496. u32 polarity;
  497. regmap_read(mvchip->regs,
  498. GPIO_IN_POL_OFF + mvchip->offset,
  499. &polarity);
  500. polarity ^= BIT(i);
  501. regmap_write(mvchip->regs,
  502. GPIO_IN_POL_OFF + mvchip->offset,
  503. polarity);
  504. }
  505. generic_handle_irq(irq);
  506. }
  507. chained_irq_exit(chip, desc);
  508. }
  509. /*
  510. * Functions implementing the pwm_chip methods
  511. */
  512. static struct mvebu_pwm *to_mvebu_pwm(struct pwm_chip *chip)
  513. {
  514. return container_of(chip, struct mvebu_pwm, chip);
  515. }
  516. static int mvebu_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
  517. {
  518. struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
  519. struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
  520. struct gpio_desc *desc;
  521. unsigned long flags;
  522. int ret = 0;
  523. spin_lock_irqsave(&mvpwm->lock, flags);
  524. if (mvpwm->gpiod) {
  525. ret = -EBUSY;
  526. } else {
  527. desc = gpiochip_request_own_desc(&mvchip->chip,
  528. pwm->hwpwm, "mvebu-pwm",
  529. GPIO_ACTIVE_HIGH,
  530. GPIOD_OUT_LOW);
  531. if (IS_ERR(desc)) {
  532. ret = PTR_ERR(desc);
  533. goto out;
  534. }
  535. mvpwm->gpiod = desc;
  536. }
  537. out:
  538. spin_unlock_irqrestore(&mvpwm->lock, flags);
  539. return ret;
  540. }
  541. static void mvebu_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
  542. {
  543. struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
  544. unsigned long flags;
  545. spin_lock_irqsave(&mvpwm->lock, flags);
  546. gpiochip_free_own_desc(mvpwm->gpiod);
  547. mvpwm->gpiod = NULL;
  548. spin_unlock_irqrestore(&mvpwm->lock, flags);
  549. }
  550. static void mvebu_pwm_get_state(struct pwm_chip *chip,
  551. struct pwm_device *pwm,
  552. struct pwm_state *state) {
  553. struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
  554. struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
  555. unsigned long long val;
  556. unsigned long flags;
  557. u32 u;
  558. spin_lock_irqsave(&mvpwm->lock, flags);
  559. u = readl_relaxed(mvebu_pwmreg_blink_on_duration(mvpwm));
  560. val = (unsigned long long) u * NSEC_PER_SEC;
  561. do_div(val, mvpwm->clk_rate);
  562. if (val > UINT_MAX)
  563. state->duty_cycle = UINT_MAX;
  564. else if (val)
  565. state->duty_cycle = val;
  566. else
  567. state->duty_cycle = 1;
  568. val = (unsigned long long) u; /* on duration */
  569. /* period = on + off duration */
  570. val += readl_relaxed(mvebu_pwmreg_blink_off_duration(mvpwm));
  571. val *= NSEC_PER_SEC;
  572. do_div(val, mvpwm->clk_rate);
  573. if (val > UINT_MAX)
  574. state->period = UINT_MAX;
  575. else if (val)
  576. state->period = val;
  577. else
  578. state->period = 1;
  579. regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &u);
  580. if (u)
  581. state->enabled = true;
  582. else
  583. state->enabled = false;
  584. spin_unlock_irqrestore(&mvpwm->lock, flags);
  585. }
  586. static int mvebu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
  587. const struct pwm_state *state)
  588. {
  589. struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
  590. struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
  591. unsigned long long val;
  592. unsigned long flags;
  593. unsigned int on, off;
  594. val = (unsigned long long) mvpwm->clk_rate * state->duty_cycle;
  595. do_div(val, NSEC_PER_SEC);
  596. if (val > UINT_MAX)
  597. return -EINVAL;
  598. if (val)
  599. on = val;
  600. else
  601. on = 1;
  602. val = (unsigned long long) mvpwm->clk_rate *
  603. (state->period - state->duty_cycle);
  604. do_div(val, NSEC_PER_SEC);
  605. if (val > UINT_MAX)
  606. return -EINVAL;
  607. if (val)
  608. off = val;
  609. else
  610. off = 1;
  611. spin_lock_irqsave(&mvpwm->lock, flags);
  612. writel_relaxed(on, mvebu_pwmreg_blink_on_duration(mvpwm));
  613. writel_relaxed(off, mvebu_pwmreg_blink_off_duration(mvpwm));
  614. if (state->enabled)
  615. mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 1);
  616. else
  617. mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 0);
  618. spin_unlock_irqrestore(&mvpwm->lock, flags);
  619. return 0;
  620. }
  621. static const struct pwm_ops mvebu_pwm_ops = {
  622. .request = mvebu_pwm_request,
  623. .free = mvebu_pwm_free,
  624. .get_state = mvebu_pwm_get_state,
  625. .apply = mvebu_pwm_apply,
  626. .owner = THIS_MODULE,
  627. };
  628. static void __maybe_unused mvebu_pwm_suspend(struct mvebu_gpio_chip *mvchip)
  629. {
  630. struct mvebu_pwm *mvpwm = mvchip->mvpwm;
  631. regmap_read(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
  632. &mvpwm->blink_select);
  633. mvpwm->blink_on_duration =
  634. readl_relaxed(mvebu_pwmreg_blink_on_duration(mvpwm));
  635. mvpwm->blink_off_duration =
  636. readl_relaxed(mvebu_pwmreg_blink_off_duration(mvpwm));
  637. }
  638. static void __maybe_unused mvebu_pwm_resume(struct mvebu_gpio_chip *mvchip)
  639. {
  640. struct mvebu_pwm *mvpwm = mvchip->mvpwm;
  641. regmap_write(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
  642. mvpwm->blink_select);
  643. writel_relaxed(mvpwm->blink_on_duration,
  644. mvebu_pwmreg_blink_on_duration(mvpwm));
  645. writel_relaxed(mvpwm->blink_off_duration,
  646. mvebu_pwmreg_blink_off_duration(mvpwm));
  647. }
  648. static int mvebu_pwm_probe(struct platform_device *pdev,
  649. struct mvebu_gpio_chip *mvchip,
  650. int id)
  651. {
  652. struct device *dev = &pdev->dev;
  653. struct mvebu_pwm *mvpwm;
  654. u32 set;
  655. if (!of_device_is_compatible(mvchip->chip.of_node,
  656. "marvell,armada-370-gpio"))
  657. return 0;
  658. /*
  659. * There are only two sets of PWM configuration registers for
  660. * all the GPIO lines on those SoCs which this driver reserves
  661. * for the first two GPIO chips. So if the resource is missing
  662. * we can't treat it as an error.
  663. */
  664. if (!platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwm"))
  665. return 0;
  666. if (IS_ERR(mvchip->clk))
  667. return PTR_ERR(mvchip->clk);
  668. /*
  669. * Use set A for lines of GPIO chip with id 0, B for GPIO chip
  670. * with id 1. Don't allow further GPIO chips to be used for PWM.
  671. */
  672. if (id == 0)
  673. set = 0;
  674. else if (id == 1)
  675. set = U32_MAX;
  676. else
  677. return -EINVAL;
  678. regmap_write(mvchip->regs,
  679. GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, set);
  680. mvpwm = devm_kzalloc(dev, sizeof(struct mvebu_pwm), GFP_KERNEL);
  681. if (!mvpwm)
  682. return -ENOMEM;
  683. mvchip->mvpwm = mvpwm;
  684. mvpwm->mvchip = mvchip;
  685. mvpwm->membase = devm_platform_ioremap_resource_byname(pdev, "pwm");
  686. if (IS_ERR(mvpwm->membase))
  687. return PTR_ERR(mvpwm->membase);
  688. mvpwm->clk_rate = clk_get_rate(mvchip->clk);
  689. if (!mvpwm->clk_rate) {
  690. dev_err(dev, "failed to get clock rate\n");
  691. return -EINVAL;
  692. }
  693. mvpwm->chip.dev = dev;
  694. mvpwm->chip.ops = &mvebu_pwm_ops;
  695. mvpwm->chip.npwm = mvchip->chip.ngpio;
  696. /*
  697. * There may already be some PWM allocated, so we can't force
  698. * mvpwm->chip.base to a fixed point like mvchip->chip.base.
  699. * So, we let pwmchip_add() do the numbering and take the next free
  700. * region.
  701. */
  702. mvpwm->chip.base = -1;
  703. spin_lock_init(&mvpwm->lock);
  704. return pwmchip_add(&mvpwm->chip);
  705. }
  706. #ifdef CONFIG_DEBUG_FS
  707. #include <linux/seq_file.h>
  708. static void mvebu_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
  709. {
  710. struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
  711. u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk;
  712. const char *label;
  713. int i;
  714. regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &out);
  715. regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &io_conf);
  716. regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &blink);
  717. regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, &in_pol);
  718. regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
  719. cause = mvebu_gpio_read_edge_cause(mvchip);
  720. edg_msk = mvebu_gpio_read_edge_mask(mvchip);
  721. lvl_msk = mvebu_gpio_read_level_mask(mvchip);
  722. for_each_requested_gpio(chip, i, label) {
  723. u32 msk;
  724. bool is_out;
  725. msk = BIT(i);
  726. is_out = !(io_conf & msk);
  727. seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label);
  728. if (is_out) {
  729. seq_printf(s, " out %s %s\n",
  730. out & msk ? "hi" : "lo",
  731. blink & msk ? "(blink )" : "");
  732. continue;
  733. }
  734. seq_printf(s, " in %s (act %s) - IRQ",
  735. (data_in ^ in_pol) & msk ? "hi" : "lo",
  736. in_pol & msk ? "lo" : "hi");
  737. if (!((edg_msk | lvl_msk) & msk)) {
  738. seq_puts(s, " disabled\n");
  739. continue;
  740. }
  741. if (edg_msk & msk)
  742. seq_puts(s, " edge ");
  743. if (lvl_msk & msk)
  744. seq_puts(s, " level");
  745. seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear ");
  746. }
  747. }
  748. #else
  749. #define mvebu_gpio_dbg_show NULL
  750. #endif
  751. static const struct of_device_id mvebu_gpio_of_match[] = {
  752. {
  753. .compatible = "marvell,orion-gpio",
  754. .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION,
  755. },
  756. {
  757. .compatible = "marvell,mv78200-gpio",
  758. .data = (void *) MVEBU_GPIO_SOC_VARIANT_MV78200,
  759. },
  760. {
  761. .compatible = "marvell,armadaxp-gpio",
  762. .data = (void *) MVEBU_GPIO_SOC_VARIANT_ARMADAXP,
  763. },
  764. {
  765. .compatible = "marvell,armada-370-gpio",
  766. .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION,
  767. },
  768. {
  769. .compatible = "marvell,armada-8k-gpio",
  770. .data = (void *) MVEBU_GPIO_SOC_VARIANT_A8K,
  771. },
  772. {
  773. /* sentinel */
  774. },
  775. };
  776. static int mvebu_gpio_suspend(struct platform_device *pdev, pm_message_t state)
  777. {
  778. struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
  779. int i;
  780. regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
  781. &mvchip->out_reg);
  782. regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
  783. &mvchip->io_conf_reg);
  784. regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
  785. &mvchip->blink_en_reg);
  786. regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
  787. &mvchip->in_pol_reg);
  788. switch (mvchip->soc_variant) {
  789. case MVEBU_GPIO_SOC_VARIANT_ORION:
  790. case MVEBU_GPIO_SOC_VARIANT_A8K:
  791. regmap_read(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset,
  792. &mvchip->edge_mask_regs[0]);
  793. regmap_read(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset,
  794. &mvchip->level_mask_regs[0]);
  795. break;
  796. case MVEBU_GPIO_SOC_VARIANT_MV78200:
  797. for (i = 0; i < 2; i++) {
  798. regmap_read(mvchip->regs,
  799. GPIO_EDGE_MASK_MV78200_OFF(i),
  800. &mvchip->edge_mask_regs[i]);
  801. regmap_read(mvchip->regs,
  802. GPIO_LEVEL_MASK_MV78200_OFF(i),
  803. &mvchip->level_mask_regs[i]);
  804. }
  805. break;
  806. case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
  807. for (i = 0; i < 4; i++) {
  808. regmap_read(mvchip->regs,
  809. GPIO_EDGE_MASK_ARMADAXP_OFF(i),
  810. &mvchip->edge_mask_regs[i]);
  811. regmap_read(mvchip->regs,
  812. GPIO_LEVEL_MASK_ARMADAXP_OFF(i),
  813. &mvchip->level_mask_regs[i]);
  814. }
  815. break;
  816. default:
  817. BUG();
  818. }
  819. if (IS_ENABLED(CONFIG_PWM))
  820. mvebu_pwm_suspend(mvchip);
  821. return 0;
  822. }
  823. static int mvebu_gpio_resume(struct platform_device *pdev)
  824. {
  825. struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
  826. int i;
  827. regmap_write(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
  828. mvchip->out_reg);
  829. regmap_write(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
  830. mvchip->io_conf_reg);
  831. regmap_write(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
  832. mvchip->blink_en_reg);
  833. regmap_write(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
  834. mvchip->in_pol_reg);
  835. switch (mvchip->soc_variant) {
  836. case MVEBU_GPIO_SOC_VARIANT_ORION:
  837. case MVEBU_GPIO_SOC_VARIANT_A8K:
  838. regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset,
  839. mvchip->edge_mask_regs[0]);
  840. regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset,
  841. mvchip->level_mask_regs[0]);
  842. break;
  843. case MVEBU_GPIO_SOC_VARIANT_MV78200:
  844. for (i = 0; i < 2; i++) {
  845. regmap_write(mvchip->regs,
  846. GPIO_EDGE_MASK_MV78200_OFF(i),
  847. mvchip->edge_mask_regs[i]);
  848. regmap_write(mvchip->regs,
  849. GPIO_LEVEL_MASK_MV78200_OFF(i),
  850. mvchip->level_mask_regs[i]);
  851. }
  852. break;
  853. case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
  854. for (i = 0; i < 4; i++) {
  855. regmap_write(mvchip->regs,
  856. GPIO_EDGE_MASK_ARMADAXP_OFF(i),
  857. mvchip->edge_mask_regs[i]);
  858. regmap_write(mvchip->regs,
  859. GPIO_LEVEL_MASK_ARMADAXP_OFF(i),
  860. mvchip->level_mask_regs[i]);
  861. }
  862. break;
  863. default:
  864. BUG();
  865. }
  866. if (IS_ENABLED(CONFIG_PWM))
  867. mvebu_pwm_resume(mvchip);
  868. return 0;
  869. }
  870. static const struct regmap_config mvebu_gpio_regmap_config = {
  871. .reg_bits = 32,
  872. .reg_stride = 4,
  873. .val_bits = 32,
  874. .fast_io = true,
  875. };
  876. static int mvebu_gpio_probe_raw(struct platform_device *pdev,
  877. struct mvebu_gpio_chip *mvchip)
  878. {
  879. void __iomem *base;
  880. base = devm_platform_ioremap_resource(pdev, 0);
  881. if (IS_ERR(base))
  882. return PTR_ERR(base);
  883. mvchip->regs = devm_regmap_init_mmio(&pdev->dev, base,
  884. &mvebu_gpio_regmap_config);
  885. if (IS_ERR(mvchip->regs))
  886. return PTR_ERR(mvchip->regs);
  887. /*
  888. * For the legacy SoCs, the regmap directly maps to the GPIO
  889. * registers, so no offset is needed.
  890. */
  891. mvchip->offset = 0;
  892. /*
  893. * The Armada XP has a second range of registers for the
  894. * per-CPU registers
  895. */
  896. if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) {
  897. base = devm_platform_ioremap_resource(pdev, 1);
  898. if (IS_ERR(base))
  899. return PTR_ERR(base);
  900. mvchip->percpu_regs =
  901. devm_regmap_init_mmio(&pdev->dev, base,
  902. &mvebu_gpio_regmap_config);
  903. if (IS_ERR(mvchip->percpu_regs))
  904. return PTR_ERR(mvchip->percpu_regs);
  905. }
  906. return 0;
  907. }
  908. static int mvebu_gpio_probe_syscon(struct platform_device *pdev,
  909. struct mvebu_gpio_chip *mvchip)
  910. {
  911. mvchip->regs = syscon_node_to_regmap(pdev->dev.parent->of_node);
  912. if (IS_ERR(mvchip->regs))
  913. return PTR_ERR(mvchip->regs);
  914. if (of_property_read_u32(pdev->dev.of_node, "offset", &mvchip->offset))
  915. return -EINVAL;
  916. return 0;
  917. }
  918. static int mvebu_gpio_probe(struct platform_device *pdev)
  919. {
  920. struct mvebu_gpio_chip *mvchip;
  921. const struct of_device_id *match;
  922. struct device_node *np = pdev->dev.of_node;
  923. struct irq_chip_generic *gc;
  924. struct irq_chip_type *ct;
  925. unsigned int ngpios;
  926. bool have_irqs;
  927. int soc_variant;
  928. int i, cpu, id;
  929. int err;
  930. match = of_match_device(mvebu_gpio_of_match, &pdev->dev);
  931. if (match)
  932. soc_variant = (unsigned long) match->data;
  933. else
  934. soc_variant = MVEBU_GPIO_SOC_VARIANT_ORION;
  935. /* Some gpio controllers do not provide irq support */
  936. err = platform_irq_count(pdev);
  937. if (err < 0)
  938. return err;
  939. have_irqs = err != 0;
  940. mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip),
  941. GFP_KERNEL);
  942. if (!mvchip)
  943. return -ENOMEM;
  944. platform_set_drvdata(pdev, mvchip);
  945. if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) {
  946. dev_err(&pdev->dev, "Missing ngpios OF property\n");
  947. return -ENODEV;
  948. }
  949. id = of_alias_get_id(pdev->dev.of_node, "gpio");
  950. if (id < 0) {
  951. dev_err(&pdev->dev, "Couldn't get OF id\n");
  952. return id;
  953. }
  954. mvchip->clk = devm_clk_get(&pdev->dev, NULL);
  955. /* Not all SoCs require a clock.*/
  956. if (!IS_ERR(mvchip->clk))
  957. clk_prepare_enable(mvchip->clk);
  958. mvchip->soc_variant = soc_variant;
  959. mvchip->chip.label = dev_name(&pdev->dev);
  960. mvchip->chip.parent = &pdev->dev;
  961. mvchip->chip.request = gpiochip_generic_request;
  962. mvchip->chip.free = gpiochip_generic_free;
  963. mvchip->chip.get_direction = mvebu_gpio_get_direction;
  964. mvchip->chip.direction_input = mvebu_gpio_direction_input;
  965. mvchip->chip.get = mvebu_gpio_get;
  966. mvchip->chip.direction_output = mvebu_gpio_direction_output;
  967. mvchip->chip.set = mvebu_gpio_set;
  968. if (have_irqs)
  969. mvchip->chip.to_irq = mvebu_gpio_to_irq;
  970. mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK;
  971. mvchip->chip.ngpio = ngpios;
  972. mvchip->chip.can_sleep = false;
  973. mvchip->chip.of_node = np;
  974. mvchip->chip.dbg_show = mvebu_gpio_dbg_show;
  975. if (soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K)
  976. err = mvebu_gpio_probe_syscon(pdev, mvchip);
  977. else
  978. err = mvebu_gpio_probe_raw(pdev, mvchip);
  979. if (err)
  980. return err;
  981. /*
  982. * Mask and clear GPIO interrupts.
  983. */
  984. switch (soc_variant) {
  985. case MVEBU_GPIO_SOC_VARIANT_ORION:
  986. case MVEBU_GPIO_SOC_VARIANT_A8K:
  987. regmap_write(mvchip->regs,
  988. GPIO_EDGE_CAUSE_OFF + mvchip->offset, 0);
  989. regmap_write(mvchip->regs,
  990. GPIO_EDGE_MASK_OFF + mvchip->offset, 0);
  991. regmap_write(mvchip->regs,
  992. GPIO_LEVEL_MASK_OFF + mvchip->offset, 0);
  993. break;
  994. case MVEBU_GPIO_SOC_VARIANT_MV78200:
  995. regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0);
  996. for (cpu = 0; cpu < 2; cpu++) {
  997. regmap_write(mvchip->regs,
  998. GPIO_EDGE_MASK_MV78200_OFF(cpu), 0);
  999. regmap_write(mvchip->regs,
  1000. GPIO_LEVEL_MASK_MV78200_OFF(cpu), 0);
  1001. }
  1002. break;
  1003. case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
  1004. regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0);
  1005. regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF, 0);
  1006. regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF, 0);
  1007. for (cpu = 0; cpu < 4; cpu++) {
  1008. regmap_write(mvchip->percpu_regs,
  1009. GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu), 0);
  1010. regmap_write(mvchip->percpu_regs,
  1011. GPIO_EDGE_MASK_ARMADAXP_OFF(cpu), 0);
  1012. regmap_write(mvchip->percpu_regs,
  1013. GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu), 0);
  1014. }
  1015. break;
  1016. default:
  1017. BUG();
  1018. }
  1019. devm_gpiochip_add_data(&pdev->dev, &mvchip->chip, mvchip);
  1020. /* Some MVEBU SoCs have simple PWM support for GPIO lines */
  1021. if (IS_ENABLED(CONFIG_PWM)) {
  1022. err = mvebu_pwm_probe(pdev, mvchip, id);
  1023. if (err)
  1024. return err;
  1025. }
  1026. /* Some gpio controllers do not provide irq support */
  1027. if (!have_irqs)
  1028. return 0;
  1029. mvchip->domain =
  1030. irq_domain_add_linear(np, ngpios, &irq_generic_chip_ops, NULL);
  1031. if (!mvchip->domain) {
  1032. dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n",
  1033. mvchip->chip.label);
  1034. err = -ENODEV;
  1035. goto err_pwm;
  1036. }
  1037. err = irq_alloc_domain_generic_chips(
  1038. mvchip->domain, ngpios, 2, np->name, handle_level_irq,
  1039. IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_LEVEL, 0, 0);
  1040. if (err) {
  1041. dev_err(&pdev->dev, "couldn't allocate irq chips %s (DT).\n",
  1042. mvchip->chip.label);
  1043. goto err_domain;
  1044. }
  1045. /*
  1046. * NOTE: The common accessors cannot be used because of the percpu
  1047. * access to the mask registers
  1048. */
  1049. gc = irq_get_domain_generic_chip(mvchip->domain, 0);
  1050. gc->private = mvchip;
  1051. ct = &gc->chip_types[0];
  1052. ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
  1053. ct->chip.irq_mask = mvebu_gpio_level_irq_mask;
  1054. ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask;
  1055. ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
  1056. ct->chip.name = mvchip->chip.label;
  1057. ct = &gc->chip_types[1];
  1058. ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
  1059. ct->chip.irq_ack = mvebu_gpio_irq_ack;
  1060. ct->chip.irq_mask = mvebu_gpio_edge_irq_mask;
  1061. ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask;
  1062. ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
  1063. ct->handler = handle_edge_irq;
  1064. ct->chip.name = mvchip->chip.label;
  1065. /*
  1066. * Setup the interrupt handlers. Each chip can have up to 4
  1067. * interrupt handlers, with each handler dealing with 8 GPIO
  1068. * pins.
  1069. */
  1070. for (i = 0; i < 4; i++) {
  1071. int irq = platform_get_irq_optional(pdev, i);
  1072. if (irq < 0)
  1073. continue;
  1074. irq_set_chained_handler_and_data(irq, mvebu_gpio_irq_handler,
  1075. mvchip);
  1076. }
  1077. return 0;
  1078. err_domain:
  1079. irq_domain_remove(mvchip->domain);
  1080. err_pwm:
  1081. pwmchip_remove(&mvchip->mvpwm->chip);
  1082. return err;
  1083. }
  1084. static struct platform_driver mvebu_gpio_driver = {
  1085. .driver = {
  1086. .name = "mvebu-gpio",
  1087. .of_match_table = mvebu_gpio_of_match,
  1088. },
  1089. .probe = mvebu_gpio_probe,
  1090. .suspend = mvebu_gpio_suspend,
  1091. .resume = mvebu_gpio_resume,
  1092. };
  1093. builtin_platform_driver(mvebu_gpio_driver);