gpio-msic.c 7.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Intel Medfield MSIC GPIO driver>
  4. * Copyright (c) 2011, Intel Corporation.
  5. *
  6. * Author: Mathias Nyman <mathias.nyman@linux.intel.com>
  7. * Based on intel_pmic_gpio.c
  8. */
  9. #include <linux/gpio/driver.h>
  10. #include <linux/init.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/kernel.h>
  13. #include <linux/mfd/intel_msic.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/slab.h>
  16. /* the offset for the mapping of global gpio pin to irq */
  17. #define MSIC_GPIO_IRQ_OFFSET 0x100
  18. #define MSIC_GPIO_DIR_IN 0
  19. #define MSIC_GPIO_DIR_OUT BIT(5)
  20. #define MSIC_GPIO_TRIG_FALL BIT(1)
  21. #define MSIC_GPIO_TRIG_RISE BIT(2)
  22. /* masks for msic gpio output GPIOxxxxCTLO registers */
  23. #define MSIC_GPIO_DIR_MASK BIT(5)
  24. #define MSIC_GPIO_DRV_MASK BIT(4)
  25. #define MSIC_GPIO_REN_MASK BIT(3)
  26. #define MSIC_GPIO_RVAL_MASK (BIT(2) | BIT(1))
  27. #define MSIC_GPIO_DOUT_MASK BIT(0)
  28. /* masks for msic gpio input GPIOxxxxCTLI registers */
  29. #define MSIC_GPIO_GLBYP_MASK BIT(5)
  30. #define MSIC_GPIO_DBNC_MASK (BIT(4) | BIT(3))
  31. #define MSIC_GPIO_INTCNT_MASK (BIT(2) | BIT(1))
  32. #define MSIC_GPIO_DIN_MASK BIT(0)
  33. #define MSIC_NUM_GPIO 24
  34. struct msic_gpio {
  35. struct platform_device *pdev;
  36. struct mutex buslock;
  37. struct gpio_chip chip;
  38. int irq;
  39. unsigned irq_base;
  40. unsigned long trig_change_mask;
  41. unsigned trig_type;
  42. };
  43. /*
  44. * MSIC has 24 gpios, 16 low voltage (1.2-1.8v) and 8 high voltage (3v).
  45. * Both the high and low voltage gpios are divided in two banks.
  46. * GPIOs are numbered with GPIO0LV0 as gpio_base in the following order:
  47. * GPIO0LV0..GPIO0LV7: low voltage, bank 0, gpio_base
  48. * GPIO1LV0..GPIO1LV7: low voltage, bank 1, gpio_base + 8
  49. * GPIO0HV0..GPIO0HV3: high voltage, bank 0, gpio_base + 16
  50. * GPIO1HV0..GPIO1HV3: high voltage, bank 1, gpio_base + 20
  51. */
  52. static int msic_gpio_to_ireg(unsigned offset)
  53. {
  54. if (offset >= MSIC_NUM_GPIO)
  55. return -EINVAL;
  56. if (offset < 8)
  57. return INTEL_MSIC_GPIO0LV0CTLI - offset;
  58. if (offset < 16)
  59. return INTEL_MSIC_GPIO1LV0CTLI - offset + 8;
  60. if (offset < 20)
  61. return INTEL_MSIC_GPIO0HV0CTLI - offset + 16;
  62. return INTEL_MSIC_GPIO1HV0CTLI - offset + 20;
  63. }
  64. static int msic_gpio_to_oreg(unsigned offset)
  65. {
  66. if (offset >= MSIC_NUM_GPIO)
  67. return -EINVAL;
  68. if (offset < 8)
  69. return INTEL_MSIC_GPIO0LV0CTLO - offset;
  70. if (offset < 16)
  71. return INTEL_MSIC_GPIO1LV0CTLO - offset + 8;
  72. if (offset < 20)
  73. return INTEL_MSIC_GPIO0HV0CTLO - offset + 16;
  74. return INTEL_MSIC_GPIO1HV0CTLO - offset + 20;
  75. }
  76. static int msic_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
  77. {
  78. int reg;
  79. reg = msic_gpio_to_oreg(offset);
  80. if (reg < 0)
  81. return reg;
  82. return intel_msic_reg_update(reg, MSIC_GPIO_DIR_IN, MSIC_GPIO_DIR_MASK);
  83. }
  84. static int msic_gpio_direction_output(struct gpio_chip *chip,
  85. unsigned offset, int value)
  86. {
  87. int reg;
  88. unsigned mask;
  89. value = (!!value) | MSIC_GPIO_DIR_OUT;
  90. mask = MSIC_GPIO_DIR_MASK | MSIC_GPIO_DOUT_MASK;
  91. reg = msic_gpio_to_oreg(offset);
  92. if (reg < 0)
  93. return reg;
  94. return intel_msic_reg_update(reg, value, mask);
  95. }
  96. static int msic_gpio_get(struct gpio_chip *chip, unsigned offset)
  97. {
  98. u8 r;
  99. int ret;
  100. int reg;
  101. reg = msic_gpio_to_ireg(offset);
  102. if (reg < 0)
  103. return reg;
  104. ret = intel_msic_reg_read(reg, &r);
  105. if (ret < 0)
  106. return ret;
  107. return !!(r & MSIC_GPIO_DIN_MASK);
  108. }
  109. static void msic_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
  110. {
  111. int reg;
  112. reg = msic_gpio_to_oreg(offset);
  113. if (reg < 0)
  114. return;
  115. intel_msic_reg_update(reg, !!value , MSIC_GPIO_DOUT_MASK);
  116. }
  117. /*
  118. * This is called from genirq with mg->buslock locked and
  119. * irq_desc->lock held. We can not access the scu bus here, so we
  120. * store the change and update in the bus_sync_unlock() function below
  121. */
  122. static int msic_irq_type(struct irq_data *data, unsigned type)
  123. {
  124. struct msic_gpio *mg = irq_data_get_irq_chip_data(data);
  125. u32 gpio = data->irq - mg->irq_base;
  126. if (gpio >= mg->chip.ngpio)
  127. return -EINVAL;
  128. /* mark for which gpio the trigger changed, protected by buslock */
  129. mg->trig_change_mask |= (1 << gpio);
  130. mg->trig_type = type;
  131. return 0;
  132. }
  133. static int msic_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
  134. {
  135. struct msic_gpio *mg = gpiochip_get_data(chip);
  136. return mg->irq_base + offset;
  137. }
  138. static void msic_bus_lock(struct irq_data *data)
  139. {
  140. struct msic_gpio *mg = irq_data_get_irq_chip_data(data);
  141. mutex_lock(&mg->buslock);
  142. }
  143. static void msic_bus_sync_unlock(struct irq_data *data)
  144. {
  145. struct msic_gpio *mg = irq_data_get_irq_chip_data(data);
  146. int offset;
  147. int reg;
  148. u8 trig = 0;
  149. /* We can only get one change at a time as the buslock covers the
  150. entire transaction. The irq_desc->lock is dropped before we are
  151. called but that is fine */
  152. if (mg->trig_change_mask) {
  153. offset = __ffs(mg->trig_change_mask);
  154. reg = msic_gpio_to_ireg(offset);
  155. if (reg < 0)
  156. goto out;
  157. if (mg->trig_type & IRQ_TYPE_EDGE_RISING)
  158. trig |= MSIC_GPIO_TRIG_RISE;
  159. if (mg->trig_type & IRQ_TYPE_EDGE_FALLING)
  160. trig |= MSIC_GPIO_TRIG_FALL;
  161. intel_msic_reg_update(reg, trig, MSIC_GPIO_INTCNT_MASK);
  162. mg->trig_change_mask = 0;
  163. }
  164. out:
  165. mutex_unlock(&mg->buslock);
  166. }
  167. /* Firmware does all the masking and unmasking for us, no masking here. */
  168. static void msic_irq_unmask(struct irq_data *data) { }
  169. static void msic_irq_mask(struct irq_data *data) { }
  170. static struct irq_chip msic_irqchip = {
  171. .name = "MSIC-GPIO",
  172. .irq_mask = msic_irq_mask,
  173. .irq_unmask = msic_irq_unmask,
  174. .irq_set_type = msic_irq_type,
  175. .irq_bus_lock = msic_bus_lock,
  176. .irq_bus_sync_unlock = msic_bus_sync_unlock,
  177. };
  178. static void msic_gpio_irq_handler(struct irq_desc *desc)
  179. {
  180. struct irq_data *data = irq_desc_get_irq_data(desc);
  181. struct msic_gpio *mg = irq_data_get_irq_handler_data(data);
  182. struct irq_chip *chip = irq_data_get_irq_chip(data);
  183. struct intel_msic *msic = pdev_to_intel_msic(mg->pdev);
  184. unsigned long pending;
  185. int i;
  186. int bitnr;
  187. u8 pin;
  188. for (i = 0; i < (mg->chip.ngpio / BITS_PER_BYTE); i++) {
  189. intel_msic_irq_read(msic, INTEL_MSIC_GPIO0LVIRQ + i, &pin);
  190. pending = pin;
  191. for_each_set_bit(bitnr, &pending, BITS_PER_BYTE)
  192. generic_handle_irq(mg->irq_base + i * BITS_PER_BYTE + bitnr);
  193. }
  194. chip->irq_eoi(data);
  195. }
  196. static int platform_msic_gpio_probe(struct platform_device *pdev)
  197. {
  198. struct device *dev = &pdev->dev;
  199. struct intel_msic_gpio_pdata *pdata = dev_get_platdata(dev);
  200. struct msic_gpio *mg;
  201. int irq = platform_get_irq(pdev, 0);
  202. int retval;
  203. int i;
  204. if (irq < 0) {
  205. dev_err(dev, "no IRQ line: %d\n", irq);
  206. return irq;
  207. }
  208. if (!pdata || !pdata->gpio_base) {
  209. dev_err(dev, "incorrect or missing platform data\n");
  210. return -EINVAL;
  211. }
  212. mg = kzalloc(sizeof(*mg), GFP_KERNEL);
  213. if (!mg)
  214. return -ENOMEM;
  215. dev_set_drvdata(dev, mg);
  216. mg->pdev = pdev;
  217. mg->irq = irq;
  218. mg->irq_base = pdata->gpio_base + MSIC_GPIO_IRQ_OFFSET;
  219. mg->chip.label = "msic_gpio";
  220. mg->chip.direction_input = msic_gpio_direction_input;
  221. mg->chip.direction_output = msic_gpio_direction_output;
  222. mg->chip.get = msic_gpio_get;
  223. mg->chip.set = msic_gpio_set;
  224. mg->chip.to_irq = msic_gpio_to_irq;
  225. mg->chip.base = pdata->gpio_base;
  226. mg->chip.ngpio = MSIC_NUM_GPIO;
  227. mg->chip.can_sleep = true;
  228. mg->chip.parent = dev;
  229. mutex_init(&mg->buslock);
  230. retval = gpiochip_add_data(&mg->chip, mg);
  231. if (retval) {
  232. dev_err(dev, "Adding MSIC gpio chip failed\n");
  233. goto err;
  234. }
  235. for (i = 0; i < mg->chip.ngpio; i++) {
  236. irq_set_chip_data(i + mg->irq_base, mg);
  237. irq_set_chip_and_handler(i + mg->irq_base,
  238. &msic_irqchip,
  239. handle_simple_irq);
  240. }
  241. irq_set_chained_handler_and_data(mg->irq, msic_gpio_irq_handler, mg);
  242. return 0;
  243. err:
  244. kfree(mg);
  245. return retval;
  246. }
  247. static struct platform_driver platform_msic_gpio_driver = {
  248. .driver = {
  249. .name = "msic_gpio",
  250. },
  251. .probe = platform_msic_gpio_probe,
  252. };
  253. static int __init platform_msic_gpio_init(void)
  254. {
  255. return platform_driver_register(&platform_msic_gpio_driver);
  256. }
  257. subsys_initcall(platform_msic_gpio_init);