gpio-mmio.c 21 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Generic driver for memory-mapped GPIO controllers.
  4. *
  5. * Copyright 2008 MontaVista Software, Inc.
  6. * Copyright 2008,2010 Anton Vorontsov <cbouatmailru@gmail.com>
  7. *
  8. * ....``.```~~~~````.`.`.`.`.```````'',,,.........`````......`.......
  9. * ...`` ```````..
  10. * ..The simplest form of a GPIO controller that the driver supports is``
  11. * `.just a single "data" register, where GPIO state can be read and/or `
  12. * `,..written. ,,..``~~~~ .....``.`.`.~~.```.`.........``````.```````
  13. * `````````
  14. ___
  15. _/~~|___/~| . ```~~~~~~ ___/___\___ ,~.`.`.`.`````.~~...,,,,...
  16. __________|~$@~~~ %~ /o*o*o*o*o*o\ .. Implementing such a GPIO .
  17. o ` ~~~~\___/~~~~ ` controller in FPGA is ,.`
  18. `....trivial..'~`.```.```
  19. * ```````
  20. * .```````~~~~`..`.``.``.
  21. * . The driver supports `... ,..```.`~~~```````````````....````.``,,
  22. * . big-endian notation, just`. .. A bit more sophisticated controllers ,
  23. * . register the device with -be`. .with a pair of set/clear-bit registers ,
  24. * `.. suffix. ```~~`````....`.` . affecting the data register and the .`
  25. * ``.`.``...``` ```.. output pins are also supported.`
  26. * ^^ `````.`````````.,``~``~``~~``````
  27. * . ^^
  28. * ,..`.`.`...````````````......`.`.`.`.`.`..`.`.`..
  29. * .. The expectation is that in at least some cases . ,-~~~-,
  30. * .this will be used with roll-your-own ASIC/FPGA .` \ /
  31. * .logic in Verilog or VHDL. ~~~`````````..`````~~` \ /
  32. * ..````````......``````````` \o_
  33. * |
  34. * ^^ / \
  35. *
  36. * ...`````~~`.....``.`..........``````.`.``.```........``.
  37. * ` 8, 16, 32 and 64 bits registers are supported, and``.
  38. * . the number of GPIOs is determined by the width of ~
  39. * .. the registers. ,............```.`.`..`.`.~~~.`.`.`~
  40. * `.......````.```
  41. */
  42. #include <linux/init.h>
  43. #include <linux/err.h>
  44. #include <linux/bug.h>
  45. #include <linux/kernel.h>
  46. #include <linux/module.h>
  47. #include <linux/spinlock.h>
  48. #include <linux/compiler.h>
  49. #include <linux/types.h>
  50. #include <linux/errno.h>
  51. #include <linux/log2.h>
  52. #include <linux/ioport.h>
  53. #include <linux/io.h>
  54. #include <linux/gpio/driver.h>
  55. #include <linux/slab.h>
  56. #include <linux/bitops.h>
  57. #include <linux/platform_device.h>
  58. #include <linux/mod_devicetable.h>
  59. #include <linux/of.h>
  60. #include <linux/of_device.h>
  61. static void bgpio_write8(void __iomem *reg, unsigned long data)
  62. {
  63. writeb(data, reg);
  64. }
  65. static unsigned long bgpio_read8(void __iomem *reg)
  66. {
  67. return readb(reg);
  68. }
  69. static void bgpio_write16(void __iomem *reg, unsigned long data)
  70. {
  71. writew(data, reg);
  72. }
  73. static unsigned long bgpio_read16(void __iomem *reg)
  74. {
  75. return readw(reg);
  76. }
  77. static void bgpio_write32(void __iomem *reg, unsigned long data)
  78. {
  79. writel(data, reg);
  80. }
  81. static unsigned long bgpio_read32(void __iomem *reg)
  82. {
  83. return readl(reg);
  84. }
  85. #if BITS_PER_LONG >= 64
  86. static void bgpio_write64(void __iomem *reg, unsigned long data)
  87. {
  88. writeq(data, reg);
  89. }
  90. static unsigned long bgpio_read64(void __iomem *reg)
  91. {
  92. return readq(reg);
  93. }
  94. #endif /* BITS_PER_LONG >= 64 */
  95. static void bgpio_write16be(void __iomem *reg, unsigned long data)
  96. {
  97. iowrite16be(data, reg);
  98. }
  99. static unsigned long bgpio_read16be(void __iomem *reg)
  100. {
  101. return ioread16be(reg);
  102. }
  103. static void bgpio_write32be(void __iomem *reg, unsigned long data)
  104. {
  105. iowrite32be(data, reg);
  106. }
  107. static unsigned long bgpio_read32be(void __iomem *reg)
  108. {
  109. return ioread32be(reg);
  110. }
  111. static unsigned long bgpio_line2mask(struct gpio_chip *gc, unsigned int line)
  112. {
  113. if (gc->be_bits)
  114. return BIT(gc->bgpio_bits - 1 - line);
  115. return BIT(line);
  116. }
  117. static int bgpio_get_set(struct gpio_chip *gc, unsigned int gpio)
  118. {
  119. unsigned long pinmask = bgpio_line2mask(gc, gpio);
  120. bool dir = !!(gc->bgpio_dir & pinmask);
  121. if (dir)
  122. return !!(gc->read_reg(gc->reg_set) & pinmask);
  123. else
  124. return !!(gc->read_reg(gc->reg_dat) & pinmask);
  125. }
  126. /*
  127. * This assumes that the bits in the GPIO register are in native endianness.
  128. * We only assign the function pointer if we have that.
  129. */
  130. static int bgpio_get_set_multiple(struct gpio_chip *gc, unsigned long *mask,
  131. unsigned long *bits)
  132. {
  133. unsigned long get_mask = 0;
  134. unsigned long set_mask = 0;
  135. /* Make sure we first clear any bits that are zero when we read the register */
  136. *bits &= ~*mask;
  137. set_mask = *mask & gc->bgpio_dir;
  138. get_mask = *mask & ~gc->bgpio_dir;
  139. if (set_mask)
  140. *bits |= gc->read_reg(gc->reg_set) & set_mask;
  141. if (get_mask)
  142. *bits |= gc->read_reg(gc->reg_dat) & get_mask;
  143. return 0;
  144. }
  145. static int bgpio_get(struct gpio_chip *gc, unsigned int gpio)
  146. {
  147. return !!(gc->read_reg(gc->reg_dat) & bgpio_line2mask(gc, gpio));
  148. }
  149. /*
  150. * This only works if the bits in the GPIO register are in native endianness.
  151. */
  152. static int bgpio_get_multiple(struct gpio_chip *gc, unsigned long *mask,
  153. unsigned long *bits)
  154. {
  155. /* Make sure we first clear any bits that are zero when we read the register */
  156. *bits &= ~*mask;
  157. *bits |= gc->read_reg(gc->reg_dat) & *mask;
  158. return 0;
  159. }
  160. /*
  161. * With big endian mirrored bit order it becomes more tedious.
  162. */
  163. static int bgpio_get_multiple_be(struct gpio_chip *gc, unsigned long *mask,
  164. unsigned long *bits)
  165. {
  166. unsigned long readmask = 0;
  167. unsigned long val;
  168. int bit;
  169. /* Make sure we first clear any bits that are zero when we read the register */
  170. *bits &= ~*mask;
  171. /* Create a mirrored mask */
  172. for_each_set_bit(bit, mask, gc->ngpio)
  173. readmask |= bgpio_line2mask(gc, bit);
  174. /* Read the register */
  175. val = gc->read_reg(gc->reg_dat) & readmask;
  176. /*
  177. * Mirror the result into the "bits" result, this will give line 0
  178. * in bit 0 ... line 31 in bit 31 for a 32bit register.
  179. */
  180. for_each_set_bit(bit, &val, gc->ngpio)
  181. *bits |= bgpio_line2mask(gc, bit);
  182. return 0;
  183. }
  184. static void bgpio_set_none(struct gpio_chip *gc, unsigned int gpio, int val)
  185. {
  186. }
  187. static void bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
  188. {
  189. unsigned long mask = bgpio_line2mask(gc, gpio);
  190. unsigned long flags;
  191. spin_lock_irqsave(&gc->bgpio_lock, flags);
  192. if (val)
  193. gc->bgpio_data |= mask;
  194. else
  195. gc->bgpio_data &= ~mask;
  196. gc->write_reg(gc->reg_dat, gc->bgpio_data);
  197. spin_unlock_irqrestore(&gc->bgpio_lock, flags);
  198. }
  199. static void bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio,
  200. int val)
  201. {
  202. unsigned long mask = bgpio_line2mask(gc, gpio);
  203. if (val)
  204. gc->write_reg(gc->reg_set, mask);
  205. else
  206. gc->write_reg(gc->reg_clr, mask);
  207. }
  208. static void bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val)
  209. {
  210. unsigned long mask = bgpio_line2mask(gc, gpio);
  211. unsigned long flags;
  212. spin_lock_irqsave(&gc->bgpio_lock, flags);
  213. if (val)
  214. gc->bgpio_data |= mask;
  215. else
  216. gc->bgpio_data &= ~mask;
  217. gc->write_reg(gc->reg_set, gc->bgpio_data);
  218. spin_unlock_irqrestore(&gc->bgpio_lock, flags);
  219. }
  220. static void bgpio_multiple_get_masks(struct gpio_chip *gc,
  221. unsigned long *mask, unsigned long *bits,
  222. unsigned long *set_mask,
  223. unsigned long *clear_mask)
  224. {
  225. int i;
  226. *set_mask = 0;
  227. *clear_mask = 0;
  228. for_each_set_bit(i, mask, gc->bgpio_bits) {
  229. if (test_bit(i, bits))
  230. *set_mask |= bgpio_line2mask(gc, i);
  231. else
  232. *clear_mask |= bgpio_line2mask(gc, i);
  233. }
  234. }
  235. static void bgpio_set_multiple_single_reg(struct gpio_chip *gc,
  236. unsigned long *mask,
  237. unsigned long *bits,
  238. void __iomem *reg)
  239. {
  240. unsigned long flags;
  241. unsigned long set_mask, clear_mask;
  242. spin_lock_irqsave(&gc->bgpio_lock, flags);
  243. bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask);
  244. gc->bgpio_data |= set_mask;
  245. gc->bgpio_data &= ~clear_mask;
  246. gc->write_reg(reg, gc->bgpio_data);
  247. spin_unlock_irqrestore(&gc->bgpio_lock, flags);
  248. }
  249. static void bgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
  250. unsigned long *bits)
  251. {
  252. bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_dat);
  253. }
  254. static void bgpio_set_multiple_set(struct gpio_chip *gc, unsigned long *mask,
  255. unsigned long *bits)
  256. {
  257. bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_set);
  258. }
  259. static void bgpio_set_multiple_with_clear(struct gpio_chip *gc,
  260. unsigned long *mask,
  261. unsigned long *bits)
  262. {
  263. unsigned long set_mask, clear_mask;
  264. bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask);
  265. if (set_mask)
  266. gc->write_reg(gc->reg_set, set_mask);
  267. if (clear_mask)
  268. gc->write_reg(gc->reg_clr, clear_mask);
  269. }
  270. static int bgpio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio)
  271. {
  272. return 0;
  273. }
  274. static int bgpio_dir_out_err(struct gpio_chip *gc, unsigned int gpio,
  275. int val)
  276. {
  277. return -EINVAL;
  278. }
  279. static int bgpio_simple_dir_out(struct gpio_chip *gc, unsigned int gpio,
  280. int val)
  281. {
  282. gc->set(gc, gpio, val);
  283. return 0;
  284. }
  285. static int bgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
  286. {
  287. unsigned long flags;
  288. spin_lock_irqsave(&gc->bgpio_lock, flags);
  289. gc->bgpio_dir &= ~bgpio_line2mask(gc, gpio);
  290. if (gc->reg_dir_in)
  291. gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir);
  292. if (gc->reg_dir_out)
  293. gc->write_reg(gc->reg_dir_out, gc->bgpio_dir);
  294. spin_unlock_irqrestore(&gc->bgpio_lock, flags);
  295. return 0;
  296. }
  297. static int bgpio_get_dir(struct gpio_chip *gc, unsigned int gpio)
  298. {
  299. /* Return 0 if output, 1 if input */
  300. if (gc->bgpio_dir_unreadable) {
  301. if (gc->bgpio_dir & bgpio_line2mask(gc, gpio))
  302. return GPIO_LINE_DIRECTION_OUT;
  303. return GPIO_LINE_DIRECTION_IN;
  304. }
  305. if (gc->reg_dir_out) {
  306. if (gc->read_reg(gc->reg_dir_out) & bgpio_line2mask(gc, gpio))
  307. return GPIO_LINE_DIRECTION_OUT;
  308. return GPIO_LINE_DIRECTION_IN;
  309. }
  310. if (gc->reg_dir_in)
  311. if (!(gc->read_reg(gc->reg_dir_in) & bgpio_line2mask(gc, gpio)))
  312. return GPIO_LINE_DIRECTION_OUT;
  313. return GPIO_LINE_DIRECTION_IN;
  314. }
  315. static void bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
  316. {
  317. unsigned long flags;
  318. spin_lock_irqsave(&gc->bgpio_lock, flags);
  319. gc->bgpio_dir |= bgpio_line2mask(gc, gpio);
  320. if (gc->reg_dir_in)
  321. gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir);
  322. if (gc->reg_dir_out)
  323. gc->write_reg(gc->reg_dir_out, gc->bgpio_dir);
  324. spin_unlock_irqrestore(&gc->bgpio_lock, flags);
  325. }
  326. static int bgpio_dir_out_dir_first(struct gpio_chip *gc, unsigned int gpio,
  327. int val)
  328. {
  329. bgpio_dir_out(gc, gpio, val);
  330. gc->set(gc, gpio, val);
  331. return 0;
  332. }
  333. static int bgpio_dir_out_val_first(struct gpio_chip *gc, unsigned int gpio,
  334. int val)
  335. {
  336. gc->set(gc, gpio, val);
  337. bgpio_dir_out(gc, gpio, val);
  338. return 0;
  339. }
  340. static int bgpio_setup_accessors(struct device *dev,
  341. struct gpio_chip *gc,
  342. bool byte_be)
  343. {
  344. switch (gc->bgpio_bits) {
  345. case 8:
  346. gc->read_reg = bgpio_read8;
  347. gc->write_reg = bgpio_write8;
  348. break;
  349. case 16:
  350. if (byte_be) {
  351. gc->read_reg = bgpio_read16be;
  352. gc->write_reg = bgpio_write16be;
  353. } else {
  354. gc->read_reg = bgpio_read16;
  355. gc->write_reg = bgpio_write16;
  356. }
  357. break;
  358. case 32:
  359. if (byte_be) {
  360. gc->read_reg = bgpio_read32be;
  361. gc->write_reg = bgpio_write32be;
  362. } else {
  363. gc->read_reg = bgpio_read32;
  364. gc->write_reg = bgpio_write32;
  365. }
  366. break;
  367. #if BITS_PER_LONG >= 64
  368. case 64:
  369. if (byte_be) {
  370. dev_err(dev,
  371. "64 bit big endian byte order unsupported\n");
  372. return -EINVAL;
  373. } else {
  374. gc->read_reg = bgpio_read64;
  375. gc->write_reg = bgpio_write64;
  376. }
  377. break;
  378. #endif /* BITS_PER_LONG >= 64 */
  379. default:
  380. dev_err(dev, "unsupported data width %u bits\n", gc->bgpio_bits);
  381. return -EINVAL;
  382. }
  383. return 0;
  384. }
  385. /*
  386. * Create the device and allocate the resources. For setting GPIO's there are
  387. * three supported configurations:
  388. *
  389. * - single input/output register resource (named "dat").
  390. * - set/clear pair (named "set" and "clr").
  391. * - single output register resource and single input resource ("set" and
  392. * dat").
  393. *
  394. * For the single output register, this drives a 1 by setting a bit and a zero
  395. * by clearing a bit. For the set clr pair, this drives a 1 by setting a bit
  396. * in the set register and clears it by setting a bit in the clear register.
  397. * The configuration is detected by which resources are present.
  398. *
  399. * For setting the GPIO direction, there are three supported configurations:
  400. *
  401. * - simple bidirection GPIO that requires no configuration.
  402. * - an output direction register (named "dirout") where a 1 bit
  403. * indicates the GPIO is an output.
  404. * - an input direction register (named "dirin") where a 1 bit indicates
  405. * the GPIO is an input.
  406. */
  407. static int bgpio_setup_io(struct gpio_chip *gc,
  408. void __iomem *dat,
  409. void __iomem *set,
  410. void __iomem *clr,
  411. unsigned long flags)
  412. {
  413. gc->reg_dat = dat;
  414. if (!gc->reg_dat)
  415. return -EINVAL;
  416. if (set && clr) {
  417. gc->reg_set = set;
  418. gc->reg_clr = clr;
  419. gc->set = bgpio_set_with_clear;
  420. gc->set_multiple = bgpio_set_multiple_with_clear;
  421. } else if (set && !clr) {
  422. gc->reg_set = set;
  423. gc->set = bgpio_set_set;
  424. gc->set_multiple = bgpio_set_multiple_set;
  425. } else if (flags & BGPIOF_NO_OUTPUT) {
  426. gc->set = bgpio_set_none;
  427. gc->set_multiple = NULL;
  428. } else {
  429. gc->set = bgpio_set;
  430. gc->set_multiple = bgpio_set_multiple;
  431. }
  432. if (!(flags & BGPIOF_UNREADABLE_REG_SET) &&
  433. (flags & BGPIOF_READ_OUTPUT_REG_SET)) {
  434. gc->get = bgpio_get_set;
  435. if (!gc->be_bits)
  436. gc->get_multiple = bgpio_get_set_multiple;
  437. /*
  438. * We deliberately avoid assigning the ->get_multiple() call
  439. * for big endian mirrored registers which are ALSO reflecting
  440. * their value in the set register when used as output. It is
  441. * simply too much complexity, let the GPIO core fall back to
  442. * reading each line individually in that fringe case.
  443. */
  444. } else {
  445. gc->get = bgpio_get;
  446. if (gc->be_bits)
  447. gc->get_multiple = bgpio_get_multiple_be;
  448. else
  449. gc->get_multiple = bgpio_get_multiple;
  450. }
  451. return 0;
  452. }
  453. static int bgpio_setup_direction(struct gpio_chip *gc,
  454. void __iomem *dirout,
  455. void __iomem *dirin,
  456. unsigned long flags)
  457. {
  458. if (dirout || dirin) {
  459. gc->reg_dir_out = dirout;
  460. gc->reg_dir_in = dirin;
  461. if (flags & BGPIOF_NO_SET_ON_INPUT)
  462. gc->direction_output = bgpio_dir_out_dir_first;
  463. else
  464. gc->direction_output = bgpio_dir_out_val_first;
  465. gc->direction_input = bgpio_dir_in;
  466. gc->get_direction = bgpio_get_dir;
  467. } else {
  468. if (flags & BGPIOF_NO_OUTPUT)
  469. gc->direction_output = bgpio_dir_out_err;
  470. else
  471. gc->direction_output = bgpio_simple_dir_out;
  472. gc->direction_input = bgpio_simple_dir_in;
  473. }
  474. return 0;
  475. }
  476. static int bgpio_request(struct gpio_chip *chip, unsigned gpio_pin)
  477. {
  478. if (gpio_pin < chip->ngpio)
  479. return 0;
  480. return -EINVAL;
  481. }
  482. /**
  483. * bgpio_init() - Initialize generic GPIO accessor functions
  484. * @gc: the GPIO chip to set up
  485. * @dev: the parent device of the new GPIO chip (compulsory)
  486. * @sz: the size (width) of the MMIO registers in bytes, typically 1, 2 or 4
  487. * @dat: MMIO address for the register to READ the value of the GPIO lines, it
  488. * is expected that a 1 in the corresponding bit in this register means the
  489. * line is asserted
  490. * @set: MMIO address for the register to SET the value of the GPIO lines, it is
  491. * expected that we write the line with 1 in this register to drive the GPIO line
  492. * high.
  493. * @clr: MMIO address for the register to CLEAR the value of the GPIO lines, it is
  494. * expected that we write the line with 1 in this register to drive the GPIO line
  495. * low. It is allowed to leave this address as NULL, in that case the SET register
  496. * will be assumed to also clear the GPIO lines, by actively writing the line
  497. * with 0.
  498. * @dirout: MMIO address for the register to set the line as OUTPUT. It is assumed
  499. * that setting a line to 1 in this register will turn that line into an
  500. * output line. Conversely, setting the line to 0 will turn that line into
  501. * an input.
  502. * @dirin: MMIO address for the register to set this line as INPUT. It is assumed
  503. * that setting a line to 1 in this register will turn that line into an
  504. * input line. Conversely, setting the line to 0 will turn that line into
  505. * an output.
  506. * @flags: Different flags that will affect the behaviour of the device, such as
  507. * endianness etc.
  508. */
  509. int bgpio_init(struct gpio_chip *gc, struct device *dev,
  510. unsigned long sz, void __iomem *dat, void __iomem *set,
  511. void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
  512. unsigned long flags)
  513. {
  514. int ret;
  515. if (!is_power_of_2(sz))
  516. return -EINVAL;
  517. gc->bgpio_bits = sz * 8;
  518. if (gc->bgpio_bits > BITS_PER_LONG)
  519. return -EINVAL;
  520. spin_lock_init(&gc->bgpio_lock);
  521. gc->parent = dev;
  522. gc->label = dev_name(dev);
  523. gc->base = -1;
  524. gc->ngpio = gc->bgpio_bits;
  525. gc->request = bgpio_request;
  526. gc->be_bits = !!(flags & BGPIOF_BIG_ENDIAN);
  527. ret = bgpio_setup_io(gc, dat, set, clr, flags);
  528. if (ret)
  529. return ret;
  530. ret = bgpio_setup_accessors(dev, gc, flags & BGPIOF_BIG_ENDIAN_BYTE_ORDER);
  531. if (ret)
  532. return ret;
  533. ret = bgpio_setup_direction(gc, dirout, dirin, flags);
  534. if (ret)
  535. return ret;
  536. gc->bgpio_data = gc->read_reg(gc->reg_dat);
  537. if (gc->set == bgpio_set_set &&
  538. !(flags & BGPIOF_UNREADABLE_REG_SET))
  539. gc->bgpio_data = gc->read_reg(gc->reg_set);
  540. if (flags & BGPIOF_UNREADABLE_REG_DIR)
  541. gc->bgpio_dir_unreadable = true;
  542. /*
  543. * Inspect hardware to find initial direction setting.
  544. */
  545. if ((gc->reg_dir_out || gc->reg_dir_in) &&
  546. !(flags & BGPIOF_UNREADABLE_REG_DIR)) {
  547. if (gc->reg_dir_out)
  548. gc->bgpio_dir = gc->read_reg(gc->reg_dir_out);
  549. else if (gc->reg_dir_in)
  550. gc->bgpio_dir = ~gc->read_reg(gc->reg_dir_in);
  551. /*
  552. * If we have two direction registers, synchronise
  553. * input setting to output setting, the library
  554. * can not handle a line being input and output at
  555. * the same time.
  556. */
  557. if (gc->reg_dir_out && gc->reg_dir_in)
  558. gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir);
  559. }
  560. return ret;
  561. }
  562. EXPORT_SYMBOL_GPL(bgpio_init);
  563. #if IS_ENABLED(CONFIG_GPIO_GENERIC_PLATFORM)
  564. static void __iomem *bgpio_map(struct platform_device *pdev,
  565. const char *name,
  566. resource_size_t sane_sz)
  567. {
  568. struct resource *r;
  569. resource_size_t sz;
  570. r = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
  571. if (!r)
  572. return NULL;
  573. sz = resource_size(r);
  574. if (sz != sane_sz)
  575. return IOMEM_ERR_PTR(-EINVAL);
  576. return devm_ioremap_resource(&pdev->dev, r);
  577. }
  578. #ifdef CONFIG_OF
  579. static const struct of_device_id bgpio_of_match[] = {
  580. { .compatible = "brcm,bcm6345-gpio" },
  581. { .compatible = "wd,mbl-gpio" },
  582. { .compatible = "ni,169445-nand-gpio" },
  583. { }
  584. };
  585. MODULE_DEVICE_TABLE(of, bgpio_of_match);
  586. static struct bgpio_pdata *bgpio_parse_dt(struct platform_device *pdev,
  587. unsigned long *flags)
  588. {
  589. struct bgpio_pdata *pdata;
  590. if (!of_match_device(bgpio_of_match, &pdev->dev))
  591. return NULL;
  592. pdata = devm_kzalloc(&pdev->dev, sizeof(struct bgpio_pdata),
  593. GFP_KERNEL);
  594. if (!pdata)
  595. return ERR_PTR(-ENOMEM);
  596. pdata->base = -1;
  597. if (of_device_is_big_endian(pdev->dev.of_node))
  598. *flags |= BGPIOF_BIG_ENDIAN_BYTE_ORDER;
  599. if (of_property_read_bool(pdev->dev.of_node, "no-output"))
  600. *flags |= BGPIOF_NO_OUTPUT;
  601. return pdata;
  602. }
  603. #else
  604. static struct bgpio_pdata *bgpio_parse_dt(struct platform_device *pdev,
  605. unsigned long *flags)
  606. {
  607. return NULL;
  608. }
  609. #endif /* CONFIG_OF */
  610. static int bgpio_pdev_probe(struct platform_device *pdev)
  611. {
  612. struct device *dev = &pdev->dev;
  613. struct resource *r;
  614. void __iomem *dat;
  615. void __iomem *set;
  616. void __iomem *clr;
  617. void __iomem *dirout;
  618. void __iomem *dirin;
  619. unsigned long sz;
  620. unsigned long flags = 0;
  621. int err;
  622. struct gpio_chip *gc;
  623. struct bgpio_pdata *pdata;
  624. pdata = bgpio_parse_dt(pdev, &flags);
  625. if (IS_ERR(pdata))
  626. return PTR_ERR(pdata);
  627. if (!pdata) {
  628. pdata = dev_get_platdata(dev);
  629. flags = pdev->id_entry->driver_data;
  630. }
  631. r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
  632. if (!r)
  633. return -EINVAL;
  634. sz = resource_size(r);
  635. dat = bgpio_map(pdev, "dat", sz);
  636. if (IS_ERR(dat))
  637. return PTR_ERR(dat);
  638. set = bgpio_map(pdev, "set", sz);
  639. if (IS_ERR(set))
  640. return PTR_ERR(set);
  641. clr = bgpio_map(pdev, "clr", sz);
  642. if (IS_ERR(clr))
  643. return PTR_ERR(clr);
  644. dirout = bgpio_map(pdev, "dirout", sz);
  645. if (IS_ERR(dirout))
  646. return PTR_ERR(dirout);
  647. dirin = bgpio_map(pdev, "dirin", sz);
  648. if (IS_ERR(dirin))
  649. return PTR_ERR(dirin);
  650. gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL);
  651. if (!gc)
  652. return -ENOMEM;
  653. err = bgpio_init(gc, dev, sz, dat, set, clr, dirout, dirin, flags);
  654. if (err)
  655. return err;
  656. if (pdata) {
  657. if (pdata->label)
  658. gc->label = pdata->label;
  659. gc->base = pdata->base;
  660. if (pdata->ngpio > 0)
  661. gc->ngpio = pdata->ngpio;
  662. }
  663. platform_set_drvdata(pdev, gc);
  664. return devm_gpiochip_add_data(&pdev->dev, gc, NULL);
  665. }
  666. static const struct platform_device_id bgpio_id_table[] = {
  667. {
  668. .name = "basic-mmio-gpio",
  669. .driver_data = 0,
  670. }, {
  671. .name = "basic-mmio-gpio-be",
  672. .driver_data = BGPIOF_BIG_ENDIAN,
  673. },
  674. { }
  675. };
  676. MODULE_DEVICE_TABLE(platform, bgpio_id_table);
  677. static struct platform_driver bgpio_driver = {
  678. .driver = {
  679. .name = "basic-mmio-gpio",
  680. .of_match_table = of_match_ptr(bgpio_of_match),
  681. },
  682. .id_table = bgpio_id_table,
  683. .probe = bgpio_pdev_probe,
  684. };
  685. module_platform_driver(bgpio_driver);
  686. #endif /* CONFIG_GPIO_GENERIC_PLATFORM */
  687. MODULE_DESCRIPTION("Driver for basic memory-mapped GPIO controllers");
  688. MODULE_AUTHOR("Anton Vorontsov <cbouatmailru@gmail.com>");
  689. MODULE_LICENSE("GPL");