gpio-ml-ioh.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/kernel.h>
  7. #include <linux/slab.h>
  8. #include <linux/pci.h>
  9. #include <linux/gpio/driver.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/irq.h>
  12. #define IOH_EDGE_FALLING 0
  13. #define IOH_EDGE_RISING BIT(0)
  14. #define IOH_LEVEL_L BIT(1)
  15. #define IOH_LEVEL_H (BIT(0) | BIT(1))
  16. #define IOH_EDGE_BOTH BIT(2)
  17. #define IOH_IM_MASK (BIT(0) | BIT(1) | BIT(2))
  18. #define IOH_IRQ_BASE 0
  19. struct ioh_reg_comn {
  20. u32 ien;
  21. u32 istatus;
  22. u32 idisp;
  23. u32 iclr;
  24. u32 imask;
  25. u32 imaskclr;
  26. u32 po;
  27. u32 pi;
  28. u32 pm;
  29. u32 im_0;
  30. u32 im_1;
  31. u32 reserved;
  32. };
  33. struct ioh_regs {
  34. struct ioh_reg_comn regs[8];
  35. u32 reserve1[16];
  36. u32 ioh_sel_reg[4];
  37. u32 reserve2[11];
  38. u32 srst;
  39. };
  40. /**
  41. * struct ioh_gpio_reg_data - The register store data.
  42. * @ien_reg: To store contents of interrupt enable register.
  43. * @imask_reg: To store contents of interrupt mask regist
  44. * @po_reg: To store contents of PO register.
  45. * @pm_reg: To store contents of PM register.
  46. * @im0_reg: To store contents of interrupt mode regist0
  47. * @im1_reg: To store contents of interrupt mode regist1
  48. * @use_sel_reg: To store contents of GPIO_USE_SEL0~3
  49. */
  50. struct ioh_gpio_reg_data {
  51. u32 ien_reg;
  52. u32 imask_reg;
  53. u32 po_reg;
  54. u32 pm_reg;
  55. u32 im0_reg;
  56. u32 im1_reg;
  57. u32 use_sel_reg;
  58. };
  59. /**
  60. * struct ioh_gpio - GPIO private data structure.
  61. * @base: PCI base address of Memory mapped I/O register.
  62. * @reg: Memory mapped IOH GPIO register list.
  63. * @dev: Pointer to device structure.
  64. * @gpio: Data for GPIO infrastructure.
  65. * @ioh_gpio_reg: Memory mapped Register data is saved here
  66. * when suspend.
  67. * @gpio_use_sel: Save GPIO_USE_SEL1~4 register for PM
  68. * @ch: Indicate GPIO channel
  69. * @irq_base: Save base of IRQ number for interrupt
  70. * @spinlock: Used for register access protection
  71. */
  72. struct ioh_gpio {
  73. void __iomem *base;
  74. struct ioh_regs __iomem *reg;
  75. struct device *dev;
  76. struct gpio_chip gpio;
  77. struct ioh_gpio_reg_data ioh_gpio_reg;
  78. u32 gpio_use_sel;
  79. int ch;
  80. int irq_base;
  81. spinlock_t spinlock;
  82. };
  83. static const int num_ports[] = {6, 12, 16, 16, 15, 16, 16, 12};
  84. static void ioh_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
  85. {
  86. u32 reg_val;
  87. struct ioh_gpio *chip = gpiochip_get_data(gpio);
  88. unsigned long flags;
  89. spin_lock_irqsave(&chip->spinlock, flags);
  90. reg_val = ioread32(&chip->reg->regs[chip->ch].po);
  91. if (val)
  92. reg_val |= (1 << nr);
  93. else
  94. reg_val &= ~(1 << nr);
  95. iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
  96. spin_unlock_irqrestore(&chip->spinlock, flags);
  97. }
  98. static int ioh_gpio_get(struct gpio_chip *gpio, unsigned nr)
  99. {
  100. struct ioh_gpio *chip = gpiochip_get_data(gpio);
  101. return !!(ioread32(&chip->reg->regs[chip->ch].pi) & (1 << nr));
  102. }
  103. static int ioh_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
  104. int val)
  105. {
  106. struct ioh_gpio *chip = gpiochip_get_data(gpio);
  107. u32 pm;
  108. u32 reg_val;
  109. unsigned long flags;
  110. spin_lock_irqsave(&chip->spinlock, flags);
  111. pm = ioread32(&chip->reg->regs[chip->ch].pm) &
  112. ((1 << num_ports[chip->ch]) - 1);
  113. pm |= (1 << nr);
  114. iowrite32(pm, &chip->reg->regs[chip->ch].pm);
  115. reg_val = ioread32(&chip->reg->regs[chip->ch].po);
  116. if (val)
  117. reg_val |= (1 << nr);
  118. else
  119. reg_val &= ~(1 << nr);
  120. iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
  121. spin_unlock_irqrestore(&chip->spinlock, flags);
  122. return 0;
  123. }
  124. static int ioh_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
  125. {
  126. struct ioh_gpio *chip = gpiochip_get_data(gpio);
  127. u32 pm;
  128. unsigned long flags;
  129. spin_lock_irqsave(&chip->spinlock, flags);
  130. pm = ioread32(&chip->reg->regs[chip->ch].pm) &
  131. ((1 << num_ports[chip->ch]) - 1);
  132. pm &= ~(1 << nr);
  133. iowrite32(pm, &chip->reg->regs[chip->ch].pm);
  134. spin_unlock_irqrestore(&chip->spinlock, flags);
  135. return 0;
  136. }
  137. #ifdef CONFIG_PM
  138. /*
  139. * Save register configuration and disable interrupts.
  140. */
  141. static void ioh_gpio_save_reg_conf(struct ioh_gpio *chip)
  142. {
  143. int i;
  144. for (i = 0; i < 8; i ++, chip++) {
  145. chip->ioh_gpio_reg.po_reg =
  146. ioread32(&chip->reg->regs[chip->ch].po);
  147. chip->ioh_gpio_reg.pm_reg =
  148. ioread32(&chip->reg->regs[chip->ch].pm);
  149. chip->ioh_gpio_reg.ien_reg =
  150. ioread32(&chip->reg->regs[chip->ch].ien);
  151. chip->ioh_gpio_reg.imask_reg =
  152. ioread32(&chip->reg->regs[chip->ch].imask);
  153. chip->ioh_gpio_reg.im0_reg =
  154. ioread32(&chip->reg->regs[chip->ch].im_0);
  155. chip->ioh_gpio_reg.im1_reg =
  156. ioread32(&chip->reg->regs[chip->ch].im_1);
  157. if (i < 4)
  158. chip->ioh_gpio_reg.use_sel_reg =
  159. ioread32(&chip->reg->ioh_sel_reg[i]);
  160. }
  161. }
  162. /*
  163. * This function restores the register configuration of the GPIO device.
  164. */
  165. static void ioh_gpio_restore_reg_conf(struct ioh_gpio *chip)
  166. {
  167. int i;
  168. for (i = 0; i < 8; i ++, chip++) {
  169. iowrite32(chip->ioh_gpio_reg.po_reg,
  170. &chip->reg->regs[chip->ch].po);
  171. iowrite32(chip->ioh_gpio_reg.pm_reg,
  172. &chip->reg->regs[chip->ch].pm);
  173. iowrite32(chip->ioh_gpio_reg.ien_reg,
  174. &chip->reg->regs[chip->ch].ien);
  175. iowrite32(chip->ioh_gpio_reg.imask_reg,
  176. &chip->reg->regs[chip->ch].imask);
  177. iowrite32(chip->ioh_gpio_reg.im0_reg,
  178. &chip->reg->regs[chip->ch].im_0);
  179. iowrite32(chip->ioh_gpio_reg.im1_reg,
  180. &chip->reg->regs[chip->ch].im_1);
  181. if (i < 4)
  182. iowrite32(chip->ioh_gpio_reg.use_sel_reg,
  183. &chip->reg->ioh_sel_reg[i]);
  184. }
  185. }
  186. #endif
  187. static int ioh_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
  188. {
  189. struct ioh_gpio *chip = gpiochip_get_data(gpio);
  190. return chip->irq_base + offset;
  191. }
  192. static void ioh_gpio_setup(struct ioh_gpio *chip, int num_port)
  193. {
  194. struct gpio_chip *gpio = &chip->gpio;
  195. gpio->label = dev_name(chip->dev);
  196. gpio->owner = THIS_MODULE;
  197. gpio->direction_input = ioh_gpio_direction_input;
  198. gpio->get = ioh_gpio_get;
  199. gpio->direction_output = ioh_gpio_direction_output;
  200. gpio->set = ioh_gpio_set;
  201. gpio->dbg_show = NULL;
  202. gpio->base = -1;
  203. gpio->ngpio = num_port;
  204. gpio->can_sleep = false;
  205. gpio->to_irq = ioh_gpio_to_irq;
  206. }
  207. static int ioh_irq_type(struct irq_data *d, unsigned int type)
  208. {
  209. u32 im;
  210. void __iomem *im_reg;
  211. u32 ien;
  212. u32 im_pos;
  213. int ch;
  214. unsigned long flags;
  215. u32 val;
  216. int irq = d->irq;
  217. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  218. struct ioh_gpio *chip = gc->private;
  219. ch = irq - chip->irq_base;
  220. if (irq <= chip->irq_base + 7) {
  221. im_reg = &chip->reg->regs[chip->ch].im_0;
  222. im_pos = ch;
  223. } else {
  224. im_reg = &chip->reg->regs[chip->ch].im_1;
  225. im_pos = ch - 8;
  226. }
  227. dev_dbg(chip->dev, "%s:irq=%d type=%d ch=%d pos=%d type=%d\n",
  228. __func__, irq, type, ch, im_pos, type);
  229. spin_lock_irqsave(&chip->spinlock, flags);
  230. switch (type) {
  231. case IRQ_TYPE_EDGE_RISING:
  232. val = IOH_EDGE_RISING;
  233. break;
  234. case IRQ_TYPE_EDGE_FALLING:
  235. val = IOH_EDGE_FALLING;
  236. break;
  237. case IRQ_TYPE_EDGE_BOTH:
  238. val = IOH_EDGE_BOTH;
  239. break;
  240. case IRQ_TYPE_LEVEL_HIGH:
  241. val = IOH_LEVEL_H;
  242. break;
  243. case IRQ_TYPE_LEVEL_LOW:
  244. val = IOH_LEVEL_L;
  245. break;
  246. case IRQ_TYPE_PROBE:
  247. goto end;
  248. default:
  249. dev_warn(chip->dev, "%s: unknown type(%dd)",
  250. __func__, type);
  251. goto end;
  252. }
  253. /* Set interrupt mode */
  254. im = ioread32(im_reg) & ~(IOH_IM_MASK << (im_pos * 4));
  255. iowrite32(im | (val << (im_pos * 4)), im_reg);
  256. /* iclr */
  257. iowrite32(BIT(ch), &chip->reg->regs[chip->ch].iclr);
  258. /* IMASKCLR */
  259. iowrite32(BIT(ch), &chip->reg->regs[chip->ch].imaskclr);
  260. /* Enable interrupt */
  261. ien = ioread32(&chip->reg->regs[chip->ch].ien);
  262. iowrite32(ien | BIT(ch), &chip->reg->regs[chip->ch].ien);
  263. end:
  264. spin_unlock_irqrestore(&chip->spinlock, flags);
  265. return 0;
  266. }
  267. static void ioh_irq_unmask(struct irq_data *d)
  268. {
  269. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  270. struct ioh_gpio *chip = gc->private;
  271. iowrite32(1 << (d->irq - chip->irq_base),
  272. &chip->reg->regs[chip->ch].imaskclr);
  273. }
  274. static void ioh_irq_mask(struct irq_data *d)
  275. {
  276. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  277. struct ioh_gpio *chip = gc->private;
  278. iowrite32(1 << (d->irq - chip->irq_base),
  279. &chip->reg->regs[chip->ch].imask);
  280. }
  281. static void ioh_irq_disable(struct irq_data *d)
  282. {
  283. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  284. struct ioh_gpio *chip = gc->private;
  285. unsigned long flags;
  286. u32 ien;
  287. spin_lock_irqsave(&chip->spinlock, flags);
  288. ien = ioread32(&chip->reg->regs[chip->ch].ien);
  289. ien &= ~(1 << (d->irq - chip->irq_base));
  290. iowrite32(ien, &chip->reg->regs[chip->ch].ien);
  291. spin_unlock_irqrestore(&chip->spinlock, flags);
  292. }
  293. static void ioh_irq_enable(struct irq_data *d)
  294. {
  295. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  296. struct ioh_gpio *chip = gc->private;
  297. unsigned long flags;
  298. u32 ien;
  299. spin_lock_irqsave(&chip->spinlock, flags);
  300. ien = ioread32(&chip->reg->regs[chip->ch].ien);
  301. ien |= 1 << (d->irq - chip->irq_base);
  302. iowrite32(ien, &chip->reg->regs[chip->ch].ien);
  303. spin_unlock_irqrestore(&chip->spinlock, flags);
  304. }
  305. static irqreturn_t ioh_gpio_handler(int irq, void *dev_id)
  306. {
  307. struct ioh_gpio *chip = dev_id;
  308. u32 reg_val;
  309. int i, j;
  310. int ret = IRQ_NONE;
  311. for (i = 0; i < 8; i++, chip++) {
  312. reg_val = ioread32(&chip->reg->regs[i].istatus);
  313. for (j = 0; j < num_ports[i]; j++) {
  314. if (reg_val & BIT(j)) {
  315. dev_dbg(chip->dev,
  316. "%s:[%d]:irq=%d status=0x%x\n",
  317. __func__, j, irq, reg_val);
  318. iowrite32(BIT(j),
  319. &chip->reg->regs[chip->ch].iclr);
  320. generic_handle_irq(chip->irq_base + j);
  321. ret = IRQ_HANDLED;
  322. }
  323. }
  324. }
  325. return ret;
  326. }
  327. static int ioh_gpio_alloc_generic_chip(struct ioh_gpio *chip,
  328. unsigned int irq_start,
  329. unsigned int num)
  330. {
  331. struct irq_chip_generic *gc;
  332. struct irq_chip_type *ct;
  333. int rv;
  334. gc = devm_irq_alloc_generic_chip(chip->dev, "ioh_gpio", 1, irq_start,
  335. chip->base, handle_simple_irq);
  336. if (!gc)
  337. return -ENOMEM;
  338. gc->private = chip;
  339. ct = gc->chip_types;
  340. ct->chip.irq_mask = ioh_irq_mask;
  341. ct->chip.irq_unmask = ioh_irq_unmask;
  342. ct->chip.irq_set_type = ioh_irq_type;
  343. ct->chip.irq_disable = ioh_irq_disable;
  344. ct->chip.irq_enable = ioh_irq_enable;
  345. rv = devm_irq_setup_generic_chip(chip->dev, gc, IRQ_MSK(num),
  346. IRQ_GC_INIT_MASK_CACHE,
  347. IRQ_NOREQUEST | IRQ_NOPROBE, 0);
  348. return rv;
  349. }
  350. static int ioh_gpio_probe(struct pci_dev *pdev,
  351. const struct pci_device_id *id)
  352. {
  353. int ret;
  354. int i, j;
  355. struct ioh_gpio *chip;
  356. void __iomem *base;
  357. void *chip_save;
  358. int irq_base;
  359. ret = pci_enable_device(pdev);
  360. if (ret) {
  361. dev_err(&pdev->dev, "%s : pci_enable_device failed", __func__);
  362. goto err_pci_enable;
  363. }
  364. ret = pci_request_regions(pdev, KBUILD_MODNAME);
  365. if (ret) {
  366. dev_err(&pdev->dev, "pci_request_regions failed-%d", ret);
  367. goto err_request_regions;
  368. }
  369. base = pci_iomap(pdev, 1, 0);
  370. if (!base) {
  371. dev_err(&pdev->dev, "%s : pci_iomap failed", __func__);
  372. ret = -ENOMEM;
  373. goto err_iomap;
  374. }
  375. chip_save = kcalloc(8, sizeof(*chip), GFP_KERNEL);
  376. if (chip_save == NULL) {
  377. ret = -ENOMEM;
  378. goto err_kzalloc;
  379. }
  380. chip = chip_save;
  381. for (i = 0; i < 8; i++, chip++) {
  382. chip->dev = &pdev->dev;
  383. chip->base = base;
  384. chip->reg = chip->base;
  385. chip->ch = i;
  386. spin_lock_init(&chip->spinlock);
  387. ioh_gpio_setup(chip, num_ports[i]);
  388. ret = gpiochip_add_data(&chip->gpio, chip);
  389. if (ret) {
  390. dev_err(&pdev->dev, "IOH gpio: Failed to register GPIO\n");
  391. goto err_gpiochip_add;
  392. }
  393. }
  394. chip = chip_save;
  395. for (j = 0; j < 8; j++, chip++) {
  396. irq_base = devm_irq_alloc_descs(&pdev->dev, -1, IOH_IRQ_BASE,
  397. num_ports[j], NUMA_NO_NODE);
  398. if (irq_base < 0) {
  399. dev_warn(&pdev->dev,
  400. "ml_ioh_gpio: Failed to get IRQ base num\n");
  401. ret = irq_base;
  402. goto err_gpiochip_add;
  403. }
  404. chip->irq_base = irq_base;
  405. ret = ioh_gpio_alloc_generic_chip(chip,
  406. irq_base, num_ports[j]);
  407. if (ret)
  408. goto err_gpiochip_add;
  409. }
  410. chip = chip_save;
  411. ret = devm_request_irq(&pdev->dev, pdev->irq, ioh_gpio_handler,
  412. IRQF_SHARED, KBUILD_MODNAME, chip);
  413. if (ret != 0) {
  414. dev_err(&pdev->dev,
  415. "%s request_irq failed\n", __func__);
  416. goto err_gpiochip_add;
  417. }
  418. pci_set_drvdata(pdev, chip);
  419. return 0;
  420. err_gpiochip_add:
  421. chip = chip_save;
  422. while (--i >= 0) {
  423. gpiochip_remove(&chip->gpio);
  424. chip++;
  425. }
  426. kfree(chip_save);
  427. err_kzalloc:
  428. pci_iounmap(pdev, base);
  429. err_iomap:
  430. pci_release_regions(pdev);
  431. err_request_regions:
  432. pci_disable_device(pdev);
  433. err_pci_enable:
  434. dev_err(&pdev->dev, "%s Failed returns %d\n", __func__, ret);
  435. return ret;
  436. }
  437. static void ioh_gpio_remove(struct pci_dev *pdev)
  438. {
  439. int i;
  440. struct ioh_gpio *chip = pci_get_drvdata(pdev);
  441. void *chip_save;
  442. chip_save = chip;
  443. for (i = 0; i < 8; i++, chip++)
  444. gpiochip_remove(&chip->gpio);
  445. chip = chip_save;
  446. pci_iounmap(pdev, chip->base);
  447. pci_release_regions(pdev);
  448. pci_disable_device(pdev);
  449. kfree(chip);
  450. }
  451. #ifdef CONFIG_PM
  452. static int ioh_gpio_suspend(struct pci_dev *pdev, pm_message_t state)
  453. {
  454. s32 ret;
  455. struct ioh_gpio *chip = pci_get_drvdata(pdev);
  456. unsigned long flags;
  457. spin_lock_irqsave(&chip->spinlock, flags);
  458. ioh_gpio_save_reg_conf(chip);
  459. spin_unlock_irqrestore(&chip->spinlock, flags);
  460. ret = pci_save_state(pdev);
  461. if (ret) {
  462. dev_err(&pdev->dev, "pci_save_state Failed-%d\n", ret);
  463. return ret;
  464. }
  465. pci_disable_device(pdev);
  466. pci_set_power_state(pdev, PCI_D0);
  467. ret = pci_enable_wake(pdev, PCI_D0, 1);
  468. if (ret)
  469. dev_err(&pdev->dev, "pci_enable_wake Failed -%d\n", ret);
  470. return 0;
  471. }
  472. static int ioh_gpio_resume(struct pci_dev *pdev)
  473. {
  474. s32 ret;
  475. struct ioh_gpio *chip = pci_get_drvdata(pdev);
  476. unsigned long flags;
  477. ret = pci_enable_wake(pdev, PCI_D0, 0);
  478. pci_set_power_state(pdev, PCI_D0);
  479. ret = pci_enable_device(pdev);
  480. if (ret) {
  481. dev_err(&pdev->dev, "pci_enable_device Failed-%d ", ret);
  482. return ret;
  483. }
  484. pci_restore_state(pdev);
  485. spin_lock_irqsave(&chip->spinlock, flags);
  486. iowrite32(0x01, &chip->reg->srst);
  487. iowrite32(0x00, &chip->reg->srst);
  488. ioh_gpio_restore_reg_conf(chip);
  489. spin_unlock_irqrestore(&chip->spinlock, flags);
  490. return 0;
  491. }
  492. #else
  493. #define ioh_gpio_suspend NULL
  494. #define ioh_gpio_resume NULL
  495. #endif
  496. static const struct pci_device_id ioh_gpio_pcidev_id[] = {
  497. { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x802E) },
  498. { 0, }
  499. };
  500. MODULE_DEVICE_TABLE(pci, ioh_gpio_pcidev_id);
  501. static struct pci_driver ioh_gpio_driver = {
  502. .name = "ml_ioh_gpio",
  503. .id_table = ioh_gpio_pcidev_id,
  504. .probe = ioh_gpio_probe,
  505. .remove = ioh_gpio_remove,
  506. .suspend = ioh_gpio_suspend,
  507. .resume = ioh_gpio_resume
  508. };
  509. module_pci_driver(ioh_gpio_driver);
  510. MODULE_DESCRIPTION("OKI SEMICONDUCTOR ML-IOH series GPIO Driver");
  511. MODULE_LICENSE("GPL");