gpio-merrifield.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Intel Merrifield SoC GPIO driver
  4. *
  5. * Copyright (c) 2016 Intel Corporation.
  6. * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
  7. */
  8. #include <linux/acpi.h>
  9. #include <linux/bitops.h>
  10. #include <linux/gpio/driver.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/io.h>
  13. #include <linux/module.h>
  14. #include <linux/pci.h>
  15. #include <linux/pinctrl/consumer.h>
  16. #define GCCR 0x000 /* controller configuration */
  17. #define GPLR 0x004 /* pin level r/o */
  18. #define GPDR 0x01c /* pin direction */
  19. #define GPSR 0x034 /* pin set w/o */
  20. #define GPCR 0x04c /* pin clear w/o */
  21. #define GRER 0x064 /* rising edge detect */
  22. #define GFER 0x07c /* falling edge detect */
  23. #define GFBR 0x094 /* glitch filter bypass */
  24. #define GIMR 0x0ac /* interrupt mask */
  25. #define GISR 0x0c4 /* interrupt source */
  26. #define GITR 0x300 /* input type */
  27. #define GLPR 0x318 /* level input polarity */
  28. #define GWMR 0x400 /* wake mask */
  29. #define GWSR 0x418 /* wake source */
  30. #define GSIR 0xc00 /* secure input */
  31. /* Intel Merrifield has 192 GPIO pins */
  32. #define MRFLD_NGPIO 192
  33. struct mrfld_gpio_pinrange {
  34. unsigned int gpio_base;
  35. unsigned int pin_base;
  36. unsigned int npins;
  37. };
  38. #define GPIO_PINRANGE(gstart, gend, pstart) \
  39. { \
  40. .gpio_base = (gstart), \
  41. .pin_base = (pstart), \
  42. .npins = (gend) - (gstart) + 1, \
  43. }
  44. struct mrfld_gpio {
  45. struct gpio_chip chip;
  46. void __iomem *reg_base;
  47. raw_spinlock_t lock;
  48. struct device *dev;
  49. };
  50. static const struct mrfld_gpio_pinrange mrfld_gpio_ranges[] = {
  51. GPIO_PINRANGE(0, 11, 146),
  52. GPIO_PINRANGE(12, 13, 144),
  53. GPIO_PINRANGE(14, 15, 35),
  54. GPIO_PINRANGE(16, 16, 164),
  55. GPIO_PINRANGE(17, 18, 105),
  56. GPIO_PINRANGE(19, 22, 101),
  57. GPIO_PINRANGE(23, 30, 107),
  58. GPIO_PINRANGE(32, 43, 67),
  59. GPIO_PINRANGE(44, 63, 195),
  60. GPIO_PINRANGE(64, 67, 140),
  61. GPIO_PINRANGE(68, 69, 165),
  62. GPIO_PINRANGE(70, 71, 65),
  63. GPIO_PINRANGE(72, 76, 228),
  64. GPIO_PINRANGE(77, 86, 37),
  65. GPIO_PINRANGE(87, 87, 48),
  66. GPIO_PINRANGE(88, 88, 47),
  67. GPIO_PINRANGE(89, 96, 49),
  68. GPIO_PINRANGE(97, 97, 34),
  69. GPIO_PINRANGE(102, 119, 83),
  70. GPIO_PINRANGE(120, 123, 79),
  71. GPIO_PINRANGE(124, 135, 115),
  72. GPIO_PINRANGE(137, 142, 158),
  73. GPIO_PINRANGE(154, 163, 24),
  74. GPIO_PINRANGE(164, 176, 215),
  75. GPIO_PINRANGE(177, 189, 127),
  76. GPIO_PINRANGE(190, 191, 178),
  77. };
  78. static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned int offset,
  79. unsigned int reg_type_offset)
  80. {
  81. struct mrfld_gpio *priv = gpiochip_get_data(chip);
  82. u8 reg = offset / 32;
  83. return priv->reg_base + reg_type_offset + reg * 4;
  84. }
  85. static int mrfld_gpio_get(struct gpio_chip *chip, unsigned int offset)
  86. {
  87. void __iomem *gplr = gpio_reg(chip, offset, GPLR);
  88. return !!(readl(gplr) & BIT(offset % 32));
  89. }
  90. static void mrfld_gpio_set(struct gpio_chip *chip, unsigned int offset,
  91. int value)
  92. {
  93. struct mrfld_gpio *priv = gpiochip_get_data(chip);
  94. void __iomem *gpsr, *gpcr;
  95. unsigned long flags;
  96. raw_spin_lock_irqsave(&priv->lock, flags);
  97. if (value) {
  98. gpsr = gpio_reg(chip, offset, GPSR);
  99. writel(BIT(offset % 32), gpsr);
  100. } else {
  101. gpcr = gpio_reg(chip, offset, GPCR);
  102. writel(BIT(offset % 32), gpcr);
  103. }
  104. raw_spin_unlock_irqrestore(&priv->lock, flags);
  105. }
  106. static int mrfld_gpio_direction_input(struct gpio_chip *chip,
  107. unsigned int offset)
  108. {
  109. struct mrfld_gpio *priv = gpiochip_get_data(chip);
  110. void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
  111. unsigned long flags;
  112. u32 value;
  113. raw_spin_lock_irqsave(&priv->lock, flags);
  114. value = readl(gpdr);
  115. value &= ~BIT(offset % 32);
  116. writel(value, gpdr);
  117. raw_spin_unlock_irqrestore(&priv->lock, flags);
  118. return 0;
  119. }
  120. static int mrfld_gpio_direction_output(struct gpio_chip *chip,
  121. unsigned int offset, int value)
  122. {
  123. struct mrfld_gpio *priv = gpiochip_get_data(chip);
  124. void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
  125. unsigned long flags;
  126. mrfld_gpio_set(chip, offset, value);
  127. raw_spin_lock_irqsave(&priv->lock, flags);
  128. value = readl(gpdr);
  129. value |= BIT(offset % 32);
  130. writel(value, gpdr);
  131. raw_spin_unlock_irqrestore(&priv->lock, flags);
  132. return 0;
  133. }
  134. static int mrfld_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
  135. {
  136. void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
  137. if (readl(gpdr) & BIT(offset % 32))
  138. return GPIO_LINE_DIRECTION_OUT;
  139. return GPIO_LINE_DIRECTION_IN;
  140. }
  141. static int mrfld_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset,
  142. unsigned int debounce)
  143. {
  144. struct mrfld_gpio *priv = gpiochip_get_data(chip);
  145. void __iomem *gfbr = gpio_reg(chip, offset, GFBR);
  146. unsigned long flags;
  147. u32 value;
  148. raw_spin_lock_irqsave(&priv->lock, flags);
  149. if (debounce)
  150. value = readl(gfbr) & ~BIT(offset % 32);
  151. else
  152. value = readl(gfbr) | BIT(offset % 32);
  153. writel(value, gfbr);
  154. raw_spin_unlock_irqrestore(&priv->lock, flags);
  155. return 0;
  156. }
  157. static int mrfld_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
  158. unsigned long config)
  159. {
  160. u32 debounce;
  161. if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
  162. return -ENOTSUPP;
  163. debounce = pinconf_to_config_argument(config);
  164. return mrfld_gpio_set_debounce(chip, offset, debounce);
  165. }
  166. static void mrfld_irq_ack(struct irq_data *d)
  167. {
  168. struct mrfld_gpio *priv = irq_data_get_irq_chip_data(d);
  169. u32 gpio = irqd_to_hwirq(d);
  170. void __iomem *gisr = gpio_reg(&priv->chip, gpio, GISR);
  171. unsigned long flags;
  172. raw_spin_lock_irqsave(&priv->lock, flags);
  173. writel(BIT(gpio % 32), gisr);
  174. raw_spin_unlock_irqrestore(&priv->lock, flags);
  175. }
  176. static void mrfld_irq_unmask_mask(struct irq_data *d, bool unmask)
  177. {
  178. struct mrfld_gpio *priv = irq_data_get_irq_chip_data(d);
  179. u32 gpio = irqd_to_hwirq(d);
  180. void __iomem *gimr = gpio_reg(&priv->chip, gpio, GIMR);
  181. unsigned long flags;
  182. u32 value;
  183. raw_spin_lock_irqsave(&priv->lock, flags);
  184. if (unmask)
  185. value = readl(gimr) | BIT(gpio % 32);
  186. else
  187. value = readl(gimr) & ~BIT(gpio % 32);
  188. writel(value, gimr);
  189. raw_spin_unlock_irqrestore(&priv->lock, flags);
  190. }
  191. static void mrfld_irq_mask(struct irq_data *d)
  192. {
  193. mrfld_irq_unmask_mask(d, false);
  194. }
  195. static void mrfld_irq_unmask(struct irq_data *d)
  196. {
  197. mrfld_irq_unmask_mask(d, true);
  198. }
  199. static int mrfld_irq_set_type(struct irq_data *d, unsigned int type)
  200. {
  201. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  202. struct mrfld_gpio *priv = gpiochip_get_data(gc);
  203. u32 gpio = irqd_to_hwirq(d);
  204. void __iomem *grer = gpio_reg(&priv->chip, gpio, GRER);
  205. void __iomem *gfer = gpio_reg(&priv->chip, gpio, GFER);
  206. void __iomem *gitr = gpio_reg(&priv->chip, gpio, GITR);
  207. void __iomem *glpr = gpio_reg(&priv->chip, gpio, GLPR);
  208. unsigned long flags;
  209. u32 value;
  210. raw_spin_lock_irqsave(&priv->lock, flags);
  211. if (type & IRQ_TYPE_EDGE_RISING)
  212. value = readl(grer) | BIT(gpio % 32);
  213. else
  214. value = readl(grer) & ~BIT(gpio % 32);
  215. writel(value, grer);
  216. if (type & IRQ_TYPE_EDGE_FALLING)
  217. value = readl(gfer) | BIT(gpio % 32);
  218. else
  219. value = readl(gfer) & ~BIT(gpio % 32);
  220. writel(value, gfer);
  221. /*
  222. * To prevent glitches from triggering an unintended level interrupt,
  223. * configure GLPR register first and then configure GITR.
  224. */
  225. if (type & IRQ_TYPE_LEVEL_LOW)
  226. value = readl(glpr) | BIT(gpio % 32);
  227. else
  228. value = readl(glpr) & ~BIT(gpio % 32);
  229. writel(value, glpr);
  230. if (type & IRQ_TYPE_LEVEL_MASK) {
  231. value = readl(gitr) | BIT(gpio % 32);
  232. writel(value, gitr);
  233. irq_set_handler_locked(d, handle_level_irq);
  234. } else if (type & IRQ_TYPE_EDGE_BOTH) {
  235. value = readl(gitr) & ~BIT(gpio % 32);
  236. writel(value, gitr);
  237. irq_set_handler_locked(d, handle_edge_irq);
  238. }
  239. raw_spin_unlock_irqrestore(&priv->lock, flags);
  240. return 0;
  241. }
  242. static int mrfld_irq_set_wake(struct irq_data *d, unsigned int on)
  243. {
  244. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  245. struct mrfld_gpio *priv = gpiochip_get_data(gc);
  246. u32 gpio = irqd_to_hwirq(d);
  247. void __iomem *gwmr = gpio_reg(&priv->chip, gpio, GWMR);
  248. void __iomem *gwsr = gpio_reg(&priv->chip, gpio, GWSR);
  249. unsigned long flags;
  250. u32 value;
  251. raw_spin_lock_irqsave(&priv->lock, flags);
  252. /* Clear the existing wake status */
  253. writel(BIT(gpio % 32), gwsr);
  254. if (on)
  255. value = readl(gwmr) | BIT(gpio % 32);
  256. else
  257. value = readl(gwmr) & ~BIT(gpio % 32);
  258. writel(value, gwmr);
  259. raw_spin_unlock_irqrestore(&priv->lock, flags);
  260. dev_dbg(priv->dev, "%sable wake for gpio %u\n", on ? "en" : "dis", gpio);
  261. return 0;
  262. }
  263. static struct irq_chip mrfld_irqchip = {
  264. .name = "gpio-merrifield",
  265. .irq_ack = mrfld_irq_ack,
  266. .irq_mask = mrfld_irq_mask,
  267. .irq_unmask = mrfld_irq_unmask,
  268. .irq_set_type = mrfld_irq_set_type,
  269. .irq_set_wake = mrfld_irq_set_wake,
  270. };
  271. static void mrfld_irq_handler(struct irq_desc *desc)
  272. {
  273. struct gpio_chip *gc = irq_desc_get_handler_data(desc);
  274. struct mrfld_gpio *priv = gpiochip_get_data(gc);
  275. struct irq_chip *irqchip = irq_desc_get_chip(desc);
  276. unsigned long base, gpio;
  277. chained_irq_enter(irqchip, desc);
  278. /* Check GPIO controller to check which pin triggered the interrupt */
  279. for (base = 0; base < priv->chip.ngpio; base += 32) {
  280. void __iomem *gisr = gpio_reg(&priv->chip, base, GISR);
  281. void __iomem *gimr = gpio_reg(&priv->chip, base, GIMR);
  282. unsigned long pending, enabled;
  283. pending = readl(gisr);
  284. enabled = readl(gimr);
  285. /* Only interrupts that are enabled */
  286. pending &= enabled;
  287. for_each_set_bit(gpio, &pending, 32) {
  288. unsigned int irq;
  289. irq = irq_find_mapping(gc->irq.domain, base + gpio);
  290. generic_handle_irq(irq);
  291. }
  292. }
  293. chained_irq_exit(irqchip, desc);
  294. }
  295. static int mrfld_irq_init_hw(struct gpio_chip *chip)
  296. {
  297. struct mrfld_gpio *priv = gpiochip_get_data(chip);
  298. void __iomem *reg;
  299. unsigned int base;
  300. for (base = 0; base < priv->chip.ngpio; base += 32) {
  301. /* Clear the rising-edge detect register */
  302. reg = gpio_reg(&priv->chip, base, GRER);
  303. writel(0, reg);
  304. /* Clear the falling-edge detect register */
  305. reg = gpio_reg(&priv->chip, base, GFER);
  306. writel(0, reg);
  307. }
  308. return 0;
  309. }
  310. static const char *mrfld_gpio_get_pinctrl_dev_name(struct mrfld_gpio *priv)
  311. {
  312. struct acpi_device *adev;
  313. const char *name;
  314. adev = acpi_dev_get_first_match_dev("INTC1002", NULL, -1);
  315. if (adev) {
  316. name = devm_kstrdup(priv->dev, acpi_dev_name(adev), GFP_KERNEL);
  317. acpi_dev_put(adev);
  318. } else {
  319. name = "pinctrl-merrifield";
  320. }
  321. return name;
  322. }
  323. static int mrfld_gpio_add_pin_ranges(struct gpio_chip *chip)
  324. {
  325. struct mrfld_gpio *priv = gpiochip_get_data(chip);
  326. const struct mrfld_gpio_pinrange *range;
  327. const char *pinctrl_dev_name;
  328. unsigned int i;
  329. int retval;
  330. pinctrl_dev_name = mrfld_gpio_get_pinctrl_dev_name(priv);
  331. for (i = 0; i < ARRAY_SIZE(mrfld_gpio_ranges); i++) {
  332. range = &mrfld_gpio_ranges[i];
  333. retval = gpiochip_add_pin_range(&priv->chip, pinctrl_dev_name,
  334. range->gpio_base,
  335. range->pin_base,
  336. range->npins);
  337. if (retval) {
  338. dev_err(priv->dev, "failed to add GPIO pin range\n");
  339. return retval;
  340. }
  341. }
  342. return 0;
  343. }
  344. static int mrfld_gpio_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  345. {
  346. struct gpio_irq_chip *girq;
  347. struct mrfld_gpio *priv;
  348. u32 gpio_base, irq_base;
  349. void __iomem *base;
  350. int retval;
  351. retval = pcim_enable_device(pdev);
  352. if (retval)
  353. return retval;
  354. retval = pcim_iomap_regions(pdev, BIT(1) | BIT(0), pci_name(pdev));
  355. if (retval) {
  356. dev_err(&pdev->dev, "I/O memory mapping error\n");
  357. return retval;
  358. }
  359. base = pcim_iomap_table(pdev)[1];
  360. irq_base = readl(base + 0 * sizeof(u32));
  361. gpio_base = readl(base + 1 * sizeof(u32));
  362. /* Release the IO mapping, since we already get the info from BAR1 */
  363. pcim_iounmap_regions(pdev, BIT(1));
  364. priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
  365. if (!priv)
  366. return -ENOMEM;
  367. priv->dev = &pdev->dev;
  368. priv->reg_base = pcim_iomap_table(pdev)[0];
  369. priv->chip.label = dev_name(&pdev->dev);
  370. priv->chip.parent = &pdev->dev;
  371. priv->chip.request = gpiochip_generic_request;
  372. priv->chip.free = gpiochip_generic_free;
  373. priv->chip.direction_input = mrfld_gpio_direction_input;
  374. priv->chip.direction_output = mrfld_gpio_direction_output;
  375. priv->chip.get = mrfld_gpio_get;
  376. priv->chip.set = mrfld_gpio_set;
  377. priv->chip.get_direction = mrfld_gpio_get_direction;
  378. priv->chip.set_config = mrfld_gpio_set_config;
  379. priv->chip.base = gpio_base;
  380. priv->chip.ngpio = MRFLD_NGPIO;
  381. priv->chip.can_sleep = false;
  382. priv->chip.add_pin_ranges = mrfld_gpio_add_pin_ranges;
  383. raw_spin_lock_init(&priv->lock);
  384. retval = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
  385. if (retval < 0)
  386. return retval;
  387. girq = &priv->chip.irq;
  388. girq->chip = &mrfld_irqchip;
  389. girq->init_hw = mrfld_irq_init_hw;
  390. girq->parent_handler = mrfld_irq_handler;
  391. girq->num_parents = 1;
  392. girq->parents = devm_kcalloc(&pdev->dev, girq->num_parents,
  393. sizeof(*girq->parents), GFP_KERNEL);
  394. if (!girq->parents)
  395. return -ENOMEM;
  396. girq->parents[0] = pci_irq_vector(pdev, 0);
  397. girq->first = irq_base;
  398. girq->default_type = IRQ_TYPE_NONE;
  399. girq->handler = handle_bad_irq;
  400. retval = devm_gpiochip_add_data(&pdev->dev, &priv->chip, priv);
  401. if (retval) {
  402. dev_err(&pdev->dev, "gpiochip_add error %d\n", retval);
  403. return retval;
  404. }
  405. pci_set_drvdata(pdev, priv);
  406. return 0;
  407. }
  408. static const struct pci_device_id mrfld_gpio_ids[] = {
  409. { PCI_VDEVICE(INTEL, 0x1199) },
  410. { }
  411. };
  412. MODULE_DEVICE_TABLE(pci, mrfld_gpio_ids);
  413. static struct pci_driver mrfld_gpio_driver = {
  414. .name = "gpio-merrifield",
  415. .id_table = mrfld_gpio_ids,
  416. .probe = mrfld_gpio_probe,
  417. };
  418. module_pci_driver(mrfld_gpio_driver);
  419. MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
  420. MODULE_DESCRIPTION("Intel Merrifield SoC GPIO driver");
  421. MODULE_LICENSE("GPL v2");