gpio-max77620.c 9.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * MAXIM MAX77620 GPIO driver
  4. *
  5. * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
  6. */
  7. #include <linux/gpio/driver.h>
  8. #include <linux/interrupt.h>
  9. #include <linux/mfd/max77620.h>
  10. #include <linux/module.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/regmap.h>
  13. #define GPIO_REG_ADDR(offset) (MAX77620_REG_GPIO0 + offset)
  14. struct max77620_gpio {
  15. struct gpio_chip gpio_chip;
  16. struct regmap *rmap;
  17. struct device *dev;
  18. struct mutex buslock; /* irq_bus_lock */
  19. unsigned int irq_type[MAX77620_GPIO_NR];
  20. bool irq_enabled[MAX77620_GPIO_NR];
  21. };
  22. static irqreturn_t max77620_gpio_irqhandler(int irq, void *data)
  23. {
  24. struct max77620_gpio *gpio = data;
  25. unsigned int value, offset;
  26. unsigned long pending;
  27. int err;
  28. err = regmap_read(gpio->rmap, MAX77620_REG_IRQ_LVL2_GPIO, &value);
  29. if (err < 0) {
  30. dev_err(gpio->dev, "REG_IRQ_LVL2_GPIO read failed: %d\n", err);
  31. return IRQ_NONE;
  32. }
  33. pending = value;
  34. for_each_set_bit(offset, &pending, MAX77620_GPIO_NR) {
  35. unsigned int virq;
  36. virq = irq_find_mapping(gpio->gpio_chip.irq.domain, offset);
  37. handle_nested_irq(virq);
  38. }
  39. return IRQ_HANDLED;
  40. }
  41. static void max77620_gpio_irq_mask(struct irq_data *data)
  42. {
  43. struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
  44. struct max77620_gpio *gpio = gpiochip_get_data(chip);
  45. gpio->irq_enabled[data->hwirq] = false;
  46. }
  47. static void max77620_gpio_irq_unmask(struct irq_data *data)
  48. {
  49. struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
  50. struct max77620_gpio *gpio = gpiochip_get_data(chip);
  51. gpio->irq_enabled[data->hwirq] = true;
  52. }
  53. static int max77620_gpio_set_irq_type(struct irq_data *data, unsigned int type)
  54. {
  55. struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
  56. struct max77620_gpio *gpio = gpiochip_get_data(chip);
  57. unsigned int irq_type;
  58. switch (type) {
  59. case IRQ_TYPE_EDGE_RISING:
  60. irq_type = MAX77620_CNFG_GPIO_INT_RISING;
  61. break;
  62. case IRQ_TYPE_EDGE_FALLING:
  63. irq_type = MAX77620_CNFG_GPIO_INT_FALLING;
  64. break;
  65. case IRQ_TYPE_EDGE_BOTH:
  66. irq_type = MAX77620_CNFG_GPIO_INT_RISING |
  67. MAX77620_CNFG_GPIO_INT_FALLING;
  68. break;
  69. default:
  70. return -EINVAL;
  71. }
  72. gpio->irq_type[data->hwirq] = irq_type;
  73. return 0;
  74. }
  75. static void max77620_gpio_bus_lock(struct irq_data *data)
  76. {
  77. struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
  78. struct max77620_gpio *gpio = gpiochip_get_data(chip);
  79. mutex_lock(&gpio->buslock);
  80. }
  81. static void max77620_gpio_bus_sync_unlock(struct irq_data *data)
  82. {
  83. struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
  84. struct max77620_gpio *gpio = gpiochip_get_data(chip);
  85. unsigned int value, offset = data->hwirq;
  86. int err;
  87. value = gpio->irq_enabled[offset] ? gpio->irq_type[offset] : 0;
  88. err = regmap_update_bits(gpio->rmap, GPIO_REG_ADDR(offset),
  89. MAX77620_CNFG_GPIO_INT_MASK, value);
  90. if (err < 0)
  91. dev_err(chip->parent, "failed to update interrupt mask: %d\n",
  92. err);
  93. mutex_unlock(&gpio->buslock);
  94. }
  95. static struct irq_chip max77620_gpio_irqchip = {
  96. .name = "max77620-gpio",
  97. .irq_mask = max77620_gpio_irq_mask,
  98. .irq_unmask = max77620_gpio_irq_unmask,
  99. .irq_set_type = max77620_gpio_set_irq_type,
  100. .irq_bus_lock = max77620_gpio_bus_lock,
  101. .irq_bus_sync_unlock = max77620_gpio_bus_sync_unlock,
  102. .flags = IRQCHIP_MASK_ON_SUSPEND,
  103. };
  104. static int max77620_gpio_dir_input(struct gpio_chip *gc, unsigned int offset)
  105. {
  106. struct max77620_gpio *mgpio = gpiochip_get_data(gc);
  107. int ret;
  108. ret = regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
  109. MAX77620_CNFG_GPIO_DIR_MASK,
  110. MAX77620_CNFG_GPIO_DIR_INPUT);
  111. if (ret < 0)
  112. dev_err(mgpio->dev, "CNFG_GPIOx dir update failed: %d\n", ret);
  113. return ret;
  114. }
  115. static int max77620_gpio_get(struct gpio_chip *gc, unsigned int offset)
  116. {
  117. struct max77620_gpio *mgpio = gpiochip_get_data(gc);
  118. unsigned int val;
  119. int ret;
  120. ret = regmap_read(mgpio->rmap, GPIO_REG_ADDR(offset), &val);
  121. if (ret < 0) {
  122. dev_err(mgpio->dev, "CNFG_GPIOx read failed: %d\n", ret);
  123. return ret;
  124. }
  125. if (val & MAX77620_CNFG_GPIO_DIR_MASK)
  126. return !!(val & MAX77620_CNFG_GPIO_INPUT_VAL_MASK);
  127. else
  128. return !!(val & MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK);
  129. }
  130. static int max77620_gpio_dir_output(struct gpio_chip *gc, unsigned int offset,
  131. int value)
  132. {
  133. struct max77620_gpio *mgpio = gpiochip_get_data(gc);
  134. u8 val;
  135. int ret;
  136. val = (value) ? MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH :
  137. MAX77620_CNFG_GPIO_OUTPUT_VAL_LOW;
  138. ret = regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
  139. MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK, val);
  140. if (ret < 0) {
  141. dev_err(mgpio->dev, "CNFG_GPIOx val update failed: %d\n", ret);
  142. return ret;
  143. }
  144. ret = regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
  145. MAX77620_CNFG_GPIO_DIR_MASK,
  146. MAX77620_CNFG_GPIO_DIR_OUTPUT);
  147. if (ret < 0)
  148. dev_err(mgpio->dev, "CNFG_GPIOx dir update failed: %d\n", ret);
  149. return ret;
  150. }
  151. static int max77620_gpio_set_debounce(struct max77620_gpio *mgpio,
  152. unsigned int offset,
  153. unsigned int debounce)
  154. {
  155. u8 val;
  156. int ret;
  157. switch (debounce) {
  158. case 0:
  159. val = MAX77620_CNFG_GPIO_DBNC_None;
  160. break;
  161. case 1 ... 8000:
  162. val = MAX77620_CNFG_GPIO_DBNC_8ms;
  163. break;
  164. case 8001 ... 16000:
  165. val = MAX77620_CNFG_GPIO_DBNC_16ms;
  166. break;
  167. case 16001 ... 32000:
  168. val = MAX77620_CNFG_GPIO_DBNC_32ms;
  169. break;
  170. default:
  171. dev_err(mgpio->dev, "Illegal value %u\n", debounce);
  172. return -EINVAL;
  173. }
  174. ret = regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
  175. MAX77620_CNFG_GPIO_DBNC_MASK, val);
  176. if (ret < 0)
  177. dev_err(mgpio->dev, "CNFG_GPIOx_DBNC update failed: %d\n", ret);
  178. return ret;
  179. }
  180. static void max77620_gpio_set(struct gpio_chip *gc, unsigned int offset,
  181. int value)
  182. {
  183. struct max77620_gpio *mgpio = gpiochip_get_data(gc);
  184. u8 val;
  185. int ret;
  186. val = (value) ? MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH :
  187. MAX77620_CNFG_GPIO_OUTPUT_VAL_LOW;
  188. ret = regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
  189. MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK, val);
  190. if (ret < 0)
  191. dev_err(mgpio->dev, "CNFG_GPIO_OUT update failed: %d\n", ret);
  192. }
  193. static int max77620_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
  194. unsigned long config)
  195. {
  196. struct max77620_gpio *mgpio = gpiochip_get_data(gc);
  197. switch (pinconf_to_config_param(config)) {
  198. case PIN_CONFIG_DRIVE_OPEN_DRAIN:
  199. return regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
  200. MAX77620_CNFG_GPIO_DRV_MASK,
  201. MAX77620_CNFG_GPIO_DRV_OPENDRAIN);
  202. case PIN_CONFIG_DRIVE_PUSH_PULL:
  203. return regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
  204. MAX77620_CNFG_GPIO_DRV_MASK,
  205. MAX77620_CNFG_GPIO_DRV_PUSHPULL);
  206. case PIN_CONFIG_INPUT_DEBOUNCE:
  207. return max77620_gpio_set_debounce(mgpio, offset,
  208. pinconf_to_config_argument(config));
  209. default:
  210. break;
  211. }
  212. return -ENOTSUPP;
  213. }
  214. static int max77620_gpio_irq_init_hw(struct gpio_chip *gc)
  215. {
  216. struct max77620_gpio *gpio = gpiochip_get_data(gc);
  217. unsigned int i;
  218. int err;
  219. /*
  220. * GPIO interrupts may be left ON after bootloader, hence let's
  221. * pre-initialize hardware to the expected state by disabling all
  222. * the interrupts.
  223. */
  224. for (i = 0; i < MAX77620_GPIO_NR; i++) {
  225. err = regmap_update_bits(gpio->rmap, GPIO_REG_ADDR(i),
  226. MAX77620_CNFG_GPIO_INT_MASK, 0);
  227. if (err < 0) {
  228. dev_err(gpio->dev,
  229. "failed to disable interrupt: %d\n", err);
  230. return err;
  231. }
  232. }
  233. return 0;
  234. }
  235. static int max77620_gpio_probe(struct platform_device *pdev)
  236. {
  237. struct max77620_chip *chip = dev_get_drvdata(pdev->dev.parent);
  238. struct max77620_gpio *mgpio;
  239. struct gpio_irq_chip *girq;
  240. unsigned int gpio_irq;
  241. int ret;
  242. ret = platform_get_irq(pdev, 0);
  243. if (ret < 0)
  244. return ret;
  245. gpio_irq = ret;
  246. mgpio = devm_kzalloc(&pdev->dev, sizeof(*mgpio), GFP_KERNEL);
  247. if (!mgpio)
  248. return -ENOMEM;
  249. mutex_init(&mgpio->buslock);
  250. mgpio->rmap = chip->rmap;
  251. mgpio->dev = &pdev->dev;
  252. mgpio->gpio_chip.label = pdev->name;
  253. mgpio->gpio_chip.parent = pdev->dev.parent;
  254. mgpio->gpio_chip.direction_input = max77620_gpio_dir_input;
  255. mgpio->gpio_chip.get = max77620_gpio_get;
  256. mgpio->gpio_chip.direction_output = max77620_gpio_dir_output;
  257. mgpio->gpio_chip.set = max77620_gpio_set;
  258. mgpio->gpio_chip.set_config = max77620_gpio_set_config;
  259. mgpio->gpio_chip.ngpio = MAX77620_GPIO_NR;
  260. mgpio->gpio_chip.can_sleep = 1;
  261. mgpio->gpio_chip.base = -1;
  262. girq = &mgpio->gpio_chip.irq;
  263. girq->chip = &max77620_gpio_irqchip;
  264. /* This will let us handle the parent IRQ in the driver */
  265. girq->parent_handler = NULL;
  266. girq->num_parents = 0;
  267. girq->parents = NULL;
  268. girq->default_type = IRQ_TYPE_NONE;
  269. girq->handler = handle_edge_irq;
  270. girq->init_hw = max77620_gpio_irq_init_hw,
  271. girq->threaded = true;
  272. platform_set_drvdata(pdev, mgpio);
  273. ret = devm_gpiochip_add_data(&pdev->dev, &mgpio->gpio_chip, mgpio);
  274. if (ret < 0) {
  275. dev_err(&pdev->dev, "gpio_init: Failed to add max77620_gpio\n");
  276. return ret;
  277. }
  278. ret = devm_request_threaded_irq(&pdev->dev, gpio_irq, NULL,
  279. max77620_gpio_irqhandler, IRQF_ONESHOT,
  280. "max77620-gpio", mgpio);
  281. if (ret < 0) {
  282. dev_err(&pdev->dev, "failed to request IRQ: %d\n", ret);
  283. return ret;
  284. }
  285. return 0;
  286. }
  287. static const struct platform_device_id max77620_gpio_devtype[] = {
  288. { .name = "max77620-gpio", },
  289. { .name = "max20024-gpio", },
  290. {},
  291. };
  292. MODULE_DEVICE_TABLE(platform, max77620_gpio_devtype);
  293. static struct platform_driver max77620_gpio_driver = {
  294. .driver.name = "max77620-gpio",
  295. .probe = max77620_gpio_probe,
  296. .id_table = max77620_gpio_devtype,
  297. };
  298. module_platform_driver(max77620_gpio_driver);
  299. MODULE_DESCRIPTION("GPIO interface for MAX77620 and MAX20024 PMIC");
  300. MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
  301. MODULE_AUTHOR("Chaitanya Bandi <bandik@nvidia.com>");
  302. MODULE_ALIAS("platform:max77620-gpio");
  303. MODULE_LICENSE("GPL v2");