gpio-max3191x.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * gpio-max3191x.c - GPIO driver for Maxim MAX3191x industrial serializer
  4. *
  5. * Copyright (C) 2017 KUNBUS GmbH
  6. *
  7. * The MAX3191x makes 8 digital 24V inputs available via SPI.
  8. * Multiple chips can be daisy-chained, the spec does not impose
  9. * a limit on the number of chips and neither does this driver.
  10. *
  11. * Either of two modes is selectable: In 8-bit mode, only the state
  12. * of the inputs is clocked out to achieve high readout speeds;
  13. * In 16-bit mode, an additional status byte is clocked out with
  14. * a CRC and indicator bits for undervoltage and overtemperature.
  15. * The driver returns an error instead of potentially bogus data
  16. * if any of these fault conditions occur. However it does allow
  17. * readout of non-faulting chips in the same daisy-chain.
  18. *
  19. * MAX3191x supports four debounce settings and the driver is
  20. * capable of configuring these differently for each chip in the
  21. * daisy-chain.
  22. *
  23. * If the chips are hardwired to 8-bit mode ("modesel" pulled high),
  24. * gpio-pisosr.c can be used alternatively to this driver.
  25. *
  26. * https://datasheets.maximintegrated.com/en/ds/MAX31910.pdf
  27. * https://datasheets.maximintegrated.com/en/ds/MAX31911.pdf
  28. * https://datasheets.maximintegrated.com/en/ds/MAX31912.pdf
  29. * https://datasheets.maximintegrated.com/en/ds/MAX31913.pdf
  30. * https://datasheets.maximintegrated.com/en/ds/MAX31953-MAX31963.pdf
  31. */
  32. #include <linux/bitmap.h>
  33. #include <linux/bitops.h>
  34. #include <linux/crc8.h>
  35. #include <linux/gpio/consumer.h>
  36. #include <linux/gpio/driver.h>
  37. #include <linux/module.h>
  38. #include <linux/spi/spi.h>
  39. enum max3191x_mode {
  40. STATUS_BYTE_ENABLED,
  41. STATUS_BYTE_DISABLED,
  42. };
  43. /**
  44. * struct max3191x_chip - max3191x daisy-chain
  45. * @gpio: GPIO controller struct
  46. * @lock: protects read sequences
  47. * @nchips: number of chips in the daisy-chain
  48. * @mode: current mode, 0 for 16-bit, 1 for 8-bit;
  49. * for simplicity, all chips in the daisy-chain are assumed
  50. * to use the same mode
  51. * @modesel_pins: GPIO pins to configure modesel of each chip
  52. * @fault_pins: GPIO pins to detect fault of each chip
  53. * @db0_pins: GPIO pins to configure debounce of each chip
  54. * @db1_pins: GPIO pins to configure debounce of each chip
  55. * @mesg: SPI message to perform a readout
  56. * @xfer: SPI transfer used by @mesg
  57. * @crc_error: bitmap signaling CRC error for each chip
  58. * @overtemp: bitmap signaling overtemperature alarm for each chip
  59. * @undervolt1: bitmap signaling undervoltage alarm for each chip
  60. * @undervolt2: bitmap signaling undervoltage warning for each chip
  61. * @fault: bitmap signaling assertion of @fault_pins for each chip
  62. * @ignore_uv: whether to ignore undervoltage alarms;
  63. * set by a device property if the chips are powered through
  64. * 5VOUT instead of VCC24V, in which case they will constantly
  65. * signal undervoltage;
  66. * for simplicity, all chips in the daisy-chain are assumed
  67. * to be powered the same way
  68. */
  69. struct max3191x_chip {
  70. struct gpio_chip gpio;
  71. struct mutex lock;
  72. u32 nchips;
  73. enum max3191x_mode mode;
  74. struct gpio_descs *modesel_pins;
  75. struct gpio_descs *fault_pins;
  76. struct gpio_descs *db0_pins;
  77. struct gpio_descs *db1_pins;
  78. struct spi_message mesg;
  79. struct spi_transfer xfer;
  80. unsigned long *crc_error;
  81. unsigned long *overtemp;
  82. unsigned long *undervolt1;
  83. unsigned long *undervolt2;
  84. unsigned long *fault;
  85. bool ignore_uv;
  86. };
  87. #define MAX3191X_NGPIO 8
  88. #define MAX3191X_CRC8_POLYNOMIAL 0xa8 /* (x^5) + x^4 + x^2 + x^0 */
  89. DECLARE_CRC8_TABLE(max3191x_crc8);
  90. static int max3191x_get_direction(struct gpio_chip *gpio, unsigned int offset)
  91. {
  92. return GPIO_LINE_DIRECTION_IN; /* always in */
  93. }
  94. static int max3191x_direction_input(struct gpio_chip *gpio, unsigned int offset)
  95. {
  96. return 0;
  97. }
  98. static int max3191x_direction_output(struct gpio_chip *gpio,
  99. unsigned int offset, int value)
  100. {
  101. return -EINVAL;
  102. }
  103. static void max3191x_set(struct gpio_chip *gpio, unsigned int offset, int value)
  104. { }
  105. static void max3191x_set_multiple(struct gpio_chip *gpio, unsigned long *mask,
  106. unsigned long *bits)
  107. { }
  108. static unsigned int max3191x_wordlen(struct max3191x_chip *max3191x)
  109. {
  110. return max3191x->mode == STATUS_BYTE_ENABLED ? 2 : 1;
  111. }
  112. static int max3191x_readout_locked(struct max3191x_chip *max3191x)
  113. {
  114. struct device *dev = max3191x->gpio.parent;
  115. struct spi_device *spi = to_spi_device(dev);
  116. int val, i, ot = 0, uv1 = 0;
  117. val = spi_sync(spi, &max3191x->mesg);
  118. if (val) {
  119. dev_err_ratelimited(dev, "SPI receive error %d\n", val);
  120. return val;
  121. }
  122. for (i = 0; i < max3191x->nchips; i++) {
  123. if (max3191x->mode == STATUS_BYTE_ENABLED) {
  124. u8 in = ((u8 *)max3191x->xfer.rx_buf)[i * 2];
  125. u8 status = ((u8 *)max3191x->xfer.rx_buf)[i * 2 + 1];
  126. val = (status & 0xf8) != crc8(max3191x_crc8, &in, 1, 0);
  127. __assign_bit(i, max3191x->crc_error, val);
  128. if (val)
  129. dev_err_ratelimited(dev,
  130. "chip %d: CRC error\n", i);
  131. ot = (status >> 1) & 1;
  132. __assign_bit(i, max3191x->overtemp, ot);
  133. if (ot)
  134. dev_err_ratelimited(dev,
  135. "chip %d: overtemperature\n", i);
  136. if (!max3191x->ignore_uv) {
  137. uv1 = !((status >> 2) & 1);
  138. __assign_bit(i, max3191x->undervolt1, uv1);
  139. if (uv1)
  140. dev_err_ratelimited(dev,
  141. "chip %d: undervoltage\n", i);
  142. val = !(status & 1);
  143. __assign_bit(i, max3191x->undervolt2, val);
  144. if (val && !uv1)
  145. dev_warn_ratelimited(dev,
  146. "chip %d: voltage warn\n", i);
  147. }
  148. }
  149. if (max3191x->fault_pins && !max3191x->ignore_uv) {
  150. /* fault pin shared by all chips or per chip */
  151. struct gpio_desc *fault_pin =
  152. (max3191x->fault_pins->ndescs == 1)
  153. ? max3191x->fault_pins->desc[0]
  154. : max3191x->fault_pins->desc[i];
  155. val = gpiod_get_value_cansleep(fault_pin);
  156. if (val < 0) {
  157. dev_err_ratelimited(dev,
  158. "GPIO read error %d\n", val);
  159. return val;
  160. }
  161. __assign_bit(i, max3191x->fault, val);
  162. if (val && !uv1 && !ot)
  163. dev_err_ratelimited(dev,
  164. "chip %d: fault\n", i);
  165. }
  166. }
  167. return 0;
  168. }
  169. static bool max3191x_chip_is_faulting(struct max3191x_chip *max3191x,
  170. unsigned int chipnum)
  171. {
  172. /* without status byte the only diagnostic is the fault pin */
  173. if (!max3191x->ignore_uv && test_bit(chipnum, max3191x->fault))
  174. return true;
  175. if (max3191x->mode == STATUS_BYTE_DISABLED)
  176. return false;
  177. return test_bit(chipnum, max3191x->crc_error) ||
  178. test_bit(chipnum, max3191x->overtemp) ||
  179. (!max3191x->ignore_uv &&
  180. test_bit(chipnum, max3191x->undervolt1));
  181. }
  182. static int max3191x_get(struct gpio_chip *gpio, unsigned int offset)
  183. {
  184. struct max3191x_chip *max3191x = gpiochip_get_data(gpio);
  185. int ret, chipnum, wordlen = max3191x_wordlen(max3191x);
  186. u8 in;
  187. mutex_lock(&max3191x->lock);
  188. ret = max3191x_readout_locked(max3191x);
  189. if (ret)
  190. goto out_unlock;
  191. chipnum = offset / MAX3191X_NGPIO;
  192. if (max3191x_chip_is_faulting(max3191x, chipnum)) {
  193. ret = -EIO;
  194. goto out_unlock;
  195. }
  196. in = ((u8 *)max3191x->xfer.rx_buf)[chipnum * wordlen];
  197. ret = (in >> (offset % MAX3191X_NGPIO)) & 1;
  198. out_unlock:
  199. mutex_unlock(&max3191x->lock);
  200. return ret;
  201. }
  202. static int max3191x_get_multiple(struct gpio_chip *gpio, unsigned long *mask,
  203. unsigned long *bits)
  204. {
  205. struct max3191x_chip *max3191x = gpiochip_get_data(gpio);
  206. const unsigned int wordlen = max3191x_wordlen(max3191x);
  207. int ret;
  208. unsigned long bit;
  209. unsigned long gpio_mask;
  210. unsigned long in;
  211. mutex_lock(&max3191x->lock);
  212. ret = max3191x_readout_locked(max3191x);
  213. if (ret)
  214. goto out_unlock;
  215. bitmap_zero(bits, gpio->ngpio);
  216. for_each_set_clump8(bit, gpio_mask, mask, gpio->ngpio) {
  217. unsigned int chipnum = bit / MAX3191X_NGPIO;
  218. if (max3191x_chip_is_faulting(max3191x, chipnum)) {
  219. ret = -EIO;
  220. goto out_unlock;
  221. }
  222. in = ((u8 *)max3191x->xfer.rx_buf)[chipnum * wordlen];
  223. in &= gpio_mask;
  224. bitmap_set_value8(bits, in, bit);
  225. }
  226. out_unlock:
  227. mutex_unlock(&max3191x->lock);
  228. return ret;
  229. }
  230. static int max3191x_set_config(struct gpio_chip *gpio, unsigned int offset,
  231. unsigned long config)
  232. {
  233. struct max3191x_chip *max3191x = gpiochip_get_data(gpio);
  234. u32 debounce, chipnum, db0_val, db1_val;
  235. if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
  236. return -ENOTSUPP;
  237. if (!max3191x->db0_pins || !max3191x->db1_pins)
  238. return -EINVAL;
  239. debounce = pinconf_to_config_argument(config);
  240. switch (debounce) {
  241. case 0:
  242. db0_val = 0;
  243. db1_val = 0;
  244. break;
  245. case 1 ... 25:
  246. db0_val = 0;
  247. db1_val = 1;
  248. break;
  249. case 26 ... 750:
  250. db0_val = 1;
  251. db1_val = 0;
  252. break;
  253. case 751 ... 3000:
  254. db0_val = 1;
  255. db1_val = 1;
  256. break;
  257. default:
  258. return -EINVAL;
  259. }
  260. if (max3191x->db0_pins->ndescs == 1)
  261. chipnum = 0; /* all chips use the same pair of debounce pins */
  262. else
  263. chipnum = offset / MAX3191X_NGPIO; /* per chip debounce pins */
  264. mutex_lock(&max3191x->lock);
  265. gpiod_set_value_cansleep(max3191x->db0_pins->desc[chipnum], db0_val);
  266. gpiod_set_value_cansleep(max3191x->db1_pins->desc[chipnum], db1_val);
  267. mutex_unlock(&max3191x->lock);
  268. return 0;
  269. }
  270. static void gpiod_set_array_single_value_cansleep(unsigned int ndescs,
  271. struct gpio_desc **desc,
  272. struct gpio_array *info,
  273. int value)
  274. {
  275. unsigned long *values;
  276. values = bitmap_alloc(ndescs, GFP_KERNEL);
  277. if (!values)
  278. return;
  279. if (value)
  280. bitmap_fill(values, ndescs);
  281. else
  282. bitmap_zero(values, ndescs);
  283. gpiod_set_array_value_cansleep(ndescs, desc, info, values);
  284. kfree(values);
  285. }
  286. static struct gpio_descs *devm_gpiod_get_array_optional_count(
  287. struct device *dev, const char *con_id,
  288. enum gpiod_flags flags, unsigned int expected)
  289. {
  290. struct gpio_descs *descs;
  291. int found = gpiod_count(dev, con_id);
  292. if (found == -ENOENT)
  293. return NULL;
  294. if (found != expected && found != 1) {
  295. dev_err(dev, "ignoring %s-gpios: found %d, expected %u or 1\n",
  296. con_id, found, expected);
  297. return NULL;
  298. }
  299. descs = devm_gpiod_get_array_optional(dev, con_id, flags);
  300. if (IS_ERR(descs)) {
  301. dev_err(dev, "failed to get %s-gpios: %ld\n",
  302. con_id, PTR_ERR(descs));
  303. return NULL;
  304. }
  305. return descs;
  306. }
  307. static int max3191x_probe(struct spi_device *spi)
  308. {
  309. struct device *dev = &spi->dev;
  310. struct max3191x_chip *max3191x;
  311. int n, ret;
  312. max3191x = devm_kzalloc(dev, sizeof(*max3191x), GFP_KERNEL);
  313. if (!max3191x)
  314. return -ENOMEM;
  315. spi_set_drvdata(spi, max3191x);
  316. max3191x->nchips = 1;
  317. device_property_read_u32(dev, "#daisy-chained-devices",
  318. &max3191x->nchips);
  319. n = BITS_TO_LONGS(max3191x->nchips);
  320. max3191x->crc_error = devm_kcalloc(dev, n, sizeof(long), GFP_KERNEL);
  321. max3191x->undervolt1 = devm_kcalloc(dev, n, sizeof(long), GFP_KERNEL);
  322. max3191x->undervolt2 = devm_kcalloc(dev, n, sizeof(long), GFP_KERNEL);
  323. max3191x->overtemp = devm_kcalloc(dev, n, sizeof(long), GFP_KERNEL);
  324. max3191x->fault = devm_kcalloc(dev, n, sizeof(long), GFP_KERNEL);
  325. max3191x->xfer.rx_buf = devm_kcalloc(dev, max3191x->nchips,
  326. 2, GFP_KERNEL);
  327. if (!max3191x->crc_error || !max3191x->undervolt1 ||
  328. !max3191x->overtemp || !max3191x->undervolt2 ||
  329. !max3191x->fault || !max3191x->xfer.rx_buf)
  330. return -ENOMEM;
  331. max3191x->modesel_pins = devm_gpiod_get_array_optional_count(dev,
  332. "maxim,modesel", GPIOD_ASIS, max3191x->nchips);
  333. max3191x->fault_pins = devm_gpiod_get_array_optional_count(dev,
  334. "maxim,fault", GPIOD_IN, max3191x->nchips);
  335. max3191x->db0_pins = devm_gpiod_get_array_optional_count(dev,
  336. "maxim,db0", GPIOD_OUT_LOW, max3191x->nchips);
  337. max3191x->db1_pins = devm_gpiod_get_array_optional_count(dev,
  338. "maxim,db1", GPIOD_OUT_LOW, max3191x->nchips);
  339. max3191x->mode = device_property_read_bool(dev, "maxim,modesel-8bit")
  340. ? STATUS_BYTE_DISABLED : STATUS_BYTE_ENABLED;
  341. if (max3191x->modesel_pins)
  342. gpiod_set_array_single_value_cansleep(
  343. max3191x->modesel_pins->ndescs,
  344. max3191x->modesel_pins->desc,
  345. max3191x->modesel_pins->info, max3191x->mode);
  346. max3191x->ignore_uv = device_property_read_bool(dev,
  347. "maxim,ignore-undervoltage");
  348. if (max3191x->db0_pins && max3191x->db1_pins &&
  349. max3191x->db0_pins->ndescs != max3191x->db1_pins->ndescs) {
  350. dev_err(dev, "ignoring maxim,db*-gpios: array len mismatch\n");
  351. devm_gpiod_put_array(dev, max3191x->db0_pins);
  352. devm_gpiod_put_array(dev, max3191x->db1_pins);
  353. max3191x->db0_pins = NULL;
  354. max3191x->db1_pins = NULL;
  355. }
  356. max3191x->xfer.len = max3191x->nchips * max3191x_wordlen(max3191x);
  357. spi_message_init_with_transfers(&max3191x->mesg, &max3191x->xfer, 1);
  358. max3191x->gpio.label = spi->modalias;
  359. max3191x->gpio.owner = THIS_MODULE;
  360. max3191x->gpio.parent = dev;
  361. max3191x->gpio.base = -1;
  362. max3191x->gpio.ngpio = max3191x->nchips * MAX3191X_NGPIO;
  363. max3191x->gpio.can_sleep = true;
  364. max3191x->gpio.get_direction = max3191x_get_direction;
  365. max3191x->gpio.direction_input = max3191x_direction_input;
  366. max3191x->gpio.direction_output = max3191x_direction_output;
  367. max3191x->gpio.set = max3191x_set;
  368. max3191x->gpio.set_multiple = max3191x_set_multiple;
  369. max3191x->gpio.get = max3191x_get;
  370. max3191x->gpio.get_multiple = max3191x_get_multiple;
  371. max3191x->gpio.set_config = max3191x_set_config;
  372. mutex_init(&max3191x->lock);
  373. ret = gpiochip_add_data(&max3191x->gpio, max3191x);
  374. if (ret) {
  375. mutex_destroy(&max3191x->lock);
  376. return ret;
  377. }
  378. return 0;
  379. }
  380. static int max3191x_remove(struct spi_device *spi)
  381. {
  382. struct max3191x_chip *max3191x = spi_get_drvdata(spi);
  383. gpiochip_remove(&max3191x->gpio);
  384. mutex_destroy(&max3191x->lock);
  385. return 0;
  386. }
  387. static int __init max3191x_register_driver(struct spi_driver *sdrv)
  388. {
  389. crc8_populate_msb(max3191x_crc8, MAX3191X_CRC8_POLYNOMIAL);
  390. return spi_register_driver(sdrv);
  391. }
  392. #ifdef CONFIG_OF
  393. static const struct of_device_id max3191x_of_id[] = {
  394. { .compatible = "maxim,max31910" },
  395. { .compatible = "maxim,max31911" },
  396. { .compatible = "maxim,max31912" },
  397. { .compatible = "maxim,max31913" },
  398. { .compatible = "maxim,max31953" },
  399. { .compatible = "maxim,max31963" },
  400. { }
  401. };
  402. MODULE_DEVICE_TABLE(of, max3191x_of_id);
  403. #endif
  404. static const struct spi_device_id max3191x_spi_id[] = {
  405. { "max31910" },
  406. { "max31911" },
  407. { "max31912" },
  408. { "max31913" },
  409. { "max31953" },
  410. { "max31963" },
  411. { }
  412. };
  413. MODULE_DEVICE_TABLE(spi, max3191x_spi_id);
  414. static struct spi_driver max3191x_driver = {
  415. .driver = {
  416. .name = "max3191x",
  417. .of_match_table = of_match_ptr(max3191x_of_id),
  418. },
  419. .probe = max3191x_probe,
  420. .remove = max3191x_remove,
  421. .id_table = max3191x_spi_id,
  422. };
  423. module_driver(max3191x_driver, max3191x_register_driver, spi_unregister_driver);
  424. MODULE_AUTHOR("Lukas Wunner <lukas@wunner.de>");
  425. MODULE_DESCRIPTION("GPIO driver for Maxim MAX3191x industrial serializer");
  426. MODULE_LICENSE("GPL v2");