gpio-lpc18xx.c 9.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * GPIO driver for NXP LPC18xx/43xx.
  4. *
  5. * Copyright (C) 2018 Vladimir Zapolskiy <vz@mleia.com>
  6. * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
  7. *
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/gpio/driver.h>
  11. #include <linux/io.h>
  12. #include <linux/irqdomain.h>
  13. #include <linux/module.h>
  14. #include <linux/of.h>
  15. #include <linux/of_address.h>
  16. #include <linux/of_gpio.h>
  17. #include <linux/of_irq.h>
  18. #include <linux/pinctrl/consumer.h>
  19. #include <linux/platform_device.h>
  20. /* LPC18xx GPIO register offsets */
  21. #define LPC18XX_REG_DIR(n) (0x2000 + n * sizeof(u32))
  22. #define LPC18XX_MAX_PORTS 8
  23. #define LPC18XX_PINS_PER_PORT 32
  24. /* LPC18xx GPIO pin interrupt controller register offsets */
  25. #define LPC18XX_GPIO_PIN_IC_ISEL 0x00
  26. #define LPC18XX_GPIO_PIN_IC_IENR 0x04
  27. #define LPC18XX_GPIO_PIN_IC_SIENR 0x08
  28. #define LPC18XX_GPIO_PIN_IC_CIENR 0x0c
  29. #define LPC18XX_GPIO_PIN_IC_IENF 0x10
  30. #define LPC18XX_GPIO_PIN_IC_SIENF 0x14
  31. #define LPC18XX_GPIO_PIN_IC_CIENF 0x18
  32. #define LPC18XX_GPIO_PIN_IC_RISE 0x1c
  33. #define LPC18XX_GPIO_PIN_IC_FALL 0x20
  34. #define LPC18XX_GPIO_PIN_IC_IST 0x24
  35. #define NR_LPC18XX_GPIO_PIN_IC_IRQS 8
  36. struct lpc18xx_gpio_pin_ic {
  37. void __iomem *base;
  38. struct irq_domain *domain;
  39. struct raw_spinlock lock;
  40. };
  41. struct lpc18xx_gpio_chip {
  42. struct gpio_chip gpio;
  43. void __iomem *base;
  44. struct clk *clk;
  45. struct lpc18xx_gpio_pin_ic *pin_ic;
  46. spinlock_t lock;
  47. };
  48. static inline void lpc18xx_gpio_pin_ic_isel(struct lpc18xx_gpio_pin_ic *ic,
  49. u32 pin, bool set)
  50. {
  51. u32 val = readl_relaxed(ic->base + LPC18XX_GPIO_PIN_IC_ISEL);
  52. if (set)
  53. val &= ~BIT(pin);
  54. else
  55. val |= BIT(pin);
  56. writel_relaxed(val, ic->base + LPC18XX_GPIO_PIN_IC_ISEL);
  57. }
  58. static inline void lpc18xx_gpio_pin_ic_set(struct lpc18xx_gpio_pin_ic *ic,
  59. u32 pin, u32 reg)
  60. {
  61. writel_relaxed(BIT(pin), ic->base + reg);
  62. }
  63. static void lpc18xx_gpio_pin_ic_mask(struct irq_data *d)
  64. {
  65. struct lpc18xx_gpio_pin_ic *ic = d->chip_data;
  66. u32 type = irqd_get_trigger_type(d);
  67. raw_spin_lock(&ic->lock);
  68. if (type & IRQ_TYPE_LEVEL_MASK || type & IRQ_TYPE_EDGE_RISING)
  69. lpc18xx_gpio_pin_ic_set(ic, d->hwirq,
  70. LPC18XX_GPIO_PIN_IC_CIENR);
  71. if (type & IRQ_TYPE_EDGE_FALLING)
  72. lpc18xx_gpio_pin_ic_set(ic, d->hwirq,
  73. LPC18XX_GPIO_PIN_IC_CIENF);
  74. raw_spin_unlock(&ic->lock);
  75. irq_chip_mask_parent(d);
  76. }
  77. static void lpc18xx_gpio_pin_ic_unmask(struct irq_data *d)
  78. {
  79. struct lpc18xx_gpio_pin_ic *ic = d->chip_data;
  80. u32 type = irqd_get_trigger_type(d);
  81. raw_spin_lock(&ic->lock);
  82. if (type & IRQ_TYPE_LEVEL_MASK || type & IRQ_TYPE_EDGE_RISING)
  83. lpc18xx_gpio_pin_ic_set(ic, d->hwirq,
  84. LPC18XX_GPIO_PIN_IC_SIENR);
  85. if (type & IRQ_TYPE_EDGE_FALLING)
  86. lpc18xx_gpio_pin_ic_set(ic, d->hwirq,
  87. LPC18XX_GPIO_PIN_IC_SIENF);
  88. raw_spin_unlock(&ic->lock);
  89. irq_chip_unmask_parent(d);
  90. }
  91. static void lpc18xx_gpio_pin_ic_eoi(struct irq_data *d)
  92. {
  93. struct lpc18xx_gpio_pin_ic *ic = d->chip_data;
  94. u32 type = irqd_get_trigger_type(d);
  95. raw_spin_lock(&ic->lock);
  96. if (type & IRQ_TYPE_EDGE_BOTH)
  97. lpc18xx_gpio_pin_ic_set(ic, d->hwirq,
  98. LPC18XX_GPIO_PIN_IC_IST);
  99. raw_spin_unlock(&ic->lock);
  100. irq_chip_eoi_parent(d);
  101. }
  102. static int lpc18xx_gpio_pin_ic_set_type(struct irq_data *d, unsigned int type)
  103. {
  104. struct lpc18xx_gpio_pin_ic *ic = d->chip_data;
  105. raw_spin_lock(&ic->lock);
  106. if (type & IRQ_TYPE_LEVEL_HIGH) {
  107. lpc18xx_gpio_pin_ic_isel(ic, d->hwirq, true);
  108. lpc18xx_gpio_pin_ic_set(ic, d->hwirq,
  109. LPC18XX_GPIO_PIN_IC_SIENF);
  110. } else if (type & IRQ_TYPE_LEVEL_LOW) {
  111. lpc18xx_gpio_pin_ic_isel(ic, d->hwirq, true);
  112. lpc18xx_gpio_pin_ic_set(ic, d->hwirq,
  113. LPC18XX_GPIO_PIN_IC_CIENF);
  114. } else {
  115. lpc18xx_gpio_pin_ic_isel(ic, d->hwirq, false);
  116. }
  117. raw_spin_unlock(&ic->lock);
  118. return 0;
  119. }
  120. static struct irq_chip lpc18xx_gpio_pin_ic = {
  121. .name = "LPC18xx GPIO pin",
  122. .irq_mask = lpc18xx_gpio_pin_ic_mask,
  123. .irq_unmask = lpc18xx_gpio_pin_ic_unmask,
  124. .irq_eoi = lpc18xx_gpio_pin_ic_eoi,
  125. .irq_set_type = lpc18xx_gpio_pin_ic_set_type,
  126. .flags = IRQCHIP_SET_TYPE_MASKED,
  127. };
  128. static int lpc18xx_gpio_pin_ic_domain_alloc(struct irq_domain *domain,
  129. unsigned int virq,
  130. unsigned int nr_irqs, void *data)
  131. {
  132. struct irq_fwspec parent_fwspec, *fwspec = data;
  133. struct lpc18xx_gpio_pin_ic *ic = domain->host_data;
  134. irq_hw_number_t hwirq;
  135. int ret;
  136. if (nr_irqs != 1)
  137. return -EINVAL;
  138. hwirq = fwspec->param[0];
  139. if (hwirq >= NR_LPC18XX_GPIO_PIN_IC_IRQS)
  140. return -EINVAL;
  141. /*
  142. * All LPC18xx/LPC43xx GPIO pin hardware interrupts are translated
  143. * into edge interrupts 32...39 on parent Cortex-M3/M4 NVIC
  144. */
  145. parent_fwspec.fwnode = domain->parent->fwnode;
  146. parent_fwspec.param_count = 1;
  147. parent_fwspec.param[0] = hwirq + 32;
  148. ret = irq_domain_alloc_irqs_parent(domain, virq, 1, &parent_fwspec);
  149. if (ret < 0) {
  150. pr_err("failed to allocate parent irq %u: %d\n",
  151. parent_fwspec.param[0], ret);
  152. return ret;
  153. }
  154. return irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
  155. &lpc18xx_gpio_pin_ic, ic);
  156. }
  157. static const struct irq_domain_ops lpc18xx_gpio_pin_ic_domain_ops = {
  158. .alloc = lpc18xx_gpio_pin_ic_domain_alloc,
  159. .xlate = irq_domain_xlate_twocell,
  160. .free = irq_domain_free_irqs_common,
  161. };
  162. static int lpc18xx_gpio_pin_ic_probe(struct lpc18xx_gpio_chip *gc)
  163. {
  164. struct device *dev = gc->gpio.parent;
  165. struct irq_domain *parent_domain;
  166. struct device_node *parent_node;
  167. struct lpc18xx_gpio_pin_ic *ic;
  168. struct resource res;
  169. int ret, index;
  170. parent_node = of_irq_find_parent(dev->of_node);
  171. if (!parent_node)
  172. return -ENXIO;
  173. parent_domain = irq_find_host(parent_node);
  174. of_node_put(parent_node);
  175. if (!parent_domain)
  176. return -ENXIO;
  177. ic = devm_kzalloc(dev, sizeof(*ic), GFP_KERNEL);
  178. if (!ic)
  179. return -ENOMEM;
  180. index = of_property_match_string(dev->of_node, "reg-names",
  181. "gpio-pin-ic");
  182. if (index < 0) {
  183. ret = -ENODEV;
  184. goto free_ic;
  185. }
  186. ret = of_address_to_resource(dev->of_node, index, &res);
  187. if (ret < 0)
  188. goto free_ic;
  189. ic->base = devm_ioremap_resource(dev, &res);
  190. if (IS_ERR(ic->base)) {
  191. ret = PTR_ERR(ic->base);
  192. goto free_ic;
  193. }
  194. raw_spin_lock_init(&ic->lock);
  195. ic->domain = irq_domain_add_hierarchy(parent_domain, 0,
  196. NR_LPC18XX_GPIO_PIN_IC_IRQS,
  197. dev->of_node,
  198. &lpc18xx_gpio_pin_ic_domain_ops,
  199. ic);
  200. if (!ic->domain) {
  201. pr_err("unable to add irq domain\n");
  202. ret = -ENODEV;
  203. goto free_iomap;
  204. }
  205. gc->pin_ic = ic;
  206. return 0;
  207. free_iomap:
  208. devm_iounmap(dev, ic->base);
  209. free_ic:
  210. devm_kfree(dev, ic);
  211. return ret;
  212. }
  213. static void lpc18xx_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
  214. {
  215. struct lpc18xx_gpio_chip *gc = gpiochip_get_data(chip);
  216. writeb(value ? 1 : 0, gc->base + offset);
  217. }
  218. static int lpc18xx_gpio_get(struct gpio_chip *chip, unsigned offset)
  219. {
  220. struct lpc18xx_gpio_chip *gc = gpiochip_get_data(chip);
  221. return !!readb(gc->base + offset);
  222. }
  223. static int lpc18xx_gpio_direction(struct gpio_chip *chip, unsigned offset,
  224. bool out)
  225. {
  226. struct lpc18xx_gpio_chip *gc = gpiochip_get_data(chip);
  227. unsigned long flags;
  228. u32 port, pin, dir;
  229. port = offset / LPC18XX_PINS_PER_PORT;
  230. pin = offset % LPC18XX_PINS_PER_PORT;
  231. spin_lock_irqsave(&gc->lock, flags);
  232. dir = readl(gc->base + LPC18XX_REG_DIR(port));
  233. if (out)
  234. dir |= BIT(pin);
  235. else
  236. dir &= ~BIT(pin);
  237. writel(dir, gc->base + LPC18XX_REG_DIR(port));
  238. spin_unlock_irqrestore(&gc->lock, flags);
  239. return 0;
  240. }
  241. static int lpc18xx_gpio_direction_input(struct gpio_chip *chip,
  242. unsigned offset)
  243. {
  244. return lpc18xx_gpio_direction(chip, offset, false);
  245. }
  246. static int lpc18xx_gpio_direction_output(struct gpio_chip *chip,
  247. unsigned offset, int value)
  248. {
  249. lpc18xx_gpio_set(chip, offset, value);
  250. return lpc18xx_gpio_direction(chip, offset, true);
  251. }
  252. static const struct gpio_chip lpc18xx_chip = {
  253. .label = "lpc18xx/43xx-gpio",
  254. .request = gpiochip_generic_request,
  255. .free = gpiochip_generic_free,
  256. .direction_input = lpc18xx_gpio_direction_input,
  257. .direction_output = lpc18xx_gpio_direction_output,
  258. .set = lpc18xx_gpio_set,
  259. .get = lpc18xx_gpio_get,
  260. .ngpio = LPC18XX_MAX_PORTS * LPC18XX_PINS_PER_PORT,
  261. .owner = THIS_MODULE,
  262. };
  263. static int lpc18xx_gpio_probe(struct platform_device *pdev)
  264. {
  265. struct device *dev = &pdev->dev;
  266. struct lpc18xx_gpio_chip *gc;
  267. int index, ret;
  268. gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL);
  269. if (!gc)
  270. return -ENOMEM;
  271. gc->gpio = lpc18xx_chip;
  272. platform_set_drvdata(pdev, gc);
  273. index = of_property_match_string(dev->of_node, "reg-names", "gpio");
  274. if (index < 0) {
  275. /* To support backward compatibility take the first resource */
  276. gc->base = devm_platform_ioremap_resource(pdev, 0);
  277. } else {
  278. struct resource res;
  279. ret = of_address_to_resource(dev->of_node, index, &res);
  280. if (ret < 0)
  281. return ret;
  282. gc->base = devm_ioremap_resource(dev, &res);
  283. }
  284. if (IS_ERR(gc->base))
  285. return PTR_ERR(gc->base);
  286. gc->clk = devm_clk_get(dev, NULL);
  287. if (IS_ERR(gc->clk)) {
  288. dev_err(dev, "input clock not found\n");
  289. return PTR_ERR(gc->clk);
  290. }
  291. ret = clk_prepare_enable(gc->clk);
  292. if (ret) {
  293. dev_err(dev, "unable to enable clock\n");
  294. return ret;
  295. }
  296. spin_lock_init(&gc->lock);
  297. gc->gpio.parent = dev;
  298. ret = devm_gpiochip_add_data(dev, &gc->gpio, gc);
  299. if (ret) {
  300. dev_err(dev, "failed to add gpio chip\n");
  301. clk_disable_unprepare(gc->clk);
  302. return ret;
  303. }
  304. /* On error GPIO pin interrupt controller just won't be registered */
  305. lpc18xx_gpio_pin_ic_probe(gc);
  306. return 0;
  307. }
  308. static int lpc18xx_gpio_remove(struct platform_device *pdev)
  309. {
  310. struct lpc18xx_gpio_chip *gc = platform_get_drvdata(pdev);
  311. if (gc->pin_ic)
  312. irq_domain_remove(gc->pin_ic->domain);
  313. clk_disable_unprepare(gc->clk);
  314. return 0;
  315. }
  316. static const struct of_device_id lpc18xx_gpio_match[] = {
  317. { .compatible = "nxp,lpc1850-gpio" },
  318. { }
  319. };
  320. MODULE_DEVICE_TABLE(of, lpc18xx_gpio_match);
  321. static struct platform_driver lpc18xx_gpio_driver = {
  322. .probe = lpc18xx_gpio_probe,
  323. .remove = lpc18xx_gpio_remove,
  324. .driver = {
  325. .name = "lpc18xx-gpio",
  326. .of_match_table = lpc18xx_gpio_match,
  327. },
  328. };
  329. module_platform_driver(lpc18xx_gpio_driver);
  330. MODULE_AUTHOR("Joachim Eastwood <manabian@gmail.com>");
  331. MODULE_AUTHOR("Vladimir Zapolskiy <vz@mleia.com>");
  332. MODULE_DESCRIPTION("GPIO driver for LPC18xx/43xx");
  333. MODULE_LICENSE("GPL v2");