gpio-ixp4xx.c 8.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // IXP4 GPIO driver
  4. // Copyright (C) 2019 Linus Walleij <linus.walleij@linaro.org>
  5. //
  6. // based on previous work and know-how from:
  7. // Deepak Saxena <dsaxena@plexity.net>
  8. #include <linux/gpio/driver.h>
  9. #include <linux/io.h>
  10. #include <linux/irq.h>
  11. #include <linux/irqdomain.h>
  12. #include <linux/irqchip.h>
  13. #include <linux/of_irq.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/bitops.h>
  16. /* Include that go away with DT transition */
  17. #include <linux/irqchip/irq-ixp4xx.h>
  18. #include <asm/mach-types.h>
  19. #define IXP4XX_REG_GPOUT 0x00
  20. #define IXP4XX_REG_GPOE 0x04
  21. #define IXP4XX_REG_GPIN 0x08
  22. #define IXP4XX_REG_GPIS 0x0C
  23. #define IXP4XX_REG_GPIT1 0x10
  24. #define IXP4XX_REG_GPIT2 0x14
  25. #define IXP4XX_REG_GPCLK 0x18
  26. #define IXP4XX_REG_GPDBSEL 0x1C
  27. /*
  28. * The hardware uses 3 bits to indicate interrupt "style".
  29. * we clear and set these three bits accordingly. The lower 24
  30. * bits in two registers (GPIT1 and GPIT2) are used to set up
  31. * the style for 8 lines each for a total of 16 GPIO lines.
  32. */
  33. #define IXP4XX_GPIO_STYLE_ACTIVE_HIGH 0x0
  34. #define IXP4XX_GPIO_STYLE_ACTIVE_LOW 0x1
  35. #define IXP4XX_GPIO_STYLE_RISING_EDGE 0x2
  36. #define IXP4XX_GPIO_STYLE_FALLING_EDGE 0x3
  37. #define IXP4XX_GPIO_STYLE_TRANSITIONAL 0x4
  38. #define IXP4XX_GPIO_STYLE_MASK GENMASK(2, 0)
  39. #define IXP4XX_GPIO_STYLE_SIZE 3
  40. /**
  41. * struct ixp4xx_gpio - IXP4 GPIO state container
  42. * @dev: containing device for this instance
  43. * @fwnode: the fwnode for this GPIO chip
  44. * @gc: gpiochip for this instance
  45. * @base: remapped I/O-memory base
  46. * @irq_edge: Each bit represents an IRQ: 1: edge-triggered,
  47. * 0: level triggered
  48. */
  49. struct ixp4xx_gpio {
  50. struct device *dev;
  51. struct fwnode_handle *fwnode;
  52. struct gpio_chip gc;
  53. void __iomem *base;
  54. unsigned long long irq_edge;
  55. };
  56. static void ixp4xx_gpio_irq_ack(struct irq_data *d)
  57. {
  58. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  59. struct ixp4xx_gpio *g = gpiochip_get_data(gc);
  60. __raw_writel(BIT(d->hwirq), g->base + IXP4XX_REG_GPIS);
  61. }
  62. static void ixp4xx_gpio_irq_unmask(struct irq_data *d)
  63. {
  64. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  65. struct ixp4xx_gpio *g = gpiochip_get_data(gc);
  66. /* ACK when unmasking if not edge-triggered */
  67. if (!(g->irq_edge & BIT(d->hwirq)))
  68. ixp4xx_gpio_irq_ack(d);
  69. irq_chip_unmask_parent(d);
  70. }
  71. static int ixp4xx_gpio_irq_set_type(struct irq_data *d, unsigned int type)
  72. {
  73. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  74. struct ixp4xx_gpio *g = gpiochip_get_data(gc);
  75. int line = d->hwirq;
  76. unsigned long flags;
  77. u32 int_style;
  78. u32 int_reg;
  79. u32 val;
  80. switch (type) {
  81. case IRQ_TYPE_EDGE_BOTH:
  82. irq_set_handler_locked(d, handle_edge_irq);
  83. int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL;
  84. g->irq_edge |= BIT(d->hwirq);
  85. break;
  86. case IRQ_TYPE_EDGE_RISING:
  87. irq_set_handler_locked(d, handle_edge_irq);
  88. int_style = IXP4XX_GPIO_STYLE_RISING_EDGE;
  89. g->irq_edge |= BIT(d->hwirq);
  90. break;
  91. case IRQ_TYPE_EDGE_FALLING:
  92. irq_set_handler_locked(d, handle_edge_irq);
  93. int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE;
  94. g->irq_edge |= BIT(d->hwirq);
  95. break;
  96. case IRQ_TYPE_LEVEL_HIGH:
  97. irq_set_handler_locked(d, handle_level_irq);
  98. int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
  99. g->irq_edge &= ~BIT(d->hwirq);
  100. break;
  101. case IRQ_TYPE_LEVEL_LOW:
  102. irq_set_handler_locked(d, handle_level_irq);
  103. int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW;
  104. g->irq_edge &= ~BIT(d->hwirq);
  105. break;
  106. default:
  107. return -EINVAL;
  108. }
  109. if (line >= 8) {
  110. /* pins 8-15 */
  111. line -= 8;
  112. int_reg = IXP4XX_REG_GPIT2;
  113. } else {
  114. /* pins 0-7 */
  115. int_reg = IXP4XX_REG_GPIT1;
  116. }
  117. spin_lock_irqsave(&g->gc.bgpio_lock, flags);
  118. /* Clear the style for the appropriate pin */
  119. val = __raw_readl(g->base + int_reg);
  120. val &= ~(IXP4XX_GPIO_STYLE_MASK << (line * IXP4XX_GPIO_STYLE_SIZE));
  121. __raw_writel(val, g->base + int_reg);
  122. __raw_writel(BIT(line), g->base + IXP4XX_REG_GPIS);
  123. /* Set the new style */
  124. val = __raw_readl(g->base + int_reg);
  125. val |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE));
  126. __raw_writel(val, g->base + int_reg);
  127. /* Force-configure this line as an input */
  128. val = __raw_readl(g->base + IXP4XX_REG_GPOE);
  129. val |= BIT(d->hwirq);
  130. __raw_writel(val, g->base + IXP4XX_REG_GPOE);
  131. spin_unlock_irqrestore(&g->gc.bgpio_lock, flags);
  132. /* This parent only accept level high (asserted) */
  133. return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH);
  134. }
  135. static struct irq_chip ixp4xx_gpio_irqchip = {
  136. .name = "IXP4GPIO",
  137. .irq_ack = ixp4xx_gpio_irq_ack,
  138. .irq_mask = irq_chip_mask_parent,
  139. .irq_unmask = ixp4xx_gpio_irq_unmask,
  140. .irq_set_type = ixp4xx_gpio_irq_set_type,
  141. };
  142. static int ixp4xx_gpio_child_to_parent_hwirq(struct gpio_chip *gc,
  143. unsigned int child,
  144. unsigned int child_type,
  145. unsigned int *parent,
  146. unsigned int *parent_type)
  147. {
  148. /* All these interrupts are level high in the CPU */
  149. *parent_type = IRQ_TYPE_LEVEL_HIGH;
  150. /* GPIO lines 0..12 have dedicated IRQs */
  151. if (child == 0) {
  152. *parent = 6;
  153. return 0;
  154. }
  155. if (child == 1) {
  156. *parent = 7;
  157. return 0;
  158. }
  159. if (child >= 2 && child <= 12) {
  160. *parent = child + 17;
  161. return 0;
  162. }
  163. return -EINVAL;
  164. }
  165. static int ixp4xx_gpio_probe(struct platform_device *pdev)
  166. {
  167. unsigned long flags;
  168. struct device *dev = &pdev->dev;
  169. struct device_node *np = dev->of_node;
  170. struct irq_domain *parent;
  171. struct resource *res;
  172. struct ixp4xx_gpio *g;
  173. struct gpio_irq_chip *girq;
  174. int ret;
  175. g = devm_kzalloc(dev, sizeof(*g), GFP_KERNEL);
  176. if (!g)
  177. return -ENOMEM;
  178. g->dev = dev;
  179. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  180. g->base = devm_ioremap_resource(dev, res);
  181. if (IS_ERR(g->base))
  182. return PTR_ERR(g->base);
  183. /*
  184. * When we convert to device tree we will simply look up the
  185. * parent irqdomain using irq_find_host(parent) as parent comes
  186. * from IRQCHIP_DECLARE(), then use of_node_to_fwnode() to get
  187. * the fwnode. For now we need this boardfile style code.
  188. */
  189. if (np) {
  190. struct device_node *irq_parent;
  191. irq_parent = of_irq_find_parent(np);
  192. if (!irq_parent) {
  193. dev_err(dev, "no IRQ parent node\n");
  194. return -ENODEV;
  195. }
  196. parent = irq_find_host(irq_parent);
  197. if (!parent) {
  198. dev_err(dev, "no IRQ parent domain\n");
  199. return -ENODEV;
  200. }
  201. g->fwnode = of_node_to_fwnode(np);
  202. } else {
  203. parent = ixp4xx_get_irq_domain();
  204. g->fwnode = irq_domain_alloc_fwnode(&res->start);
  205. if (!g->fwnode) {
  206. dev_err(dev, "no domain base\n");
  207. return -ENODEV;
  208. }
  209. }
  210. /*
  211. * Make sure GPIO 14 and 15 are NOT used as clocks but GPIO on
  212. * specific machines.
  213. */
  214. if (machine_is_dsmg600() || machine_is_nas100d())
  215. __raw_writel(0x0, g->base + IXP4XX_REG_GPCLK);
  216. /*
  217. * This is a very special big-endian ARM issue: when the IXP4xx is
  218. * run in big endian mode, all registers in the machine are switched
  219. * around to the CPU-native endianness. As you see mostly in the
  220. * driver we use __raw_readl()/__raw_writel() to access the registers
  221. * in the appropriate order. With the GPIO library we need to specify
  222. * byte order explicitly, so this flag needs to be set when compiling
  223. * for big endian.
  224. */
  225. #if defined(CONFIG_CPU_BIG_ENDIAN)
  226. flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER;
  227. #else
  228. flags = 0;
  229. #endif
  230. /* Populate and register gpio chip */
  231. ret = bgpio_init(&g->gc, dev, 4,
  232. g->base + IXP4XX_REG_GPIN,
  233. g->base + IXP4XX_REG_GPOUT,
  234. NULL,
  235. NULL,
  236. g->base + IXP4XX_REG_GPOE,
  237. flags);
  238. if (ret) {
  239. dev_err(dev, "unable to init generic GPIO\n");
  240. return ret;
  241. }
  242. g->gc.ngpio = 16;
  243. g->gc.label = "IXP4XX_GPIO_CHIP";
  244. /*
  245. * TODO: when we have migrated to device tree and all GPIOs
  246. * are fetched using phandles, set this to -1 to get rid of
  247. * the fixed gpiochip base.
  248. */
  249. g->gc.base = 0;
  250. g->gc.parent = &pdev->dev;
  251. g->gc.owner = THIS_MODULE;
  252. girq = &g->gc.irq;
  253. girq->chip = &ixp4xx_gpio_irqchip;
  254. girq->fwnode = g->fwnode;
  255. girq->parent_domain = parent;
  256. girq->child_to_parent_hwirq = ixp4xx_gpio_child_to_parent_hwirq;
  257. girq->handler = handle_bad_irq;
  258. girq->default_type = IRQ_TYPE_NONE;
  259. ret = devm_gpiochip_add_data(dev, &g->gc, g);
  260. if (ret) {
  261. dev_err(dev, "failed to add SoC gpiochip\n");
  262. return ret;
  263. }
  264. platform_set_drvdata(pdev, g);
  265. dev_info(dev, "IXP4 GPIO registered\n");
  266. return 0;
  267. }
  268. static const struct of_device_id ixp4xx_gpio_of_match[] = {
  269. {
  270. .compatible = "intel,ixp4xx-gpio",
  271. },
  272. {},
  273. };
  274. static struct platform_driver ixp4xx_gpio_driver = {
  275. .driver = {
  276. .name = "ixp4xx-gpio",
  277. .of_match_table = of_match_ptr(ixp4xx_gpio_of_match),
  278. },
  279. .probe = ixp4xx_gpio_probe,
  280. };
  281. builtin_platform_driver(ixp4xx_gpio_driver);