gpio-intel-mid.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Intel MID GPIO driver
  4. *
  5. * Copyright (c) 2008-2014,2016 Intel Corporation.
  6. */
  7. /* Supports:
  8. * Moorestown platform Langwell chip.
  9. * Medfield platform Penwell chip.
  10. * Clovertrail platform Cloverview chip.
  11. */
  12. #include <linux/delay.h>
  13. #include <linux/gpio/driver.h>
  14. #include <linux/init.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/io.h>
  17. #include <linux/kernel.h>
  18. #include <linux/pci.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/pm_runtime.h>
  21. #include <linux/slab.h>
  22. #include <linux/stddef.h>
  23. #define INTEL_MID_IRQ_TYPE_EDGE (1 << 0)
  24. #define INTEL_MID_IRQ_TYPE_LEVEL (1 << 1)
  25. /*
  26. * Langwell chip has 64 pins and thus there are 2 32bit registers to control
  27. * each feature, while Penwell chip has 96 pins for each block, and need 3 32bit
  28. * registers to control them, so we only define the order here instead of a
  29. * structure, to get a bit offset for a pin (use GPDR as an example):
  30. *
  31. * nreg = ngpio / 32;
  32. * reg = offset / 32;
  33. * bit = offset % 32;
  34. * reg_addr = reg_base + GPDR * nreg * 4 + reg * 4;
  35. *
  36. * so the bit of reg_addr is to control pin offset's GPDR feature
  37. */
  38. enum GPIO_REG {
  39. GPLR = 0, /* pin level read-only */
  40. GPDR, /* pin direction */
  41. GPSR, /* pin set */
  42. GPCR, /* pin clear */
  43. GRER, /* rising edge detect */
  44. GFER, /* falling edge detect */
  45. GEDR, /* edge detect result */
  46. GAFR, /* alt function */
  47. };
  48. /* intel_mid gpio driver data */
  49. struct intel_mid_gpio_ddata {
  50. u16 ngpio; /* number of gpio pins */
  51. u32 chip_irq_type; /* chip interrupt type */
  52. };
  53. struct intel_mid_gpio {
  54. struct gpio_chip chip;
  55. void __iomem *reg_base;
  56. spinlock_t lock;
  57. struct pci_dev *pdev;
  58. };
  59. static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned offset,
  60. enum GPIO_REG reg_type)
  61. {
  62. struct intel_mid_gpio *priv = gpiochip_get_data(chip);
  63. unsigned nreg = chip->ngpio / 32;
  64. u8 reg = offset / 32;
  65. return priv->reg_base + reg_type * nreg * 4 + reg * 4;
  66. }
  67. static void __iomem *gpio_reg_2bit(struct gpio_chip *chip, unsigned offset,
  68. enum GPIO_REG reg_type)
  69. {
  70. struct intel_mid_gpio *priv = gpiochip_get_data(chip);
  71. unsigned nreg = chip->ngpio / 32;
  72. u8 reg = offset / 16;
  73. return priv->reg_base + reg_type * nreg * 4 + reg * 4;
  74. }
  75. static int intel_gpio_request(struct gpio_chip *chip, unsigned offset)
  76. {
  77. void __iomem *gafr = gpio_reg_2bit(chip, offset, GAFR);
  78. u32 value = readl(gafr);
  79. int shift = (offset % 16) << 1, af = (value >> shift) & 3;
  80. if (af) {
  81. value &= ~(3 << shift);
  82. writel(value, gafr);
  83. }
  84. return 0;
  85. }
  86. static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
  87. {
  88. void __iomem *gplr = gpio_reg(chip, offset, GPLR);
  89. return !!(readl(gplr) & BIT(offset % 32));
  90. }
  91. static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
  92. {
  93. void __iomem *gpsr, *gpcr;
  94. if (value) {
  95. gpsr = gpio_reg(chip, offset, GPSR);
  96. writel(BIT(offset % 32), gpsr);
  97. } else {
  98. gpcr = gpio_reg(chip, offset, GPCR);
  99. writel(BIT(offset % 32), gpcr);
  100. }
  101. }
  102. static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
  103. {
  104. struct intel_mid_gpio *priv = gpiochip_get_data(chip);
  105. void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
  106. u32 value;
  107. unsigned long flags;
  108. if (priv->pdev)
  109. pm_runtime_get(&priv->pdev->dev);
  110. spin_lock_irqsave(&priv->lock, flags);
  111. value = readl(gpdr);
  112. value &= ~BIT(offset % 32);
  113. writel(value, gpdr);
  114. spin_unlock_irqrestore(&priv->lock, flags);
  115. if (priv->pdev)
  116. pm_runtime_put(&priv->pdev->dev);
  117. return 0;
  118. }
  119. static int intel_gpio_direction_output(struct gpio_chip *chip,
  120. unsigned offset, int value)
  121. {
  122. struct intel_mid_gpio *priv = gpiochip_get_data(chip);
  123. void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
  124. unsigned long flags;
  125. intel_gpio_set(chip, offset, value);
  126. if (priv->pdev)
  127. pm_runtime_get(&priv->pdev->dev);
  128. spin_lock_irqsave(&priv->lock, flags);
  129. value = readl(gpdr);
  130. value |= BIT(offset % 32);
  131. writel(value, gpdr);
  132. spin_unlock_irqrestore(&priv->lock, flags);
  133. if (priv->pdev)
  134. pm_runtime_put(&priv->pdev->dev);
  135. return 0;
  136. }
  137. static int intel_mid_irq_type(struct irq_data *d, unsigned type)
  138. {
  139. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  140. struct intel_mid_gpio *priv = gpiochip_get_data(gc);
  141. u32 gpio = irqd_to_hwirq(d);
  142. unsigned long flags;
  143. u32 value;
  144. void __iomem *grer = gpio_reg(&priv->chip, gpio, GRER);
  145. void __iomem *gfer = gpio_reg(&priv->chip, gpio, GFER);
  146. if (gpio >= priv->chip.ngpio)
  147. return -EINVAL;
  148. if (priv->pdev)
  149. pm_runtime_get(&priv->pdev->dev);
  150. spin_lock_irqsave(&priv->lock, flags);
  151. if (type & IRQ_TYPE_EDGE_RISING)
  152. value = readl(grer) | BIT(gpio % 32);
  153. else
  154. value = readl(grer) & (~BIT(gpio % 32));
  155. writel(value, grer);
  156. if (type & IRQ_TYPE_EDGE_FALLING)
  157. value = readl(gfer) | BIT(gpio % 32);
  158. else
  159. value = readl(gfer) & (~BIT(gpio % 32));
  160. writel(value, gfer);
  161. spin_unlock_irqrestore(&priv->lock, flags);
  162. if (priv->pdev)
  163. pm_runtime_put(&priv->pdev->dev);
  164. return 0;
  165. }
  166. static void intel_mid_irq_unmask(struct irq_data *d)
  167. {
  168. }
  169. static void intel_mid_irq_mask(struct irq_data *d)
  170. {
  171. }
  172. static struct irq_chip intel_mid_irqchip = {
  173. .name = "INTEL_MID-GPIO",
  174. .irq_mask = intel_mid_irq_mask,
  175. .irq_unmask = intel_mid_irq_unmask,
  176. .irq_set_type = intel_mid_irq_type,
  177. };
  178. static const struct intel_mid_gpio_ddata gpio_lincroft = {
  179. .ngpio = 64,
  180. };
  181. static const struct intel_mid_gpio_ddata gpio_penwell_aon = {
  182. .ngpio = 96,
  183. .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
  184. };
  185. static const struct intel_mid_gpio_ddata gpio_penwell_core = {
  186. .ngpio = 96,
  187. .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
  188. };
  189. static const struct intel_mid_gpio_ddata gpio_cloverview_aon = {
  190. .ngpio = 96,
  191. .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE | INTEL_MID_IRQ_TYPE_LEVEL,
  192. };
  193. static const struct intel_mid_gpio_ddata gpio_cloverview_core = {
  194. .ngpio = 96,
  195. .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
  196. };
  197. static const struct pci_device_id intel_gpio_ids[] = {
  198. {
  199. /* Lincroft */
  200. PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080f),
  201. .driver_data = (kernel_ulong_t)&gpio_lincroft,
  202. },
  203. {
  204. /* Penwell AON */
  205. PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081f),
  206. .driver_data = (kernel_ulong_t)&gpio_penwell_aon,
  207. },
  208. {
  209. /* Penwell Core */
  210. PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081a),
  211. .driver_data = (kernel_ulong_t)&gpio_penwell_core,
  212. },
  213. {
  214. /* Cloverview Aon */
  215. PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08eb),
  216. .driver_data = (kernel_ulong_t)&gpio_cloverview_aon,
  217. },
  218. {
  219. /* Cloverview Core */
  220. PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08f7),
  221. .driver_data = (kernel_ulong_t)&gpio_cloverview_core,
  222. },
  223. { }
  224. };
  225. static void intel_mid_irq_handler(struct irq_desc *desc)
  226. {
  227. struct gpio_chip *gc = irq_desc_get_handler_data(desc);
  228. struct intel_mid_gpio *priv = gpiochip_get_data(gc);
  229. struct irq_data *data = irq_desc_get_irq_data(desc);
  230. struct irq_chip *chip = irq_data_get_irq_chip(data);
  231. u32 base, gpio, mask;
  232. unsigned long pending;
  233. void __iomem *gedr;
  234. /* check GPIO controller to check which pin triggered the interrupt */
  235. for (base = 0; base < priv->chip.ngpio; base += 32) {
  236. gedr = gpio_reg(&priv->chip, base, GEDR);
  237. while ((pending = readl(gedr))) {
  238. gpio = __ffs(pending);
  239. mask = BIT(gpio);
  240. /* Clear before handling so we can't lose an edge */
  241. writel(mask, gedr);
  242. generic_handle_irq(irq_find_mapping(gc->irq.domain,
  243. base + gpio));
  244. }
  245. }
  246. chip->irq_eoi(data);
  247. }
  248. static int intel_mid_irq_init_hw(struct gpio_chip *chip)
  249. {
  250. struct intel_mid_gpio *priv = gpiochip_get_data(chip);
  251. void __iomem *reg;
  252. unsigned base;
  253. for (base = 0; base < priv->chip.ngpio; base += 32) {
  254. /* Clear the rising-edge detect register */
  255. reg = gpio_reg(&priv->chip, base, GRER);
  256. writel(0, reg);
  257. /* Clear the falling-edge detect register */
  258. reg = gpio_reg(&priv->chip, base, GFER);
  259. writel(0, reg);
  260. /* Clear the edge detect status register */
  261. reg = gpio_reg(&priv->chip, base, GEDR);
  262. writel(~0, reg);
  263. }
  264. return 0;
  265. }
  266. static int __maybe_unused intel_gpio_runtime_idle(struct device *dev)
  267. {
  268. int err = pm_schedule_suspend(dev, 500);
  269. return err ?: -EBUSY;
  270. }
  271. static const struct dev_pm_ops intel_gpio_pm_ops = {
  272. SET_RUNTIME_PM_OPS(NULL, NULL, intel_gpio_runtime_idle)
  273. };
  274. static int intel_gpio_probe(struct pci_dev *pdev,
  275. const struct pci_device_id *id)
  276. {
  277. void __iomem *base;
  278. struct intel_mid_gpio *priv;
  279. u32 gpio_base;
  280. u32 irq_base;
  281. int retval;
  282. struct gpio_irq_chip *girq;
  283. struct intel_mid_gpio_ddata *ddata =
  284. (struct intel_mid_gpio_ddata *)id->driver_data;
  285. retval = pcim_enable_device(pdev);
  286. if (retval)
  287. return retval;
  288. retval = pcim_iomap_regions(pdev, 1 << 0 | 1 << 1, pci_name(pdev));
  289. if (retval) {
  290. dev_err(&pdev->dev, "I/O memory mapping error\n");
  291. return retval;
  292. }
  293. base = pcim_iomap_table(pdev)[1];
  294. irq_base = readl(base);
  295. gpio_base = readl(sizeof(u32) + base);
  296. /* release the IO mapping, since we already get the info from bar1 */
  297. pcim_iounmap_regions(pdev, 1 << 1);
  298. priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
  299. if (!priv)
  300. return -ENOMEM;
  301. priv->reg_base = pcim_iomap_table(pdev)[0];
  302. priv->chip.label = dev_name(&pdev->dev);
  303. priv->chip.parent = &pdev->dev;
  304. priv->chip.request = intel_gpio_request;
  305. priv->chip.direction_input = intel_gpio_direction_input;
  306. priv->chip.direction_output = intel_gpio_direction_output;
  307. priv->chip.get = intel_gpio_get;
  308. priv->chip.set = intel_gpio_set;
  309. priv->chip.base = gpio_base;
  310. priv->chip.ngpio = ddata->ngpio;
  311. priv->chip.can_sleep = false;
  312. priv->pdev = pdev;
  313. spin_lock_init(&priv->lock);
  314. girq = &priv->chip.irq;
  315. girq->chip = &intel_mid_irqchip;
  316. girq->init_hw = intel_mid_irq_init_hw;
  317. girq->parent_handler = intel_mid_irq_handler;
  318. girq->num_parents = 1;
  319. girq->parents = devm_kcalloc(&pdev->dev, girq->num_parents,
  320. sizeof(*girq->parents),
  321. GFP_KERNEL);
  322. if (!girq->parents)
  323. return -ENOMEM;
  324. girq->parents[0] = pdev->irq;
  325. girq->first = irq_base;
  326. girq->default_type = IRQ_TYPE_NONE;
  327. girq->handler = handle_simple_irq;
  328. pci_set_drvdata(pdev, priv);
  329. retval = devm_gpiochip_add_data(&pdev->dev, &priv->chip, priv);
  330. if (retval) {
  331. dev_err(&pdev->dev, "gpiochip_add error %d\n", retval);
  332. return retval;
  333. }
  334. pm_runtime_put_noidle(&pdev->dev);
  335. pm_runtime_allow(&pdev->dev);
  336. return 0;
  337. }
  338. static struct pci_driver intel_gpio_driver = {
  339. .name = "intel_mid_gpio",
  340. .id_table = intel_gpio_ids,
  341. .probe = intel_gpio_probe,
  342. .driver = {
  343. .pm = &intel_gpio_pm_ops,
  344. },
  345. };
  346. builtin_pci_driver(intel_gpio_driver);