gpio-ich.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Intel ICH6-10, Series 5 and 6, Atom C2000 (Avoton/Rangeley) GPIO driver
  4. *
  5. * Copyright (C) 2010 Extreme Engineering Solutions.
  6. */
  7. #include <linux/bitops.h>
  8. #include <linux/gpio/driver.h>
  9. #include <linux/ioport.h>
  10. #include <linux/mfd/lpc_ich.h>
  11. #include <linux/module.h>
  12. #include <linux/pci.h>
  13. #include <linux/platform_device.h>
  14. #define DRV_NAME "gpio_ich"
  15. /*
  16. * GPIO register offsets in GPIO I/O space.
  17. * Each chunk of 32 GPIOs is manipulated via its own USE_SELx, IO_SELx, and
  18. * LVLx registers. Logic in the read/write functions takes a register and
  19. * an absolute bit number and determines the proper register offset and bit
  20. * number in that register. For example, to read the value of GPIO bit 50
  21. * the code would access offset ichx_regs[2(=GPIO_LVL)][1(=50/32)],
  22. * bit 18 (50%32).
  23. */
  24. enum GPIO_REG {
  25. GPIO_USE_SEL = 0,
  26. GPIO_IO_SEL,
  27. GPIO_LVL,
  28. GPO_BLINK
  29. };
  30. static const u8 ichx_regs[4][3] = {
  31. {0x00, 0x30, 0x40}, /* USE_SEL[1-3] offsets */
  32. {0x04, 0x34, 0x44}, /* IO_SEL[1-3] offsets */
  33. {0x0c, 0x38, 0x48}, /* LVL[1-3] offsets */
  34. {0x18, 0x18, 0x18}, /* BLINK offset */
  35. };
  36. static const u8 ichx_reglen[3] = {
  37. 0x30, 0x10, 0x10,
  38. };
  39. static const u8 avoton_regs[4][3] = {
  40. {0x00, 0x80, 0x00},
  41. {0x04, 0x84, 0x00},
  42. {0x08, 0x88, 0x00},
  43. };
  44. static const u8 avoton_reglen[3] = {
  45. 0x10, 0x10, 0x00,
  46. };
  47. #define ICHX_WRITE(val, reg, base_res) outl(val, (reg) + (base_res)->start)
  48. #define ICHX_READ(reg, base_res) inl((reg) + (base_res)->start)
  49. struct ichx_desc {
  50. /* Max GPIO pins the chipset can have */
  51. uint ngpio;
  52. /* chipset registers */
  53. const u8 (*regs)[3];
  54. const u8 *reglen;
  55. /* GPO_BLINK is available on this chipset */
  56. bool have_blink;
  57. /* Whether the chipset has GPIO in GPE0_STS in the PM IO region */
  58. bool uses_gpe0;
  59. /* USE_SEL is bogus on some chipsets, eg 3100 */
  60. u32 use_sel_ignore[3];
  61. /* Some chipsets have quirks, let these use their own request/get */
  62. int (*request)(struct gpio_chip *chip, unsigned int offset);
  63. int (*get)(struct gpio_chip *chip, unsigned int offset);
  64. /*
  65. * Some chipsets don't let reading output values on GPIO_LVL register
  66. * this option allows driver caching written output values
  67. */
  68. bool use_outlvl_cache;
  69. };
  70. static struct {
  71. spinlock_t lock;
  72. struct device *dev;
  73. struct gpio_chip chip;
  74. struct resource *gpio_base; /* GPIO IO base */
  75. struct resource *pm_base; /* Power Management IO base */
  76. struct ichx_desc *desc; /* Pointer to chipset-specific description */
  77. u32 orig_gpio_ctrl; /* Orig CTRL value, used to restore on exit */
  78. u8 use_gpio; /* Which GPIO groups are usable */
  79. int outlvl_cache[3]; /* cached output values */
  80. } ichx_priv;
  81. static int modparam_gpiobase = -1; /* dynamic */
  82. module_param_named(gpiobase, modparam_gpiobase, int, 0444);
  83. MODULE_PARM_DESC(gpiobase, "The GPIO number base. -1 means dynamic, which is the default.");
  84. static int ichx_write_bit(int reg, unsigned int nr, int val, int verify)
  85. {
  86. unsigned long flags;
  87. u32 data, tmp;
  88. int reg_nr = nr / 32;
  89. int bit = nr & 0x1f;
  90. spin_lock_irqsave(&ichx_priv.lock, flags);
  91. if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
  92. data = ichx_priv.outlvl_cache[reg_nr];
  93. else
  94. data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
  95. ichx_priv.gpio_base);
  96. if (val)
  97. data |= BIT(bit);
  98. else
  99. data &= ~BIT(bit);
  100. ICHX_WRITE(data, ichx_priv.desc->regs[reg][reg_nr],
  101. ichx_priv.gpio_base);
  102. if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
  103. ichx_priv.outlvl_cache[reg_nr] = data;
  104. tmp = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
  105. ichx_priv.gpio_base);
  106. spin_unlock_irqrestore(&ichx_priv.lock, flags);
  107. return (verify && data != tmp) ? -EPERM : 0;
  108. }
  109. static int ichx_read_bit(int reg, unsigned int nr)
  110. {
  111. unsigned long flags;
  112. u32 data;
  113. int reg_nr = nr / 32;
  114. int bit = nr & 0x1f;
  115. spin_lock_irqsave(&ichx_priv.lock, flags);
  116. data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
  117. ichx_priv.gpio_base);
  118. if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
  119. data = ichx_priv.outlvl_cache[reg_nr] | data;
  120. spin_unlock_irqrestore(&ichx_priv.lock, flags);
  121. return !!(data & BIT(bit));
  122. }
  123. static bool ichx_gpio_check_available(struct gpio_chip *gpio, unsigned int nr)
  124. {
  125. return !!(ichx_priv.use_gpio & BIT(nr / 32));
  126. }
  127. static int ichx_gpio_get_direction(struct gpio_chip *gpio, unsigned int nr)
  128. {
  129. if (ichx_read_bit(GPIO_IO_SEL, nr))
  130. return GPIO_LINE_DIRECTION_IN;
  131. return GPIO_LINE_DIRECTION_OUT;
  132. }
  133. static int ichx_gpio_direction_input(struct gpio_chip *gpio, unsigned int nr)
  134. {
  135. /*
  136. * Try setting pin as an input and verify it worked since many pins
  137. * are output-only.
  138. */
  139. return ichx_write_bit(GPIO_IO_SEL, nr, 1, 1);
  140. }
  141. static int ichx_gpio_direction_output(struct gpio_chip *gpio, unsigned int nr,
  142. int val)
  143. {
  144. /* Disable blink hardware which is available for GPIOs from 0 to 31. */
  145. if (nr < 32 && ichx_priv.desc->have_blink)
  146. ichx_write_bit(GPO_BLINK, nr, 0, 0);
  147. /* Set GPIO output value. */
  148. ichx_write_bit(GPIO_LVL, nr, val, 0);
  149. /*
  150. * Try setting pin as an output and verify it worked since many pins
  151. * are input-only.
  152. */
  153. return ichx_write_bit(GPIO_IO_SEL, nr, 0, 1);
  154. }
  155. static int ichx_gpio_get(struct gpio_chip *chip, unsigned int nr)
  156. {
  157. return ichx_read_bit(GPIO_LVL, nr);
  158. }
  159. static int ich6_gpio_get(struct gpio_chip *chip, unsigned int nr)
  160. {
  161. unsigned long flags;
  162. u32 data;
  163. /*
  164. * GPI 0 - 15 need to be read from the power management registers on
  165. * a ICH6/3100 bridge.
  166. */
  167. if (nr < 16) {
  168. if (!ichx_priv.pm_base)
  169. return -ENXIO;
  170. spin_lock_irqsave(&ichx_priv.lock, flags);
  171. /* GPI 0 - 15 are latched, write 1 to clear*/
  172. ICHX_WRITE(BIT(16 + nr), 0, ichx_priv.pm_base);
  173. data = ICHX_READ(0, ichx_priv.pm_base);
  174. spin_unlock_irqrestore(&ichx_priv.lock, flags);
  175. return !!((data >> 16) & BIT(nr));
  176. } else {
  177. return ichx_gpio_get(chip, nr);
  178. }
  179. }
  180. static int ichx_gpio_request(struct gpio_chip *chip, unsigned int nr)
  181. {
  182. if (!ichx_gpio_check_available(chip, nr))
  183. return -ENXIO;
  184. /*
  185. * Note we assume the BIOS properly set a bridge's USE value. Some
  186. * chips (eg Intel 3100) have bogus USE values though, so first see if
  187. * the chipset's USE value can be trusted for this specific bit.
  188. * If it can't be trusted, assume that the pin can be used as a GPIO.
  189. */
  190. if (ichx_priv.desc->use_sel_ignore[nr / 32] & BIT(nr & 0x1f))
  191. return 0;
  192. return ichx_read_bit(GPIO_USE_SEL, nr) ? 0 : -ENODEV;
  193. }
  194. static int ich6_gpio_request(struct gpio_chip *chip, unsigned int nr)
  195. {
  196. /*
  197. * Fixups for bits 16 and 17 are necessary on the Intel ICH6/3100
  198. * bridge as they are controlled by USE register bits 0 and 1. See
  199. * "Table 704 GPIO_USE_SEL1 register" in the i3100 datasheet for
  200. * additional info.
  201. */
  202. if (nr == 16 || nr == 17)
  203. nr -= 16;
  204. return ichx_gpio_request(chip, nr);
  205. }
  206. static void ichx_gpio_set(struct gpio_chip *chip, unsigned int nr, int val)
  207. {
  208. ichx_write_bit(GPIO_LVL, nr, val, 0);
  209. }
  210. static void ichx_gpiolib_setup(struct gpio_chip *chip)
  211. {
  212. chip->owner = THIS_MODULE;
  213. chip->label = DRV_NAME;
  214. chip->parent = ichx_priv.dev;
  215. /* Allow chip-specific overrides of request()/get() */
  216. chip->request = ichx_priv.desc->request ?
  217. ichx_priv.desc->request : ichx_gpio_request;
  218. chip->get = ichx_priv.desc->get ?
  219. ichx_priv.desc->get : ichx_gpio_get;
  220. chip->set = ichx_gpio_set;
  221. chip->get_direction = ichx_gpio_get_direction;
  222. chip->direction_input = ichx_gpio_direction_input;
  223. chip->direction_output = ichx_gpio_direction_output;
  224. chip->base = modparam_gpiobase;
  225. chip->ngpio = ichx_priv.desc->ngpio;
  226. chip->can_sleep = false;
  227. chip->dbg_show = NULL;
  228. }
  229. /* ICH6-based, 631xesb-based */
  230. static struct ichx_desc ich6_desc = {
  231. /* Bridges using the ICH6 controller need fixups for GPIO 0 - 17 */
  232. .request = ich6_gpio_request,
  233. .get = ich6_gpio_get,
  234. /* GPIO 0-15 are read in the GPE0_STS PM register */
  235. .uses_gpe0 = true,
  236. .ngpio = 50,
  237. .have_blink = true,
  238. .regs = ichx_regs,
  239. .reglen = ichx_reglen,
  240. };
  241. /* Intel 3100 */
  242. static struct ichx_desc i3100_desc = {
  243. /*
  244. * Bits 16,17, 20 of USE_SEL and bit 16 of USE_SEL2 always read 0 on
  245. * the Intel 3100. See "Table 712. GPIO Summary Table" of 3100
  246. * Datasheet for more info.
  247. */
  248. .use_sel_ignore = {0x00130000, 0x00010000, 0x0},
  249. /* The 3100 needs fixups for GPIO 0 - 17 */
  250. .request = ich6_gpio_request,
  251. .get = ich6_gpio_get,
  252. /* GPIO 0-15 are read in the GPE0_STS PM register */
  253. .uses_gpe0 = true,
  254. .ngpio = 50,
  255. .regs = ichx_regs,
  256. .reglen = ichx_reglen,
  257. };
  258. /* ICH7 and ICH8-based */
  259. static struct ichx_desc ich7_desc = {
  260. .ngpio = 50,
  261. .have_blink = true,
  262. .regs = ichx_regs,
  263. .reglen = ichx_reglen,
  264. };
  265. /* ICH9-based */
  266. static struct ichx_desc ich9_desc = {
  267. .ngpio = 61,
  268. .have_blink = true,
  269. .regs = ichx_regs,
  270. .reglen = ichx_reglen,
  271. };
  272. /* ICH10-based - Consumer/corporate versions have different amount of GPIO */
  273. static struct ichx_desc ich10_cons_desc = {
  274. .ngpio = 61,
  275. .have_blink = true,
  276. .regs = ichx_regs,
  277. .reglen = ichx_reglen,
  278. };
  279. static struct ichx_desc ich10_corp_desc = {
  280. .ngpio = 72,
  281. .have_blink = true,
  282. .regs = ichx_regs,
  283. .reglen = ichx_reglen,
  284. };
  285. /* Intel 5 series, 6 series, 3400 series, and C200 series */
  286. static struct ichx_desc intel5_desc = {
  287. .ngpio = 76,
  288. .regs = ichx_regs,
  289. .reglen = ichx_reglen,
  290. };
  291. /* Avoton */
  292. static struct ichx_desc avoton_desc = {
  293. /* Avoton has only 59 GPIOs, but we assume the first set of register
  294. * (Core) has 32 instead of 31 to keep gpio-ich compliance
  295. */
  296. .ngpio = 60,
  297. .regs = avoton_regs,
  298. .reglen = avoton_reglen,
  299. .use_outlvl_cache = true,
  300. };
  301. static int ichx_gpio_request_regions(struct device *dev,
  302. struct resource *res_base, const char *name, u8 use_gpio)
  303. {
  304. int i;
  305. if (!res_base || !res_base->start || !res_base->end)
  306. return -ENODEV;
  307. for (i = 0; i < ARRAY_SIZE(ichx_priv.desc->regs[0]); i++) {
  308. if (!(use_gpio & BIT(i)))
  309. continue;
  310. if (!devm_request_region(dev,
  311. res_base->start + ichx_priv.desc->regs[0][i],
  312. ichx_priv.desc->reglen[i], name))
  313. return -EBUSY;
  314. }
  315. return 0;
  316. }
  317. static int ichx_gpio_probe(struct platform_device *pdev)
  318. {
  319. struct device *dev = &pdev->dev;
  320. struct lpc_ich_info *ich_info = dev_get_platdata(dev);
  321. struct resource *res_base, *res_pm;
  322. int err;
  323. if (!ich_info)
  324. return -ENODEV;
  325. switch (ich_info->gpio_version) {
  326. case ICH_I3100_GPIO:
  327. ichx_priv.desc = &i3100_desc;
  328. break;
  329. case ICH_V5_GPIO:
  330. ichx_priv.desc = &intel5_desc;
  331. break;
  332. case ICH_V6_GPIO:
  333. ichx_priv.desc = &ich6_desc;
  334. break;
  335. case ICH_V7_GPIO:
  336. ichx_priv.desc = &ich7_desc;
  337. break;
  338. case ICH_V9_GPIO:
  339. ichx_priv.desc = &ich9_desc;
  340. break;
  341. case ICH_V10CORP_GPIO:
  342. ichx_priv.desc = &ich10_corp_desc;
  343. break;
  344. case ICH_V10CONS_GPIO:
  345. ichx_priv.desc = &ich10_cons_desc;
  346. break;
  347. case AVOTON_GPIO:
  348. ichx_priv.desc = &avoton_desc;
  349. break;
  350. default:
  351. return -ENODEV;
  352. }
  353. ichx_priv.dev = dev;
  354. spin_lock_init(&ichx_priv.lock);
  355. res_base = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPIO);
  356. err = ichx_gpio_request_regions(dev, res_base, pdev->name,
  357. ich_info->use_gpio);
  358. if (err)
  359. return err;
  360. ichx_priv.gpio_base = res_base;
  361. ichx_priv.use_gpio = ich_info->use_gpio;
  362. /*
  363. * If necessary, determine the I/O address of ACPI/power management
  364. * registers which are needed to read the GPE0 register for GPI pins
  365. * 0 - 15 on some chipsets.
  366. */
  367. if (!ichx_priv.desc->uses_gpe0)
  368. goto init;
  369. res_pm = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPE0);
  370. if (!res_pm) {
  371. dev_warn(dev, "ACPI BAR is unavailable, GPI 0 - 15 unavailable\n");
  372. goto init;
  373. }
  374. if (!devm_request_region(dev, res_pm->start, resource_size(res_pm),
  375. pdev->name)) {
  376. dev_warn(dev, "ACPI BAR is busy, GPI 0 - 15 unavailable\n");
  377. goto init;
  378. }
  379. ichx_priv.pm_base = res_pm;
  380. init:
  381. ichx_gpiolib_setup(&ichx_priv.chip);
  382. err = gpiochip_add_data(&ichx_priv.chip, NULL);
  383. if (err) {
  384. dev_err(dev, "Failed to register GPIOs\n");
  385. return err;
  386. }
  387. dev_info(dev, "GPIO from %d to %d\n", ichx_priv.chip.base,
  388. ichx_priv.chip.base + ichx_priv.chip.ngpio - 1);
  389. return 0;
  390. }
  391. static int ichx_gpio_remove(struct platform_device *pdev)
  392. {
  393. gpiochip_remove(&ichx_priv.chip);
  394. return 0;
  395. }
  396. static struct platform_driver ichx_gpio_driver = {
  397. .driver = {
  398. .name = DRV_NAME,
  399. },
  400. .probe = ichx_gpio_probe,
  401. .remove = ichx_gpio_remove,
  402. };
  403. module_platform_driver(ichx_gpio_driver);
  404. MODULE_AUTHOR("Peter Tyser <ptyser@xes-inc.com>");
  405. MODULE_DESCRIPTION("GPIO interface for Intel ICH series");
  406. MODULE_LICENSE("GPL");
  407. MODULE_ALIAS("platform:"DRV_NAME);