gpio-grgpio.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Driver for Aeroflex Gaisler GRGPIO General Purpose I/O cores.
  4. *
  5. * 2013 (c) Aeroflex Gaisler AB
  6. *
  7. * This driver supports the GRGPIO GPIO core available in the GRLIB VHDL
  8. * IP core library.
  9. *
  10. * Full documentation of the GRGPIO core can be found here:
  11. * http://www.gaisler.com/products/grlib/grip.pdf
  12. *
  13. * See "Documentation/devicetree/bindings/gpio/gpio-grgpio.txt" for
  14. * information on open firmware properties.
  15. *
  16. * Contributors: Andreas Larsson <andreas@gaisler.com>
  17. */
  18. #include <linux/kernel.h>
  19. #include <linux/module.h>
  20. #include <linux/init.h>
  21. #include <linux/spinlock.h>
  22. #include <linux/io.h>
  23. #include <linux/of.h>
  24. #include <linux/of_platform.h>
  25. #include <linux/gpio/driver.h>
  26. #include <linux/slab.h>
  27. #include <linux/err.h>
  28. #include <linux/interrupt.h>
  29. #include <linux/irq.h>
  30. #include <linux/irqdomain.h>
  31. #include <linux/bitops.h>
  32. #define GRGPIO_MAX_NGPIO 32
  33. #define GRGPIO_DATA 0x00
  34. #define GRGPIO_OUTPUT 0x04
  35. #define GRGPIO_DIR 0x08
  36. #define GRGPIO_IMASK 0x0c
  37. #define GRGPIO_IPOL 0x10
  38. #define GRGPIO_IEDGE 0x14
  39. #define GRGPIO_BYPASS 0x18
  40. #define GRGPIO_IMAP_BASE 0x20
  41. /* Structure for an irq of the core - called an underlying irq */
  42. struct grgpio_uirq {
  43. u8 refcnt; /* Reference counter to manage requesting/freeing of uirq */
  44. u8 uirq; /* Underlying irq of the gpio driver */
  45. };
  46. /*
  47. * Structure for an irq of a gpio line handed out by this driver. The index is
  48. * used to map to the corresponding underlying irq.
  49. */
  50. struct grgpio_lirq {
  51. s8 index; /* Index into struct grgpio_priv's uirqs, or -1 */
  52. u8 irq; /* irq for the gpio line */
  53. };
  54. struct grgpio_priv {
  55. struct gpio_chip gc;
  56. void __iomem *regs;
  57. struct device *dev;
  58. u32 imask; /* irq mask shadow register */
  59. /*
  60. * The grgpio core can have multiple "underlying" irqs. The gpio lines
  61. * can be mapped to any one or none of these underlying irqs
  62. * independently of each other. This driver sets up an irq domain and
  63. * hands out separate irqs to each gpio line
  64. */
  65. struct irq_domain *domain;
  66. /*
  67. * This array contains information on each underlying irq, each
  68. * irq of the grgpio core itself.
  69. */
  70. struct grgpio_uirq uirqs[GRGPIO_MAX_NGPIO];
  71. /*
  72. * This array contains information for each gpio line on the irqs
  73. * obtains from this driver. An index value of -1 for a certain gpio
  74. * line indicates that the line has no irq. Otherwise the index connects
  75. * the irq to the underlying irq by pointing into the uirqs array.
  76. */
  77. struct grgpio_lirq lirqs[GRGPIO_MAX_NGPIO];
  78. };
  79. static void grgpio_set_imask(struct grgpio_priv *priv, unsigned int offset,
  80. int val)
  81. {
  82. struct gpio_chip *gc = &priv->gc;
  83. if (val)
  84. priv->imask |= BIT(offset);
  85. else
  86. priv->imask &= ~BIT(offset);
  87. gc->write_reg(priv->regs + GRGPIO_IMASK, priv->imask);
  88. }
  89. static int grgpio_to_irq(struct gpio_chip *gc, unsigned offset)
  90. {
  91. struct grgpio_priv *priv = gpiochip_get_data(gc);
  92. if (offset >= gc->ngpio)
  93. return -ENXIO;
  94. if (priv->lirqs[offset].index < 0)
  95. return -ENXIO;
  96. return irq_create_mapping(priv->domain, offset);
  97. }
  98. /* -------------------- IRQ chip functions -------------------- */
  99. static int grgpio_irq_set_type(struct irq_data *d, unsigned int type)
  100. {
  101. struct grgpio_priv *priv = irq_data_get_irq_chip_data(d);
  102. unsigned long flags;
  103. u32 mask = BIT(d->hwirq);
  104. u32 ipol;
  105. u32 iedge;
  106. u32 pol;
  107. u32 edge;
  108. switch (type) {
  109. case IRQ_TYPE_LEVEL_LOW:
  110. pol = 0;
  111. edge = 0;
  112. break;
  113. case IRQ_TYPE_LEVEL_HIGH:
  114. pol = mask;
  115. edge = 0;
  116. break;
  117. case IRQ_TYPE_EDGE_FALLING:
  118. pol = 0;
  119. edge = mask;
  120. break;
  121. case IRQ_TYPE_EDGE_RISING:
  122. pol = mask;
  123. edge = mask;
  124. break;
  125. default:
  126. return -EINVAL;
  127. }
  128. spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
  129. ipol = priv->gc.read_reg(priv->regs + GRGPIO_IPOL) & ~mask;
  130. iedge = priv->gc.read_reg(priv->regs + GRGPIO_IEDGE) & ~mask;
  131. priv->gc.write_reg(priv->regs + GRGPIO_IPOL, ipol | pol);
  132. priv->gc.write_reg(priv->regs + GRGPIO_IEDGE, iedge | edge);
  133. spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
  134. return 0;
  135. }
  136. static void grgpio_irq_mask(struct irq_data *d)
  137. {
  138. struct grgpio_priv *priv = irq_data_get_irq_chip_data(d);
  139. int offset = d->hwirq;
  140. unsigned long flags;
  141. spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
  142. grgpio_set_imask(priv, offset, 0);
  143. spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
  144. }
  145. static void grgpio_irq_unmask(struct irq_data *d)
  146. {
  147. struct grgpio_priv *priv = irq_data_get_irq_chip_data(d);
  148. int offset = d->hwirq;
  149. unsigned long flags;
  150. spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
  151. grgpio_set_imask(priv, offset, 1);
  152. spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
  153. }
  154. static struct irq_chip grgpio_irq_chip = {
  155. .name = "grgpio",
  156. .irq_mask = grgpio_irq_mask,
  157. .irq_unmask = grgpio_irq_unmask,
  158. .irq_set_type = grgpio_irq_set_type,
  159. };
  160. static irqreturn_t grgpio_irq_handler(int irq, void *dev)
  161. {
  162. struct grgpio_priv *priv = dev;
  163. int ngpio = priv->gc.ngpio;
  164. unsigned long flags;
  165. int i;
  166. int match = 0;
  167. spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
  168. /*
  169. * For each gpio line, call its interrupt handler if it its underlying
  170. * irq matches the current irq that is handled.
  171. */
  172. for (i = 0; i < ngpio; i++) {
  173. struct grgpio_lirq *lirq = &priv->lirqs[i];
  174. if (priv->imask & BIT(i) && lirq->index >= 0 &&
  175. priv->uirqs[lirq->index].uirq == irq) {
  176. generic_handle_irq(lirq->irq);
  177. match = 1;
  178. }
  179. }
  180. spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
  181. if (!match)
  182. dev_warn(priv->dev, "No gpio line matched irq %d\n", irq);
  183. return IRQ_HANDLED;
  184. }
  185. /*
  186. * This function will be called as a consequence of the call to
  187. * irq_create_mapping in grgpio_to_irq
  188. */
  189. static int grgpio_irq_map(struct irq_domain *d, unsigned int irq,
  190. irq_hw_number_t hwirq)
  191. {
  192. struct grgpio_priv *priv = d->host_data;
  193. struct grgpio_lirq *lirq;
  194. struct grgpio_uirq *uirq;
  195. unsigned long flags;
  196. int offset = hwirq;
  197. int ret = 0;
  198. if (!priv)
  199. return -EINVAL;
  200. lirq = &priv->lirqs[offset];
  201. if (lirq->index < 0)
  202. return -EINVAL;
  203. dev_dbg(priv->dev, "Mapping irq %d for gpio line %d\n",
  204. irq, offset);
  205. spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
  206. /* Request underlying irq if not already requested */
  207. lirq->irq = irq;
  208. uirq = &priv->uirqs[lirq->index];
  209. if (uirq->refcnt == 0) {
  210. spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
  211. ret = request_irq(uirq->uirq, grgpio_irq_handler, 0,
  212. dev_name(priv->dev), priv);
  213. if (ret) {
  214. dev_err(priv->dev,
  215. "Could not request underlying irq %d\n",
  216. uirq->uirq);
  217. return ret;
  218. }
  219. spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
  220. }
  221. uirq->refcnt++;
  222. spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
  223. /* Setup irq */
  224. irq_set_chip_data(irq, priv);
  225. irq_set_chip_and_handler(irq, &grgpio_irq_chip,
  226. handle_simple_irq);
  227. irq_set_noprobe(irq);
  228. return ret;
  229. }
  230. static void grgpio_irq_unmap(struct irq_domain *d, unsigned int irq)
  231. {
  232. struct grgpio_priv *priv = d->host_data;
  233. int index;
  234. struct grgpio_lirq *lirq;
  235. struct grgpio_uirq *uirq;
  236. unsigned long flags;
  237. int ngpio = priv->gc.ngpio;
  238. int i;
  239. irq_set_chip_and_handler(irq, NULL, NULL);
  240. irq_set_chip_data(irq, NULL);
  241. spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
  242. /* Free underlying irq if last user unmapped */
  243. index = -1;
  244. for (i = 0; i < ngpio; i++) {
  245. lirq = &priv->lirqs[i];
  246. if (lirq->irq == irq) {
  247. grgpio_set_imask(priv, i, 0);
  248. lirq->irq = 0;
  249. index = lirq->index;
  250. break;
  251. }
  252. }
  253. WARN_ON(index < 0);
  254. if (index >= 0) {
  255. uirq = &priv->uirqs[lirq->index];
  256. uirq->refcnt--;
  257. if (uirq->refcnt == 0) {
  258. spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
  259. free_irq(uirq->uirq, priv);
  260. return;
  261. }
  262. }
  263. spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
  264. }
  265. static const struct irq_domain_ops grgpio_irq_domain_ops = {
  266. .map = grgpio_irq_map,
  267. .unmap = grgpio_irq_unmap,
  268. };
  269. /* ------------------------------------------------------------ */
  270. static int grgpio_probe(struct platform_device *ofdev)
  271. {
  272. struct device_node *np = ofdev->dev.of_node;
  273. void __iomem *regs;
  274. struct gpio_chip *gc;
  275. struct grgpio_priv *priv;
  276. int err;
  277. u32 prop;
  278. s32 *irqmap;
  279. int size;
  280. int i;
  281. priv = devm_kzalloc(&ofdev->dev, sizeof(*priv), GFP_KERNEL);
  282. if (!priv)
  283. return -ENOMEM;
  284. regs = devm_platform_ioremap_resource(ofdev, 0);
  285. if (IS_ERR(regs))
  286. return PTR_ERR(regs);
  287. gc = &priv->gc;
  288. err = bgpio_init(gc, &ofdev->dev, 4, regs + GRGPIO_DATA,
  289. regs + GRGPIO_OUTPUT, NULL, regs + GRGPIO_DIR, NULL,
  290. BGPIOF_BIG_ENDIAN_BYTE_ORDER);
  291. if (err) {
  292. dev_err(&ofdev->dev, "bgpio_init() failed\n");
  293. return err;
  294. }
  295. priv->regs = regs;
  296. priv->imask = gc->read_reg(regs + GRGPIO_IMASK);
  297. priv->dev = &ofdev->dev;
  298. gc->of_node = np;
  299. gc->owner = THIS_MODULE;
  300. gc->to_irq = grgpio_to_irq;
  301. gc->label = devm_kasprintf(&ofdev->dev, GFP_KERNEL, "%pOF", np);
  302. gc->base = -1;
  303. err = of_property_read_u32(np, "nbits", &prop);
  304. if (err || prop <= 0 || prop > GRGPIO_MAX_NGPIO) {
  305. gc->ngpio = GRGPIO_MAX_NGPIO;
  306. dev_dbg(&ofdev->dev,
  307. "No or invalid nbits property: assume %d\n", gc->ngpio);
  308. } else {
  309. gc->ngpio = prop;
  310. }
  311. /*
  312. * The irqmap contains the index values indicating which underlying irq,
  313. * if anyone, is connected to that line
  314. */
  315. irqmap = (s32 *)of_get_property(np, "irqmap", &size);
  316. if (irqmap) {
  317. if (size < gc->ngpio) {
  318. dev_err(&ofdev->dev,
  319. "irqmap shorter than ngpio (%d < %d)\n",
  320. size, gc->ngpio);
  321. return -EINVAL;
  322. }
  323. priv->domain = irq_domain_add_linear(np, gc->ngpio,
  324. &grgpio_irq_domain_ops,
  325. priv);
  326. if (!priv->domain) {
  327. dev_err(&ofdev->dev, "Could not add irq domain\n");
  328. return -EINVAL;
  329. }
  330. for (i = 0; i < gc->ngpio; i++) {
  331. struct grgpio_lirq *lirq;
  332. int ret;
  333. lirq = &priv->lirqs[i];
  334. lirq->index = irqmap[i];
  335. if (lirq->index < 0)
  336. continue;
  337. ret = platform_get_irq(ofdev, lirq->index);
  338. if (ret <= 0) {
  339. /*
  340. * Continue without irq functionality for that
  341. * gpio line
  342. */
  343. continue;
  344. }
  345. priv->uirqs[lirq->index].uirq = ret;
  346. }
  347. }
  348. platform_set_drvdata(ofdev, priv);
  349. err = gpiochip_add_data(gc, priv);
  350. if (err) {
  351. dev_err(&ofdev->dev, "Could not add gpiochip\n");
  352. if (priv->domain)
  353. irq_domain_remove(priv->domain);
  354. return err;
  355. }
  356. dev_info(&ofdev->dev, "regs=0x%p, base=%d, ngpio=%d, irqs=%s\n",
  357. priv->regs, gc->base, gc->ngpio, priv->domain ? "on" : "off");
  358. return 0;
  359. }
  360. static int grgpio_remove(struct platform_device *ofdev)
  361. {
  362. struct grgpio_priv *priv = platform_get_drvdata(ofdev);
  363. int i;
  364. int ret = 0;
  365. if (priv->domain) {
  366. for (i = 0; i < GRGPIO_MAX_NGPIO; i++) {
  367. if (priv->uirqs[i].refcnt != 0) {
  368. ret = -EBUSY;
  369. goto out;
  370. }
  371. }
  372. }
  373. gpiochip_remove(&priv->gc);
  374. if (priv->domain)
  375. irq_domain_remove(priv->domain);
  376. out:
  377. return ret;
  378. }
  379. static const struct of_device_id grgpio_match[] = {
  380. {.name = "GAISLER_GPIO"},
  381. {.name = "01_01a"},
  382. {},
  383. };
  384. MODULE_DEVICE_TABLE(of, grgpio_match);
  385. static struct platform_driver grgpio_driver = {
  386. .driver = {
  387. .name = "grgpio",
  388. .of_match_table = grgpio_match,
  389. },
  390. .probe = grgpio_probe,
  391. .remove = grgpio_remove,
  392. };
  393. module_platform_driver(grgpio_driver);
  394. MODULE_AUTHOR("Aeroflex Gaisler AB.");
  395. MODULE_DESCRIPTION("Driver for Aeroflex Gaisler GRGPIO");
  396. MODULE_LICENSE("GPL");