gpio-f7188x.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * GPIO driver for Fintek Super-I/O F71869, F71869A, F71882, F71889 and F81866
  4. *
  5. * Copyright (C) 2010-2013 LaCie
  6. *
  7. * Author: Simon Guinot <simon.guinot@sequanux.org>
  8. */
  9. #include <linux/module.h>
  10. #include <linux/init.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/io.h>
  13. #include <linux/gpio/driver.h>
  14. #include <linux/bitops.h>
  15. #define DRVNAME "gpio-f7188x"
  16. /*
  17. * Super-I/O registers
  18. */
  19. #define SIO_LDSEL 0x07 /* Logical device select */
  20. #define SIO_DEVID 0x20 /* Device ID (2 bytes) */
  21. #define SIO_DEVREV 0x22 /* Device revision */
  22. #define SIO_MANID 0x23 /* Fintek ID (2 bytes) */
  23. #define SIO_LD_GPIO 0x06 /* GPIO logical device */
  24. #define SIO_UNLOCK_KEY 0x87 /* Key to enable Super-I/O */
  25. #define SIO_LOCK_KEY 0xAA /* Key to disable Super-I/O */
  26. #define SIO_FINTEK_ID 0x1934 /* Manufacturer ID */
  27. #define SIO_F71869_ID 0x0814 /* F71869 chipset ID */
  28. #define SIO_F71869A_ID 0x1007 /* F71869A chipset ID */
  29. #define SIO_F71882_ID 0x0541 /* F71882 chipset ID */
  30. #define SIO_F71889_ID 0x0909 /* F71889 chipset ID */
  31. #define SIO_F71889A_ID 0x1005 /* F71889A chipset ID */
  32. #define SIO_F81866_ID 0x1010 /* F81866 chipset ID */
  33. #define SIO_F81804_ID 0x1502 /* F81804 chipset ID, same for f81966 */
  34. #define SIO_F81865_ID 0x0704 /* F81865 chipset ID */
  35. enum chips {
  36. f71869,
  37. f71869a,
  38. f71882fg,
  39. f71889a,
  40. f71889f,
  41. f81866,
  42. f81804,
  43. f81865,
  44. };
  45. static const char * const f7188x_names[] = {
  46. "f71869",
  47. "f71869a",
  48. "f71882fg",
  49. "f71889a",
  50. "f71889f",
  51. "f81866",
  52. "f81804",
  53. "f81865",
  54. };
  55. struct f7188x_sio {
  56. int addr;
  57. enum chips type;
  58. };
  59. struct f7188x_gpio_bank {
  60. struct gpio_chip chip;
  61. unsigned int regbase;
  62. struct f7188x_gpio_data *data;
  63. };
  64. struct f7188x_gpio_data {
  65. struct f7188x_sio *sio;
  66. int nr_bank;
  67. struct f7188x_gpio_bank *bank;
  68. };
  69. /*
  70. * Super-I/O functions.
  71. */
  72. static inline int superio_inb(int base, int reg)
  73. {
  74. outb(reg, base);
  75. return inb(base + 1);
  76. }
  77. static int superio_inw(int base, int reg)
  78. {
  79. int val;
  80. outb(reg++, base);
  81. val = inb(base + 1) << 8;
  82. outb(reg, base);
  83. val |= inb(base + 1);
  84. return val;
  85. }
  86. static inline void superio_outb(int base, int reg, int val)
  87. {
  88. outb(reg, base);
  89. outb(val, base + 1);
  90. }
  91. static inline int superio_enter(int base)
  92. {
  93. /* Don't step on other drivers' I/O space by accident. */
  94. if (!request_muxed_region(base, 2, DRVNAME)) {
  95. pr_err(DRVNAME "I/O address 0x%04x already in use\n", base);
  96. return -EBUSY;
  97. }
  98. /* According to the datasheet the key must be send twice. */
  99. outb(SIO_UNLOCK_KEY, base);
  100. outb(SIO_UNLOCK_KEY, base);
  101. return 0;
  102. }
  103. static inline void superio_select(int base, int ld)
  104. {
  105. outb(SIO_LDSEL, base);
  106. outb(ld, base + 1);
  107. }
  108. static inline void superio_exit(int base)
  109. {
  110. outb(SIO_LOCK_KEY, base);
  111. release_region(base, 2);
  112. }
  113. /*
  114. * GPIO chip.
  115. */
  116. static int f7188x_gpio_get_direction(struct gpio_chip *chip, unsigned offset);
  117. static int f7188x_gpio_direction_in(struct gpio_chip *chip, unsigned offset);
  118. static int f7188x_gpio_get(struct gpio_chip *chip, unsigned offset);
  119. static int f7188x_gpio_direction_out(struct gpio_chip *chip,
  120. unsigned offset, int value);
  121. static void f7188x_gpio_set(struct gpio_chip *chip, unsigned offset, int value);
  122. static int f7188x_gpio_set_config(struct gpio_chip *chip, unsigned offset,
  123. unsigned long config);
  124. #define F7188X_GPIO_BANK(_base, _ngpio, _regbase) \
  125. { \
  126. .chip = { \
  127. .label = DRVNAME, \
  128. .owner = THIS_MODULE, \
  129. .get_direction = f7188x_gpio_get_direction, \
  130. .direction_input = f7188x_gpio_direction_in, \
  131. .get = f7188x_gpio_get, \
  132. .direction_output = f7188x_gpio_direction_out, \
  133. .set = f7188x_gpio_set, \
  134. .set_config = f7188x_gpio_set_config, \
  135. .base = _base, \
  136. .ngpio = _ngpio, \
  137. .can_sleep = true, \
  138. }, \
  139. .regbase = _regbase, \
  140. }
  141. #define gpio_dir(base) (base + 0)
  142. #define gpio_data_out(base) (base + 1)
  143. #define gpio_data_in(base) (base + 2)
  144. /* Output mode register (0:open drain 1:push-pull). */
  145. #define gpio_out_mode(base) (base + 3)
  146. static struct f7188x_gpio_bank f71869_gpio_bank[] = {
  147. F7188X_GPIO_BANK(0, 6, 0xF0),
  148. F7188X_GPIO_BANK(10, 8, 0xE0),
  149. F7188X_GPIO_BANK(20, 8, 0xD0),
  150. F7188X_GPIO_BANK(30, 8, 0xC0),
  151. F7188X_GPIO_BANK(40, 8, 0xB0),
  152. F7188X_GPIO_BANK(50, 5, 0xA0),
  153. F7188X_GPIO_BANK(60, 6, 0x90),
  154. };
  155. static struct f7188x_gpio_bank f71869a_gpio_bank[] = {
  156. F7188X_GPIO_BANK(0, 6, 0xF0),
  157. F7188X_GPIO_BANK(10, 8, 0xE0),
  158. F7188X_GPIO_BANK(20, 8, 0xD0),
  159. F7188X_GPIO_BANK(30, 8, 0xC0),
  160. F7188X_GPIO_BANK(40, 8, 0xB0),
  161. F7188X_GPIO_BANK(50, 5, 0xA0),
  162. F7188X_GPIO_BANK(60, 8, 0x90),
  163. F7188X_GPIO_BANK(70, 8, 0x80),
  164. };
  165. static struct f7188x_gpio_bank f71882_gpio_bank[] = {
  166. F7188X_GPIO_BANK(0, 8, 0xF0),
  167. F7188X_GPIO_BANK(10, 8, 0xE0),
  168. F7188X_GPIO_BANK(20, 8, 0xD0),
  169. F7188X_GPIO_BANK(30, 4, 0xC0),
  170. F7188X_GPIO_BANK(40, 4, 0xB0),
  171. };
  172. static struct f7188x_gpio_bank f71889a_gpio_bank[] = {
  173. F7188X_GPIO_BANK(0, 7, 0xF0),
  174. F7188X_GPIO_BANK(10, 7, 0xE0),
  175. F7188X_GPIO_BANK(20, 8, 0xD0),
  176. F7188X_GPIO_BANK(30, 8, 0xC0),
  177. F7188X_GPIO_BANK(40, 8, 0xB0),
  178. F7188X_GPIO_BANK(50, 5, 0xA0),
  179. F7188X_GPIO_BANK(60, 8, 0x90),
  180. F7188X_GPIO_BANK(70, 8, 0x80),
  181. };
  182. static struct f7188x_gpio_bank f71889_gpio_bank[] = {
  183. F7188X_GPIO_BANK(0, 7, 0xF0),
  184. F7188X_GPIO_BANK(10, 7, 0xE0),
  185. F7188X_GPIO_BANK(20, 8, 0xD0),
  186. F7188X_GPIO_BANK(30, 8, 0xC0),
  187. F7188X_GPIO_BANK(40, 8, 0xB0),
  188. F7188X_GPIO_BANK(50, 5, 0xA0),
  189. F7188X_GPIO_BANK(60, 8, 0x90),
  190. F7188X_GPIO_BANK(70, 8, 0x80),
  191. };
  192. static struct f7188x_gpio_bank f81866_gpio_bank[] = {
  193. F7188X_GPIO_BANK(0, 8, 0xF0),
  194. F7188X_GPIO_BANK(10, 8, 0xE0),
  195. F7188X_GPIO_BANK(20, 8, 0xD0),
  196. F7188X_GPIO_BANK(30, 8, 0xC0),
  197. F7188X_GPIO_BANK(40, 8, 0xB0),
  198. F7188X_GPIO_BANK(50, 8, 0xA0),
  199. F7188X_GPIO_BANK(60, 8, 0x90),
  200. F7188X_GPIO_BANK(70, 8, 0x80),
  201. F7188X_GPIO_BANK(80, 8, 0x88),
  202. };
  203. static struct f7188x_gpio_bank f81804_gpio_bank[] = {
  204. F7188X_GPIO_BANK(0, 8, 0xF0),
  205. F7188X_GPIO_BANK(10, 8, 0xE0),
  206. F7188X_GPIO_BANK(20, 8, 0xD0),
  207. F7188X_GPIO_BANK(50, 8, 0xA0),
  208. F7188X_GPIO_BANK(60, 8, 0x90),
  209. F7188X_GPIO_BANK(70, 8, 0x80),
  210. F7188X_GPIO_BANK(90, 8, 0x98),
  211. };
  212. static struct f7188x_gpio_bank f81865_gpio_bank[] = {
  213. F7188X_GPIO_BANK(0, 8, 0xF0),
  214. F7188X_GPIO_BANK(10, 8, 0xE0),
  215. F7188X_GPIO_BANK(20, 8, 0xD0),
  216. F7188X_GPIO_BANK(30, 8, 0xC0),
  217. F7188X_GPIO_BANK(40, 8, 0xB0),
  218. F7188X_GPIO_BANK(50, 8, 0xA0),
  219. F7188X_GPIO_BANK(60, 5, 0x90),
  220. };
  221. static int f7188x_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
  222. {
  223. int err;
  224. struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
  225. struct f7188x_sio *sio = bank->data->sio;
  226. u8 dir;
  227. err = superio_enter(sio->addr);
  228. if (err)
  229. return err;
  230. superio_select(sio->addr, SIO_LD_GPIO);
  231. dir = superio_inb(sio->addr, gpio_dir(bank->regbase));
  232. superio_exit(sio->addr);
  233. if (dir & 1 << offset)
  234. return GPIO_LINE_DIRECTION_OUT;
  235. return GPIO_LINE_DIRECTION_IN;
  236. }
  237. static int f7188x_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
  238. {
  239. int err;
  240. struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
  241. struct f7188x_sio *sio = bank->data->sio;
  242. u8 dir;
  243. err = superio_enter(sio->addr);
  244. if (err)
  245. return err;
  246. superio_select(sio->addr, SIO_LD_GPIO);
  247. dir = superio_inb(sio->addr, gpio_dir(bank->regbase));
  248. dir &= ~BIT(offset);
  249. superio_outb(sio->addr, gpio_dir(bank->regbase), dir);
  250. superio_exit(sio->addr);
  251. return 0;
  252. }
  253. static int f7188x_gpio_get(struct gpio_chip *chip, unsigned offset)
  254. {
  255. int err;
  256. struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
  257. struct f7188x_sio *sio = bank->data->sio;
  258. u8 dir, data;
  259. err = superio_enter(sio->addr);
  260. if (err)
  261. return err;
  262. superio_select(sio->addr, SIO_LD_GPIO);
  263. dir = superio_inb(sio->addr, gpio_dir(bank->regbase));
  264. dir = !!(dir & BIT(offset));
  265. if (dir)
  266. data = superio_inb(sio->addr, gpio_data_out(bank->regbase));
  267. else
  268. data = superio_inb(sio->addr, gpio_data_in(bank->regbase));
  269. superio_exit(sio->addr);
  270. return !!(data & BIT(offset));
  271. }
  272. static int f7188x_gpio_direction_out(struct gpio_chip *chip,
  273. unsigned offset, int value)
  274. {
  275. int err;
  276. struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
  277. struct f7188x_sio *sio = bank->data->sio;
  278. u8 dir, data_out;
  279. err = superio_enter(sio->addr);
  280. if (err)
  281. return err;
  282. superio_select(sio->addr, SIO_LD_GPIO);
  283. data_out = superio_inb(sio->addr, gpio_data_out(bank->regbase));
  284. if (value)
  285. data_out |= BIT(offset);
  286. else
  287. data_out &= ~BIT(offset);
  288. superio_outb(sio->addr, gpio_data_out(bank->regbase), data_out);
  289. dir = superio_inb(sio->addr, gpio_dir(bank->regbase));
  290. dir |= BIT(offset);
  291. superio_outb(sio->addr, gpio_dir(bank->regbase), dir);
  292. superio_exit(sio->addr);
  293. return 0;
  294. }
  295. static void f7188x_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
  296. {
  297. int err;
  298. struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
  299. struct f7188x_sio *sio = bank->data->sio;
  300. u8 data_out;
  301. err = superio_enter(sio->addr);
  302. if (err)
  303. return;
  304. superio_select(sio->addr, SIO_LD_GPIO);
  305. data_out = superio_inb(sio->addr, gpio_data_out(bank->regbase));
  306. if (value)
  307. data_out |= BIT(offset);
  308. else
  309. data_out &= ~BIT(offset);
  310. superio_outb(sio->addr, gpio_data_out(bank->regbase), data_out);
  311. superio_exit(sio->addr);
  312. }
  313. static int f7188x_gpio_set_config(struct gpio_chip *chip, unsigned offset,
  314. unsigned long config)
  315. {
  316. int err;
  317. enum pin_config_param param = pinconf_to_config_param(config);
  318. struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
  319. struct f7188x_sio *sio = bank->data->sio;
  320. u8 data;
  321. if (param != PIN_CONFIG_DRIVE_OPEN_DRAIN &&
  322. param != PIN_CONFIG_DRIVE_PUSH_PULL)
  323. return -ENOTSUPP;
  324. err = superio_enter(sio->addr);
  325. if (err)
  326. return err;
  327. superio_select(sio->addr, SIO_LD_GPIO);
  328. data = superio_inb(sio->addr, gpio_out_mode(bank->regbase));
  329. if (param == PIN_CONFIG_DRIVE_OPEN_DRAIN)
  330. data &= ~BIT(offset);
  331. else
  332. data |= BIT(offset);
  333. superio_outb(sio->addr, gpio_out_mode(bank->regbase), data);
  334. superio_exit(sio->addr);
  335. return 0;
  336. }
  337. /*
  338. * Platform device and driver.
  339. */
  340. static int f7188x_gpio_probe(struct platform_device *pdev)
  341. {
  342. int err;
  343. int i;
  344. struct f7188x_sio *sio = dev_get_platdata(&pdev->dev);
  345. struct f7188x_gpio_data *data;
  346. data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
  347. if (!data)
  348. return -ENOMEM;
  349. switch (sio->type) {
  350. case f71869:
  351. data->nr_bank = ARRAY_SIZE(f71869_gpio_bank);
  352. data->bank = f71869_gpio_bank;
  353. break;
  354. case f71869a:
  355. data->nr_bank = ARRAY_SIZE(f71869a_gpio_bank);
  356. data->bank = f71869a_gpio_bank;
  357. break;
  358. case f71882fg:
  359. data->nr_bank = ARRAY_SIZE(f71882_gpio_bank);
  360. data->bank = f71882_gpio_bank;
  361. break;
  362. case f71889a:
  363. data->nr_bank = ARRAY_SIZE(f71889a_gpio_bank);
  364. data->bank = f71889a_gpio_bank;
  365. break;
  366. case f71889f:
  367. data->nr_bank = ARRAY_SIZE(f71889_gpio_bank);
  368. data->bank = f71889_gpio_bank;
  369. break;
  370. case f81866:
  371. data->nr_bank = ARRAY_SIZE(f81866_gpio_bank);
  372. data->bank = f81866_gpio_bank;
  373. break;
  374. case f81804:
  375. data->nr_bank = ARRAY_SIZE(f81804_gpio_bank);
  376. data->bank = f81804_gpio_bank;
  377. break;
  378. case f81865:
  379. data->nr_bank = ARRAY_SIZE(f81865_gpio_bank);
  380. data->bank = f81865_gpio_bank;
  381. break;
  382. default:
  383. return -ENODEV;
  384. }
  385. data->sio = sio;
  386. platform_set_drvdata(pdev, data);
  387. /* For each GPIO bank, register a GPIO chip. */
  388. for (i = 0; i < data->nr_bank; i++) {
  389. struct f7188x_gpio_bank *bank = &data->bank[i];
  390. bank->chip.parent = &pdev->dev;
  391. bank->data = data;
  392. err = devm_gpiochip_add_data(&pdev->dev, &bank->chip, bank);
  393. if (err) {
  394. dev_err(&pdev->dev,
  395. "Failed to register gpiochip %d: %d\n",
  396. i, err);
  397. return err;
  398. }
  399. }
  400. return 0;
  401. }
  402. static int __init f7188x_find(int addr, struct f7188x_sio *sio)
  403. {
  404. int err;
  405. u16 devid;
  406. err = superio_enter(addr);
  407. if (err)
  408. return err;
  409. err = -ENODEV;
  410. devid = superio_inw(addr, SIO_MANID);
  411. if (devid != SIO_FINTEK_ID) {
  412. pr_debug(DRVNAME ": Not a Fintek device at 0x%08x\n", addr);
  413. goto err;
  414. }
  415. devid = superio_inw(addr, SIO_DEVID);
  416. switch (devid) {
  417. case SIO_F71869_ID:
  418. sio->type = f71869;
  419. break;
  420. case SIO_F71869A_ID:
  421. sio->type = f71869a;
  422. break;
  423. case SIO_F71882_ID:
  424. sio->type = f71882fg;
  425. break;
  426. case SIO_F71889A_ID:
  427. sio->type = f71889a;
  428. break;
  429. case SIO_F71889_ID:
  430. sio->type = f71889f;
  431. break;
  432. case SIO_F81866_ID:
  433. sio->type = f81866;
  434. break;
  435. case SIO_F81804_ID:
  436. sio->type = f81804;
  437. break;
  438. case SIO_F81865_ID:
  439. sio->type = f81865;
  440. break;
  441. default:
  442. pr_info(DRVNAME ": Unsupported Fintek device 0x%04x\n", devid);
  443. goto err;
  444. }
  445. sio->addr = addr;
  446. err = 0;
  447. pr_info(DRVNAME ": Found %s at %#x, revision %d\n",
  448. f7188x_names[sio->type],
  449. (unsigned int) addr,
  450. (int) superio_inb(addr, SIO_DEVREV));
  451. err:
  452. superio_exit(addr);
  453. return err;
  454. }
  455. static struct platform_device *f7188x_gpio_pdev;
  456. static int __init
  457. f7188x_gpio_device_add(const struct f7188x_sio *sio)
  458. {
  459. int err;
  460. f7188x_gpio_pdev = platform_device_alloc(DRVNAME, -1);
  461. if (!f7188x_gpio_pdev)
  462. return -ENOMEM;
  463. err = platform_device_add_data(f7188x_gpio_pdev,
  464. sio, sizeof(*sio));
  465. if (err) {
  466. pr_err(DRVNAME "Platform data allocation failed\n");
  467. goto err;
  468. }
  469. err = platform_device_add(f7188x_gpio_pdev);
  470. if (err) {
  471. pr_err(DRVNAME "Device addition failed\n");
  472. goto err;
  473. }
  474. return 0;
  475. err:
  476. platform_device_put(f7188x_gpio_pdev);
  477. return err;
  478. }
  479. /*
  480. * Try to match a supported Fintek device by reading the (hard-wired)
  481. * configuration I/O ports. If available, then register both the platform
  482. * device and driver to support the GPIOs.
  483. */
  484. static struct platform_driver f7188x_gpio_driver = {
  485. .driver = {
  486. .name = DRVNAME,
  487. },
  488. .probe = f7188x_gpio_probe,
  489. };
  490. static int __init f7188x_gpio_init(void)
  491. {
  492. int err;
  493. struct f7188x_sio sio;
  494. if (f7188x_find(0x2e, &sio) &&
  495. f7188x_find(0x4e, &sio))
  496. return -ENODEV;
  497. err = platform_driver_register(&f7188x_gpio_driver);
  498. if (!err) {
  499. err = f7188x_gpio_device_add(&sio);
  500. if (err)
  501. platform_driver_unregister(&f7188x_gpio_driver);
  502. }
  503. return err;
  504. }
  505. subsys_initcall(f7188x_gpio_init);
  506. static void __exit f7188x_gpio_exit(void)
  507. {
  508. platform_device_unregister(f7188x_gpio_pdev);
  509. platform_driver_unregister(&f7188x_gpio_driver);
  510. }
  511. module_exit(f7188x_gpio_exit);
  512. MODULE_DESCRIPTION("GPIO driver for Super-I/O chips F71869, F71869A, F71882FG, F71889A, F71889F and F81866");
  513. MODULE_AUTHOR("Simon Guinot <simon.guinot@sequanux.org>");
  514. MODULE_LICENSE("GPL");