gpio-em.c 9.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Emma Mobile GPIO Support - GIO
  4. *
  5. * Copyright (C) 2012 Magnus Damm
  6. */
  7. #include <linux/init.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/spinlock.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/ioport.h>
  12. #include <linux/io.h>
  13. #include <linux/irq.h>
  14. #include <linux/irqdomain.h>
  15. #include <linux/bitops.h>
  16. #include <linux/err.h>
  17. #include <linux/gpio/driver.h>
  18. #include <linux/slab.h>
  19. #include <linux/module.h>
  20. #include <linux/pinctrl/consumer.h>
  21. struct em_gio_priv {
  22. void __iomem *base0;
  23. void __iomem *base1;
  24. spinlock_t sense_lock;
  25. struct platform_device *pdev;
  26. struct gpio_chip gpio_chip;
  27. struct irq_chip irq_chip;
  28. struct irq_domain *irq_domain;
  29. };
  30. #define GIO_E1 0x00
  31. #define GIO_E0 0x04
  32. #define GIO_EM 0x04
  33. #define GIO_OL 0x08
  34. #define GIO_OH 0x0c
  35. #define GIO_I 0x10
  36. #define GIO_IIA 0x14
  37. #define GIO_IEN 0x18
  38. #define GIO_IDS 0x1c
  39. #define GIO_IIM 0x1c
  40. #define GIO_RAW 0x20
  41. #define GIO_MST 0x24
  42. #define GIO_IIR 0x28
  43. #define GIO_IDT0 0x40
  44. #define GIO_IDT1 0x44
  45. #define GIO_IDT2 0x48
  46. #define GIO_IDT3 0x4c
  47. #define GIO_RAWBL 0x50
  48. #define GIO_RAWBH 0x54
  49. #define GIO_IRBL 0x58
  50. #define GIO_IRBH 0x5c
  51. #define GIO_IDT(n) (GIO_IDT0 + ((n) * 4))
  52. static inline unsigned long em_gio_read(struct em_gio_priv *p, int offs)
  53. {
  54. if (offs < GIO_IDT0)
  55. return ioread32(p->base0 + offs);
  56. else
  57. return ioread32(p->base1 + (offs - GIO_IDT0));
  58. }
  59. static inline void em_gio_write(struct em_gio_priv *p, int offs,
  60. unsigned long value)
  61. {
  62. if (offs < GIO_IDT0)
  63. iowrite32(value, p->base0 + offs);
  64. else
  65. iowrite32(value, p->base1 + (offs - GIO_IDT0));
  66. }
  67. static void em_gio_irq_disable(struct irq_data *d)
  68. {
  69. struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
  70. em_gio_write(p, GIO_IDS, BIT(irqd_to_hwirq(d)));
  71. }
  72. static void em_gio_irq_enable(struct irq_data *d)
  73. {
  74. struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
  75. em_gio_write(p, GIO_IEN, BIT(irqd_to_hwirq(d)));
  76. }
  77. static int em_gio_irq_reqres(struct irq_data *d)
  78. {
  79. struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
  80. int ret;
  81. ret = gpiochip_lock_as_irq(&p->gpio_chip, irqd_to_hwirq(d));
  82. if (ret) {
  83. dev_err(p->gpio_chip.parent,
  84. "unable to lock HW IRQ %lu for IRQ\n",
  85. irqd_to_hwirq(d));
  86. return ret;
  87. }
  88. return 0;
  89. }
  90. static void em_gio_irq_relres(struct irq_data *d)
  91. {
  92. struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
  93. gpiochip_unlock_as_irq(&p->gpio_chip, irqd_to_hwirq(d));
  94. }
  95. #define GIO_ASYNC(x) (x + 8)
  96. static unsigned char em_gio_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
  97. [IRQ_TYPE_EDGE_RISING] = GIO_ASYNC(0x00),
  98. [IRQ_TYPE_EDGE_FALLING] = GIO_ASYNC(0x01),
  99. [IRQ_TYPE_LEVEL_HIGH] = GIO_ASYNC(0x02),
  100. [IRQ_TYPE_LEVEL_LOW] = GIO_ASYNC(0x03),
  101. [IRQ_TYPE_EDGE_BOTH] = GIO_ASYNC(0x04),
  102. };
  103. static int em_gio_irq_set_type(struct irq_data *d, unsigned int type)
  104. {
  105. unsigned char value = em_gio_sense_table[type & IRQ_TYPE_SENSE_MASK];
  106. struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
  107. unsigned int reg, offset, shift;
  108. unsigned long flags;
  109. unsigned long tmp;
  110. if (!value)
  111. return -EINVAL;
  112. offset = irqd_to_hwirq(d);
  113. pr_debug("gio: sense irq = %d, mode = %d\n", offset, value);
  114. /* 8 x 4 bit fields in 4 IDT registers */
  115. reg = GIO_IDT(offset >> 3);
  116. shift = (offset & 0x07) << 4;
  117. spin_lock_irqsave(&p->sense_lock, flags);
  118. /* disable the interrupt in IIA */
  119. tmp = em_gio_read(p, GIO_IIA);
  120. tmp &= ~BIT(offset);
  121. em_gio_write(p, GIO_IIA, tmp);
  122. /* change the sense setting in IDT */
  123. tmp = em_gio_read(p, reg);
  124. tmp &= ~(0xf << shift);
  125. tmp |= value << shift;
  126. em_gio_write(p, reg, tmp);
  127. /* clear pending interrupts */
  128. em_gio_write(p, GIO_IIR, BIT(offset));
  129. /* enable the interrupt in IIA */
  130. tmp = em_gio_read(p, GIO_IIA);
  131. tmp |= BIT(offset);
  132. em_gio_write(p, GIO_IIA, tmp);
  133. spin_unlock_irqrestore(&p->sense_lock, flags);
  134. return 0;
  135. }
  136. static irqreturn_t em_gio_irq_handler(int irq, void *dev_id)
  137. {
  138. struct em_gio_priv *p = dev_id;
  139. unsigned long pending;
  140. unsigned int offset, irqs_handled = 0;
  141. while ((pending = em_gio_read(p, GIO_MST))) {
  142. offset = __ffs(pending);
  143. em_gio_write(p, GIO_IIR, BIT(offset));
  144. generic_handle_irq(irq_find_mapping(p->irq_domain, offset));
  145. irqs_handled++;
  146. }
  147. return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
  148. }
  149. static inline struct em_gio_priv *gpio_to_priv(struct gpio_chip *chip)
  150. {
  151. return gpiochip_get_data(chip);
  152. }
  153. static int em_gio_direction_input(struct gpio_chip *chip, unsigned offset)
  154. {
  155. em_gio_write(gpio_to_priv(chip), GIO_E0, BIT(offset));
  156. return 0;
  157. }
  158. static int em_gio_get(struct gpio_chip *chip, unsigned offset)
  159. {
  160. return !!(em_gio_read(gpio_to_priv(chip), GIO_I) & BIT(offset));
  161. }
  162. static void __em_gio_set(struct gpio_chip *chip, unsigned int reg,
  163. unsigned shift, int value)
  164. {
  165. /* upper 16 bits contains mask and lower 16 actual value */
  166. em_gio_write(gpio_to_priv(chip), reg,
  167. (BIT(shift + 16)) | (value << shift));
  168. }
  169. static void em_gio_set(struct gpio_chip *chip, unsigned offset, int value)
  170. {
  171. /* output is split into two registers */
  172. if (offset < 16)
  173. __em_gio_set(chip, GIO_OL, offset, value);
  174. else
  175. __em_gio_set(chip, GIO_OH, offset - 16, value);
  176. }
  177. static int em_gio_direction_output(struct gpio_chip *chip, unsigned offset,
  178. int value)
  179. {
  180. /* write GPIO value to output before selecting output mode of pin */
  181. em_gio_set(chip, offset, value);
  182. em_gio_write(gpio_to_priv(chip), GIO_E1, BIT(offset));
  183. return 0;
  184. }
  185. static int em_gio_to_irq(struct gpio_chip *chip, unsigned offset)
  186. {
  187. return irq_create_mapping(gpio_to_priv(chip)->irq_domain, offset);
  188. }
  189. static int em_gio_request(struct gpio_chip *chip, unsigned offset)
  190. {
  191. return pinctrl_gpio_request(chip->base + offset);
  192. }
  193. static void em_gio_free(struct gpio_chip *chip, unsigned offset)
  194. {
  195. pinctrl_gpio_free(chip->base + offset);
  196. /* Set the GPIO as an input to ensure that the next GPIO request won't
  197. * drive the GPIO pin as an output.
  198. */
  199. em_gio_direction_input(chip, offset);
  200. }
  201. static int em_gio_irq_domain_map(struct irq_domain *h, unsigned int irq,
  202. irq_hw_number_t hwirq)
  203. {
  204. struct em_gio_priv *p = h->host_data;
  205. pr_debug("gio: map hw irq = %d, irq = %d\n", (int)hwirq, irq);
  206. irq_set_chip_data(irq, h->host_data);
  207. irq_set_chip_and_handler(irq, &p->irq_chip, handle_level_irq);
  208. return 0;
  209. }
  210. static const struct irq_domain_ops em_gio_irq_domain_ops = {
  211. .map = em_gio_irq_domain_map,
  212. .xlate = irq_domain_xlate_twocell,
  213. };
  214. static void em_gio_irq_domain_remove(void *data)
  215. {
  216. struct irq_domain *domain = data;
  217. irq_domain_remove(domain);
  218. }
  219. static int em_gio_probe(struct platform_device *pdev)
  220. {
  221. struct em_gio_priv *p;
  222. struct gpio_chip *gpio_chip;
  223. struct irq_chip *irq_chip;
  224. struct device *dev = &pdev->dev;
  225. const char *name = dev_name(dev);
  226. unsigned int ngpios;
  227. int irq[2], ret;
  228. p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
  229. if (!p)
  230. return -ENOMEM;
  231. p->pdev = pdev;
  232. platform_set_drvdata(pdev, p);
  233. spin_lock_init(&p->sense_lock);
  234. irq[0] = platform_get_irq(pdev, 0);
  235. if (irq[0] < 0)
  236. return irq[0];
  237. irq[1] = platform_get_irq(pdev, 1);
  238. if (irq[1] < 0)
  239. return irq[1];
  240. p->base0 = devm_platform_ioremap_resource(pdev, 0);
  241. if (IS_ERR(p->base0))
  242. return PTR_ERR(p->base0);
  243. p->base1 = devm_platform_ioremap_resource(pdev, 1);
  244. if (IS_ERR(p->base1))
  245. return PTR_ERR(p->base1);
  246. if (of_property_read_u32(dev->of_node, "ngpios", &ngpios)) {
  247. dev_err(dev, "Missing ngpios OF property\n");
  248. return -EINVAL;
  249. }
  250. gpio_chip = &p->gpio_chip;
  251. gpio_chip->of_node = dev->of_node;
  252. gpio_chip->direction_input = em_gio_direction_input;
  253. gpio_chip->get = em_gio_get;
  254. gpio_chip->direction_output = em_gio_direction_output;
  255. gpio_chip->set = em_gio_set;
  256. gpio_chip->to_irq = em_gio_to_irq;
  257. gpio_chip->request = em_gio_request;
  258. gpio_chip->free = em_gio_free;
  259. gpio_chip->label = name;
  260. gpio_chip->parent = dev;
  261. gpio_chip->owner = THIS_MODULE;
  262. gpio_chip->base = -1;
  263. gpio_chip->ngpio = ngpios;
  264. irq_chip = &p->irq_chip;
  265. irq_chip->name = "gpio-em";
  266. irq_chip->irq_mask = em_gio_irq_disable;
  267. irq_chip->irq_unmask = em_gio_irq_enable;
  268. irq_chip->irq_set_type = em_gio_irq_set_type;
  269. irq_chip->irq_request_resources = em_gio_irq_reqres;
  270. irq_chip->irq_release_resources = em_gio_irq_relres;
  271. irq_chip->flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND;
  272. p->irq_domain = irq_domain_add_simple(dev->of_node, ngpios, 0,
  273. &em_gio_irq_domain_ops, p);
  274. if (!p->irq_domain) {
  275. dev_err(dev, "cannot initialize irq domain\n");
  276. return -ENXIO;
  277. }
  278. ret = devm_add_action_or_reset(dev, em_gio_irq_domain_remove,
  279. p->irq_domain);
  280. if (ret)
  281. return ret;
  282. if (devm_request_irq(dev, irq[0], em_gio_irq_handler, 0, name, p)) {
  283. dev_err(dev, "failed to request low IRQ\n");
  284. return -ENOENT;
  285. }
  286. if (devm_request_irq(dev, irq[1], em_gio_irq_handler, 0, name, p)) {
  287. dev_err(dev, "failed to request high IRQ\n");
  288. return -ENOENT;
  289. }
  290. ret = devm_gpiochip_add_data(dev, gpio_chip, p);
  291. if (ret) {
  292. dev_err(dev, "failed to add GPIO controller\n");
  293. return ret;
  294. }
  295. return 0;
  296. }
  297. static const struct of_device_id em_gio_dt_ids[] = {
  298. { .compatible = "renesas,em-gio", },
  299. {},
  300. };
  301. MODULE_DEVICE_TABLE(of, em_gio_dt_ids);
  302. static struct platform_driver em_gio_device_driver = {
  303. .probe = em_gio_probe,
  304. .driver = {
  305. .name = "em_gio",
  306. .of_match_table = em_gio_dt_ids,
  307. }
  308. };
  309. static int __init em_gio_init(void)
  310. {
  311. return platform_driver_register(&em_gio_device_driver);
  312. }
  313. postcore_initcall(em_gio_init);
  314. static void __exit em_gio_exit(void)
  315. {
  316. platform_driver_unregister(&em_gio_device_driver);
  317. }
  318. module_exit(em_gio_exit);
  319. MODULE_AUTHOR("Magnus Damm");
  320. MODULE_DESCRIPTION("Renesas Emma Mobile GIO Driver");
  321. MODULE_LICENSE("GPL v2");