gpio-eic-sprd.c 19 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2018 Spreadtrum Communications Inc.
  4. * Copyright (C) 2018 Linaro Ltd.
  5. */
  6. #include <linux/bitops.h>
  7. #include <linux/gpio/driver.h>
  8. #include <linux/interrupt.h>
  9. #include <linux/kernel.h>
  10. #include <linux/module.h>
  11. #include <linux/of_device.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/spinlock.h>
  14. /* EIC registers definition */
  15. #define SPRD_EIC_DBNC_DATA 0x0
  16. #define SPRD_EIC_DBNC_DMSK 0x4
  17. #define SPRD_EIC_DBNC_IEV 0x14
  18. #define SPRD_EIC_DBNC_IE 0x18
  19. #define SPRD_EIC_DBNC_RIS 0x1c
  20. #define SPRD_EIC_DBNC_MIS 0x20
  21. #define SPRD_EIC_DBNC_IC 0x24
  22. #define SPRD_EIC_DBNC_TRIG 0x28
  23. #define SPRD_EIC_DBNC_CTRL0 0x40
  24. #define SPRD_EIC_LATCH_INTEN 0x0
  25. #define SPRD_EIC_LATCH_INTRAW 0x4
  26. #define SPRD_EIC_LATCH_INTMSK 0x8
  27. #define SPRD_EIC_LATCH_INTCLR 0xc
  28. #define SPRD_EIC_LATCH_INTPOL 0x10
  29. #define SPRD_EIC_LATCH_INTMODE 0x14
  30. #define SPRD_EIC_ASYNC_INTIE 0x0
  31. #define SPRD_EIC_ASYNC_INTRAW 0x4
  32. #define SPRD_EIC_ASYNC_INTMSK 0x8
  33. #define SPRD_EIC_ASYNC_INTCLR 0xc
  34. #define SPRD_EIC_ASYNC_INTMODE 0x10
  35. #define SPRD_EIC_ASYNC_INTBOTH 0x14
  36. #define SPRD_EIC_ASYNC_INTPOL 0x18
  37. #define SPRD_EIC_ASYNC_DATA 0x1c
  38. #define SPRD_EIC_SYNC_INTIE 0x0
  39. #define SPRD_EIC_SYNC_INTRAW 0x4
  40. #define SPRD_EIC_SYNC_INTMSK 0x8
  41. #define SPRD_EIC_SYNC_INTCLR 0xc
  42. #define SPRD_EIC_SYNC_INTMODE 0x10
  43. #define SPRD_EIC_SYNC_INTBOTH 0x14
  44. #define SPRD_EIC_SYNC_INTPOL 0x18
  45. #define SPRD_EIC_SYNC_DATA 0x1c
  46. /*
  47. * The digital-chip EIC controller can support maximum 3 banks, and each bank
  48. * contains 8 EICs.
  49. */
  50. #define SPRD_EIC_MAX_BANK 3
  51. #define SPRD_EIC_PER_BANK_NR 8
  52. #define SPRD_EIC_DATA_MASK GENMASK(7, 0)
  53. #define SPRD_EIC_BIT(x) ((x) & (SPRD_EIC_PER_BANK_NR - 1))
  54. #define SPRD_EIC_DBNC_MASK GENMASK(11, 0)
  55. /*
  56. * The Spreadtrum EIC (external interrupt controller) can be used only in
  57. * input mode to generate interrupts if detecting input signals.
  58. *
  59. * The Spreadtrum digital-chip EIC controller contains 4 sub-modules:
  60. * debounce EIC, latch EIC, async EIC and sync EIC,
  61. *
  62. * The debounce EIC is used to capture the input signals' stable status
  63. * (millisecond resolution) and a single-trigger mechanism is introduced
  64. * into this sub-module to enhance the input event detection reliability.
  65. * The debounce range is from 1ms to 4s with a step size of 1ms.
  66. *
  67. * The latch EIC is used to latch some special power down signals and
  68. * generate interrupts, since the latch EIC does not depend on the APB clock
  69. * to capture signals.
  70. *
  71. * The async EIC uses a 32k clock to capture the short signals (microsecond
  72. * resolution) to generate interrupts by level or edge trigger.
  73. *
  74. * The EIC-sync is similar with GPIO's input function, which is a synchronized
  75. * signal input register.
  76. */
  77. enum sprd_eic_type {
  78. SPRD_EIC_DEBOUNCE,
  79. SPRD_EIC_LATCH,
  80. SPRD_EIC_ASYNC,
  81. SPRD_EIC_SYNC,
  82. SPRD_EIC_MAX,
  83. };
  84. struct sprd_eic {
  85. struct gpio_chip chip;
  86. struct irq_chip intc;
  87. void __iomem *base[SPRD_EIC_MAX_BANK];
  88. enum sprd_eic_type type;
  89. spinlock_t lock;
  90. int irq;
  91. };
  92. struct sprd_eic_variant_data {
  93. enum sprd_eic_type type;
  94. u32 num_eics;
  95. };
  96. static const char *sprd_eic_label_name[SPRD_EIC_MAX] = {
  97. "eic-debounce", "eic-latch", "eic-async",
  98. "eic-sync",
  99. };
  100. static const struct sprd_eic_variant_data sc9860_eic_dbnc_data = {
  101. .type = SPRD_EIC_DEBOUNCE,
  102. .num_eics = 8,
  103. };
  104. static const struct sprd_eic_variant_data sc9860_eic_latch_data = {
  105. .type = SPRD_EIC_LATCH,
  106. .num_eics = 8,
  107. };
  108. static const struct sprd_eic_variant_data sc9860_eic_async_data = {
  109. .type = SPRD_EIC_ASYNC,
  110. .num_eics = 8,
  111. };
  112. static const struct sprd_eic_variant_data sc9860_eic_sync_data = {
  113. .type = SPRD_EIC_SYNC,
  114. .num_eics = 8,
  115. };
  116. static inline void __iomem *sprd_eic_offset_base(struct sprd_eic *sprd_eic,
  117. unsigned int bank)
  118. {
  119. if (bank >= SPRD_EIC_MAX_BANK)
  120. return NULL;
  121. return sprd_eic->base[bank];
  122. }
  123. static void sprd_eic_update(struct gpio_chip *chip, unsigned int offset,
  124. u16 reg, unsigned int val)
  125. {
  126. struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
  127. void __iomem *base =
  128. sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR);
  129. unsigned long flags;
  130. u32 tmp;
  131. spin_lock_irqsave(&sprd_eic->lock, flags);
  132. tmp = readl_relaxed(base + reg);
  133. if (val)
  134. tmp |= BIT(SPRD_EIC_BIT(offset));
  135. else
  136. tmp &= ~BIT(SPRD_EIC_BIT(offset));
  137. writel_relaxed(tmp, base + reg);
  138. spin_unlock_irqrestore(&sprd_eic->lock, flags);
  139. }
  140. static int sprd_eic_read(struct gpio_chip *chip, unsigned int offset, u16 reg)
  141. {
  142. struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
  143. void __iomem *base =
  144. sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR);
  145. return !!(readl_relaxed(base + reg) & BIT(SPRD_EIC_BIT(offset)));
  146. }
  147. static int sprd_eic_request(struct gpio_chip *chip, unsigned int offset)
  148. {
  149. sprd_eic_update(chip, offset, SPRD_EIC_DBNC_DMSK, 1);
  150. return 0;
  151. }
  152. static void sprd_eic_free(struct gpio_chip *chip, unsigned int offset)
  153. {
  154. sprd_eic_update(chip, offset, SPRD_EIC_DBNC_DMSK, 0);
  155. }
  156. static int sprd_eic_get(struct gpio_chip *chip, unsigned int offset)
  157. {
  158. struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
  159. switch (sprd_eic->type) {
  160. case SPRD_EIC_DEBOUNCE:
  161. return sprd_eic_read(chip, offset, SPRD_EIC_DBNC_DATA);
  162. case SPRD_EIC_ASYNC:
  163. return sprd_eic_read(chip, offset, SPRD_EIC_ASYNC_DATA);
  164. case SPRD_EIC_SYNC:
  165. return sprd_eic_read(chip, offset, SPRD_EIC_SYNC_DATA);
  166. default:
  167. return -ENOTSUPP;
  168. }
  169. }
  170. static int sprd_eic_direction_input(struct gpio_chip *chip, unsigned int offset)
  171. {
  172. /* EICs are always input, nothing need to do here. */
  173. return 0;
  174. }
  175. static void sprd_eic_set(struct gpio_chip *chip, unsigned int offset, int value)
  176. {
  177. /* EICs are always input, nothing need to do here. */
  178. }
  179. static int sprd_eic_set_debounce(struct gpio_chip *chip, unsigned int offset,
  180. unsigned int debounce)
  181. {
  182. struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
  183. void __iomem *base =
  184. sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR);
  185. u32 reg = SPRD_EIC_DBNC_CTRL0 + SPRD_EIC_BIT(offset) * 0x4;
  186. u32 value = readl_relaxed(base + reg) & ~SPRD_EIC_DBNC_MASK;
  187. value |= (debounce / 1000) & SPRD_EIC_DBNC_MASK;
  188. writel_relaxed(value, base + reg);
  189. return 0;
  190. }
  191. static int sprd_eic_set_config(struct gpio_chip *chip, unsigned int offset,
  192. unsigned long config)
  193. {
  194. unsigned long param = pinconf_to_config_param(config);
  195. u32 arg = pinconf_to_config_argument(config);
  196. if (param == PIN_CONFIG_INPUT_DEBOUNCE)
  197. return sprd_eic_set_debounce(chip, offset, arg);
  198. return -ENOTSUPP;
  199. }
  200. static void sprd_eic_irq_mask(struct irq_data *data)
  201. {
  202. struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
  203. struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
  204. u32 offset = irqd_to_hwirq(data);
  205. switch (sprd_eic->type) {
  206. case SPRD_EIC_DEBOUNCE:
  207. sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IE, 0);
  208. sprd_eic_update(chip, offset, SPRD_EIC_DBNC_TRIG, 0);
  209. break;
  210. case SPRD_EIC_LATCH:
  211. sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTEN, 0);
  212. break;
  213. case SPRD_EIC_ASYNC:
  214. sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTIE, 0);
  215. break;
  216. case SPRD_EIC_SYNC:
  217. sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTIE, 0);
  218. break;
  219. default:
  220. dev_err(chip->parent, "Unsupported EIC type.\n");
  221. }
  222. }
  223. static void sprd_eic_irq_unmask(struct irq_data *data)
  224. {
  225. struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
  226. struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
  227. u32 offset = irqd_to_hwirq(data);
  228. switch (sprd_eic->type) {
  229. case SPRD_EIC_DEBOUNCE:
  230. sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IE, 1);
  231. sprd_eic_update(chip, offset, SPRD_EIC_DBNC_TRIG, 1);
  232. break;
  233. case SPRD_EIC_LATCH:
  234. sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTEN, 1);
  235. break;
  236. case SPRD_EIC_ASYNC:
  237. sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTIE, 1);
  238. break;
  239. case SPRD_EIC_SYNC:
  240. sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTIE, 1);
  241. break;
  242. default:
  243. dev_err(chip->parent, "Unsupported EIC type.\n");
  244. }
  245. }
  246. static void sprd_eic_irq_ack(struct irq_data *data)
  247. {
  248. struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
  249. struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
  250. u32 offset = irqd_to_hwirq(data);
  251. switch (sprd_eic->type) {
  252. case SPRD_EIC_DEBOUNCE:
  253. sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IC, 1);
  254. break;
  255. case SPRD_EIC_LATCH:
  256. sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTCLR, 1);
  257. break;
  258. case SPRD_EIC_ASYNC:
  259. sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1);
  260. break;
  261. case SPRD_EIC_SYNC:
  262. sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1);
  263. break;
  264. default:
  265. dev_err(chip->parent, "Unsupported EIC type.\n");
  266. }
  267. }
  268. static int sprd_eic_irq_set_type(struct irq_data *data, unsigned int flow_type)
  269. {
  270. struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
  271. struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
  272. u32 offset = irqd_to_hwirq(data);
  273. int state;
  274. switch (sprd_eic->type) {
  275. case SPRD_EIC_DEBOUNCE:
  276. switch (flow_type) {
  277. case IRQ_TYPE_LEVEL_HIGH:
  278. sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 1);
  279. break;
  280. case IRQ_TYPE_LEVEL_LOW:
  281. sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 0);
  282. break;
  283. case IRQ_TYPE_EDGE_RISING:
  284. case IRQ_TYPE_EDGE_FALLING:
  285. case IRQ_TYPE_EDGE_BOTH:
  286. state = sprd_eic_get(chip, offset);
  287. if (state)
  288. sprd_eic_update(chip, offset,
  289. SPRD_EIC_DBNC_IEV, 0);
  290. else
  291. sprd_eic_update(chip, offset,
  292. SPRD_EIC_DBNC_IEV, 1);
  293. break;
  294. default:
  295. return -ENOTSUPP;
  296. }
  297. irq_set_handler_locked(data, handle_level_irq);
  298. break;
  299. case SPRD_EIC_LATCH:
  300. switch (flow_type) {
  301. case IRQ_TYPE_LEVEL_HIGH:
  302. sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 0);
  303. break;
  304. case IRQ_TYPE_LEVEL_LOW:
  305. sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 1);
  306. break;
  307. case IRQ_TYPE_EDGE_RISING:
  308. case IRQ_TYPE_EDGE_FALLING:
  309. case IRQ_TYPE_EDGE_BOTH:
  310. state = sprd_eic_get(chip, offset);
  311. if (state)
  312. sprd_eic_update(chip, offset,
  313. SPRD_EIC_LATCH_INTPOL, 0);
  314. else
  315. sprd_eic_update(chip, offset,
  316. SPRD_EIC_LATCH_INTPOL, 1);
  317. break;
  318. default:
  319. return -ENOTSUPP;
  320. }
  321. irq_set_handler_locked(data, handle_level_irq);
  322. break;
  323. case SPRD_EIC_ASYNC:
  324. switch (flow_type) {
  325. case IRQ_TYPE_EDGE_RISING:
  326. sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
  327. sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0);
  328. sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 1);
  329. irq_set_handler_locked(data, handle_edge_irq);
  330. break;
  331. case IRQ_TYPE_EDGE_FALLING:
  332. sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
  333. sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0);
  334. sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 0);
  335. irq_set_handler_locked(data, handle_edge_irq);
  336. break;
  337. case IRQ_TYPE_EDGE_BOTH:
  338. sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0);
  339. sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 1);
  340. irq_set_handler_locked(data, handle_edge_irq);
  341. break;
  342. case IRQ_TYPE_LEVEL_HIGH:
  343. sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
  344. sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 1);
  345. sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 1);
  346. irq_set_handler_locked(data, handle_level_irq);
  347. break;
  348. case IRQ_TYPE_LEVEL_LOW:
  349. sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
  350. sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 1);
  351. sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 0);
  352. irq_set_handler_locked(data, handle_level_irq);
  353. break;
  354. default:
  355. return -ENOTSUPP;
  356. }
  357. break;
  358. case SPRD_EIC_SYNC:
  359. switch (flow_type) {
  360. case IRQ_TYPE_EDGE_RISING:
  361. sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
  362. sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0);
  363. sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 1);
  364. irq_set_handler_locked(data, handle_edge_irq);
  365. break;
  366. case IRQ_TYPE_EDGE_FALLING:
  367. sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
  368. sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0);
  369. sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 0);
  370. irq_set_handler_locked(data, handle_edge_irq);
  371. break;
  372. case IRQ_TYPE_EDGE_BOTH:
  373. sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0);
  374. sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 1);
  375. irq_set_handler_locked(data, handle_edge_irq);
  376. break;
  377. case IRQ_TYPE_LEVEL_HIGH:
  378. sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
  379. sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 1);
  380. sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 1);
  381. irq_set_handler_locked(data, handle_level_irq);
  382. break;
  383. case IRQ_TYPE_LEVEL_LOW:
  384. sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
  385. sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 1);
  386. sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 0);
  387. irq_set_handler_locked(data, handle_level_irq);
  388. break;
  389. default:
  390. return -ENOTSUPP;
  391. }
  392. break;
  393. default:
  394. dev_err(chip->parent, "Unsupported EIC type.\n");
  395. return -ENOTSUPP;
  396. }
  397. return 0;
  398. }
  399. static void sprd_eic_toggle_trigger(struct gpio_chip *chip, unsigned int irq,
  400. unsigned int offset)
  401. {
  402. struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
  403. struct irq_data *data = irq_get_irq_data(irq);
  404. u32 trigger = irqd_get_trigger_type(data);
  405. int state, post_state;
  406. /*
  407. * The debounce EIC and latch EIC can only support level trigger, so we
  408. * can toggle the level trigger to emulate the edge trigger.
  409. */
  410. if ((sprd_eic->type != SPRD_EIC_DEBOUNCE &&
  411. sprd_eic->type != SPRD_EIC_LATCH) ||
  412. !(trigger & IRQ_TYPE_EDGE_BOTH))
  413. return;
  414. sprd_eic_irq_mask(data);
  415. state = sprd_eic_get(chip, offset);
  416. retry:
  417. switch (sprd_eic->type) {
  418. case SPRD_EIC_DEBOUNCE:
  419. if (state)
  420. sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 0);
  421. else
  422. sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 1);
  423. break;
  424. case SPRD_EIC_LATCH:
  425. if (state)
  426. sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 0);
  427. else
  428. sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 1);
  429. break;
  430. default:
  431. sprd_eic_irq_unmask(data);
  432. return;
  433. }
  434. post_state = sprd_eic_get(chip, offset);
  435. if (state != post_state) {
  436. dev_warn(chip->parent, "EIC level was changed.\n");
  437. state = post_state;
  438. goto retry;
  439. }
  440. sprd_eic_irq_unmask(data);
  441. }
  442. static int sprd_eic_match_chip_by_type(struct gpio_chip *chip, void *data)
  443. {
  444. enum sprd_eic_type type = *(enum sprd_eic_type *)data;
  445. return !strcmp(chip->label, sprd_eic_label_name[type]);
  446. }
  447. static void sprd_eic_handle_one_type(struct gpio_chip *chip)
  448. {
  449. struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
  450. u32 bank, n, girq;
  451. for (bank = 0; bank * SPRD_EIC_PER_BANK_NR < chip->ngpio; bank++) {
  452. void __iomem *base = sprd_eic_offset_base(sprd_eic, bank);
  453. unsigned long reg;
  454. switch (sprd_eic->type) {
  455. case SPRD_EIC_DEBOUNCE:
  456. reg = readl_relaxed(base + SPRD_EIC_DBNC_MIS) &
  457. SPRD_EIC_DATA_MASK;
  458. break;
  459. case SPRD_EIC_LATCH:
  460. reg = readl_relaxed(base + SPRD_EIC_LATCH_INTMSK) &
  461. SPRD_EIC_DATA_MASK;
  462. break;
  463. case SPRD_EIC_ASYNC:
  464. reg = readl_relaxed(base + SPRD_EIC_ASYNC_INTMSK) &
  465. SPRD_EIC_DATA_MASK;
  466. break;
  467. case SPRD_EIC_SYNC:
  468. reg = readl_relaxed(base + SPRD_EIC_SYNC_INTMSK) &
  469. SPRD_EIC_DATA_MASK;
  470. break;
  471. default:
  472. dev_err(chip->parent, "Unsupported EIC type.\n");
  473. return;
  474. }
  475. for_each_set_bit(n, &reg, SPRD_EIC_PER_BANK_NR) {
  476. u32 offset = bank * SPRD_EIC_PER_BANK_NR + n;
  477. girq = irq_find_mapping(chip->irq.domain, offset);
  478. generic_handle_irq(girq);
  479. sprd_eic_toggle_trigger(chip, girq, offset);
  480. }
  481. }
  482. }
  483. static void sprd_eic_irq_handler(struct irq_desc *desc)
  484. {
  485. struct irq_chip *ic = irq_desc_get_chip(desc);
  486. struct gpio_chip *chip;
  487. enum sprd_eic_type type;
  488. chained_irq_enter(ic, desc);
  489. /*
  490. * Since the digital-chip EIC 4 sub-modules (debounce, latch, async
  491. * and sync) share one same interrupt line, we should iterate each
  492. * EIC module to check if there are EIC interrupts were triggered.
  493. */
  494. for (type = SPRD_EIC_DEBOUNCE; type < SPRD_EIC_MAX; type++) {
  495. chip = gpiochip_find(&type, sprd_eic_match_chip_by_type);
  496. if (!chip)
  497. continue;
  498. sprd_eic_handle_one_type(chip);
  499. }
  500. chained_irq_exit(ic, desc);
  501. }
  502. static int sprd_eic_probe(struct platform_device *pdev)
  503. {
  504. const struct sprd_eic_variant_data *pdata;
  505. struct gpio_irq_chip *irq;
  506. struct sprd_eic *sprd_eic;
  507. struct resource *res;
  508. int ret, i;
  509. pdata = of_device_get_match_data(&pdev->dev);
  510. if (!pdata) {
  511. dev_err(&pdev->dev, "No matching driver data found.\n");
  512. return -EINVAL;
  513. }
  514. sprd_eic = devm_kzalloc(&pdev->dev, sizeof(*sprd_eic), GFP_KERNEL);
  515. if (!sprd_eic)
  516. return -ENOMEM;
  517. spin_lock_init(&sprd_eic->lock);
  518. sprd_eic->type = pdata->type;
  519. sprd_eic->irq = platform_get_irq(pdev, 0);
  520. if (sprd_eic->irq < 0)
  521. return sprd_eic->irq;
  522. for (i = 0; i < SPRD_EIC_MAX_BANK; i++) {
  523. /*
  524. * We can have maximum 3 banks EICs, and each EIC has
  525. * its own base address. But some platform maybe only
  526. * have one bank EIC, thus base[1] and base[2] can be
  527. * optional.
  528. */
  529. res = platform_get_resource(pdev, IORESOURCE_MEM, i);
  530. if (!res)
  531. break;
  532. sprd_eic->base[i] = devm_ioremap_resource(&pdev->dev, res);
  533. if (IS_ERR(sprd_eic->base[i]))
  534. return PTR_ERR(sprd_eic->base[i]);
  535. }
  536. sprd_eic->chip.label = sprd_eic_label_name[sprd_eic->type];
  537. sprd_eic->chip.ngpio = pdata->num_eics;
  538. sprd_eic->chip.base = -1;
  539. sprd_eic->chip.parent = &pdev->dev;
  540. sprd_eic->chip.of_node = pdev->dev.of_node;
  541. sprd_eic->chip.direction_input = sprd_eic_direction_input;
  542. switch (sprd_eic->type) {
  543. case SPRD_EIC_DEBOUNCE:
  544. sprd_eic->chip.request = sprd_eic_request;
  545. sprd_eic->chip.free = sprd_eic_free;
  546. sprd_eic->chip.set_config = sprd_eic_set_config;
  547. sprd_eic->chip.set = sprd_eic_set;
  548. fallthrough;
  549. case SPRD_EIC_ASYNC:
  550. case SPRD_EIC_SYNC:
  551. sprd_eic->chip.get = sprd_eic_get;
  552. break;
  553. case SPRD_EIC_LATCH:
  554. default:
  555. break;
  556. }
  557. sprd_eic->intc.name = dev_name(&pdev->dev);
  558. sprd_eic->intc.irq_ack = sprd_eic_irq_ack;
  559. sprd_eic->intc.irq_mask = sprd_eic_irq_mask;
  560. sprd_eic->intc.irq_unmask = sprd_eic_irq_unmask;
  561. sprd_eic->intc.irq_set_type = sprd_eic_irq_set_type;
  562. sprd_eic->intc.flags = IRQCHIP_SKIP_SET_WAKE;
  563. irq = &sprd_eic->chip.irq;
  564. irq->chip = &sprd_eic->intc;
  565. irq->handler = handle_bad_irq;
  566. irq->default_type = IRQ_TYPE_NONE;
  567. irq->parent_handler = sprd_eic_irq_handler;
  568. irq->parent_handler_data = sprd_eic;
  569. irq->num_parents = 1;
  570. irq->parents = &sprd_eic->irq;
  571. ret = devm_gpiochip_add_data(&pdev->dev, &sprd_eic->chip, sprd_eic);
  572. if (ret < 0) {
  573. dev_err(&pdev->dev, "Could not register gpiochip %d.\n", ret);
  574. return ret;
  575. }
  576. platform_set_drvdata(pdev, sprd_eic);
  577. return 0;
  578. }
  579. static const struct of_device_id sprd_eic_of_match[] = {
  580. {
  581. .compatible = "sprd,sc9860-eic-debounce",
  582. .data = &sc9860_eic_dbnc_data,
  583. },
  584. {
  585. .compatible = "sprd,sc9860-eic-latch",
  586. .data = &sc9860_eic_latch_data,
  587. },
  588. {
  589. .compatible = "sprd,sc9860-eic-async",
  590. .data = &sc9860_eic_async_data,
  591. },
  592. {
  593. .compatible = "sprd,sc9860-eic-sync",
  594. .data = &sc9860_eic_sync_data,
  595. },
  596. {
  597. /* end of list */
  598. }
  599. };
  600. MODULE_DEVICE_TABLE(of, sprd_eic_of_match);
  601. static struct platform_driver sprd_eic_driver = {
  602. .probe = sprd_eic_probe,
  603. .driver = {
  604. .name = "sprd-eic",
  605. .of_match_table = sprd_eic_of_match,
  606. },
  607. };
  608. module_platform_driver(sprd_eic_driver);
  609. MODULE_DESCRIPTION("Spreadtrum EIC driver");
  610. MODULE_LICENSE("GPL v2");