gpio-dln2.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Driver for the Diolan DLN-2 USB-GPIO adapter
  4. *
  5. * Copyright (c) 2014 Intel Corporation
  6. */
  7. #include <linux/kernel.h>
  8. #include <linux/module.h>
  9. #include <linux/slab.h>
  10. #include <linux/types.h>
  11. #include <linux/irqdomain.h>
  12. #include <linux/irq.h>
  13. #include <linux/irqchip/chained_irq.h>
  14. #include <linux/gpio/driver.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/mfd/dln2.h>
  17. #define DLN2_GPIO_ID 0x01
  18. #define DLN2_GPIO_GET_PIN_COUNT DLN2_CMD(0x01, DLN2_GPIO_ID)
  19. #define DLN2_GPIO_SET_DEBOUNCE DLN2_CMD(0x04, DLN2_GPIO_ID)
  20. #define DLN2_GPIO_GET_DEBOUNCE DLN2_CMD(0x05, DLN2_GPIO_ID)
  21. #define DLN2_GPIO_PORT_GET_VAL DLN2_CMD(0x06, DLN2_GPIO_ID)
  22. #define DLN2_GPIO_PIN_GET_VAL DLN2_CMD(0x0B, DLN2_GPIO_ID)
  23. #define DLN2_GPIO_PIN_SET_OUT_VAL DLN2_CMD(0x0C, DLN2_GPIO_ID)
  24. #define DLN2_GPIO_PIN_GET_OUT_VAL DLN2_CMD(0x0D, DLN2_GPIO_ID)
  25. #define DLN2_GPIO_CONDITION_MET_EV DLN2_CMD(0x0F, DLN2_GPIO_ID)
  26. #define DLN2_GPIO_PIN_ENABLE DLN2_CMD(0x10, DLN2_GPIO_ID)
  27. #define DLN2_GPIO_PIN_DISABLE DLN2_CMD(0x11, DLN2_GPIO_ID)
  28. #define DLN2_GPIO_PIN_SET_DIRECTION DLN2_CMD(0x13, DLN2_GPIO_ID)
  29. #define DLN2_GPIO_PIN_GET_DIRECTION DLN2_CMD(0x14, DLN2_GPIO_ID)
  30. #define DLN2_GPIO_PIN_SET_EVENT_CFG DLN2_CMD(0x1E, DLN2_GPIO_ID)
  31. #define DLN2_GPIO_PIN_GET_EVENT_CFG DLN2_CMD(0x1F, DLN2_GPIO_ID)
  32. #define DLN2_GPIO_EVENT_NONE 0
  33. #define DLN2_GPIO_EVENT_CHANGE 1
  34. #define DLN2_GPIO_EVENT_LVL_HIGH 2
  35. #define DLN2_GPIO_EVENT_LVL_LOW 3
  36. #define DLN2_GPIO_EVENT_CHANGE_RISING 0x11
  37. #define DLN2_GPIO_EVENT_CHANGE_FALLING 0x21
  38. #define DLN2_GPIO_EVENT_MASK 0x0F
  39. #define DLN2_GPIO_MAX_PINS 32
  40. struct dln2_gpio {
  41. struct platform_device *pdev;
  42. struct gpio_chip gpio;
  43. struct irq_chip irqchip;
  44. /*
  45. * Cache pin direction to save us one transfer, since the hardware has
  46. * separate commands to read the in and out values.
  47. */
  48. DECLARE_BITMAP(output_enabled, DLN2_GPIO_MAX_PINS);
  49. /* active IRQs - not synced to hardware */
  50. DECLARE_BITMAP(unmasked_irqs, DLN2_GPIO_MAX_PINS);
  51. /* active IRQS - synced to hardware */
  52. DECLARE_BITMAP(enabled_irqs, DLN2_GPIO_MAX_PINS);
  53. int irq_type[DLN2_GPIO_MAX_PINS];
  54. struct mutex irq_lock;
  55. };
  56. struct dln2_gpio_pin {
  57. __le16 pin;
  58. };
  59. struct dln2_gpio_pin_val {
  60. __le16 pin __packed;
  61. u8 value;
  62. };
  63. static int dln2_gpio_get_pin_count(struct platform_device *pdev)
  64. {
  65. int ret;
  66. __le16 count;
  67. int len = sizeof(count);
  68. ret = dln2_transfer_rx(pdev, DLN2_GPIO_GET_PIN_COUNT, &count, &len);
  69. if (ret < 0)
  70. return ret;
  71. if (len < sizeof(count))
  72. return -EPROTO;
  73. return le16_to_cpu(count);
  74. }
  75. static int dln2_gpio_pin_cmd(struct dln2_gpio *dln2, int cmd, unsigned pin)
  76. {
  77. struct dln2_gpio_pin req = {
  78. .pin = cpu_to_le16(pin),
  79. };
  80. return dln2_transfer_tx(dln2->pdev, cmd, &req, sizeof(req));
  81. }
  82. static int dln2_gpio_pin_val(struct dln2_gpio *dln2, int cmd, unsigned int pin)
  83. {
  84. int ret;
  85. struct dln2_gpio_pin req = {
  86. .pin = cpu_to_le16(pin),
  87. };
  88. struct dln2_gpio_pin_val rsp;
  89. int len = sizeof(rsp);
  90. ret = dln2_transfer(dln2->pdev, cmd, &req, sizeof(req), &rsp, &len);
  91. if (ret < 0)
  92. return ret;
  93. if (len < sizeof(rsp) || req.pin != rsp.pin)
  94. return -EPROTO;
  95. return rsp.value;
  96. }
  97. static int dln2_gpio_pin_get_in_val(struct dln2_gpio *dln2, unsigned int pin)
  98. {
  99. int ret;
  100. ret = dln2_gpio_pin_val(dln2, DLN2_GPIO_PIN_GET_VAL, pin);
  101. if (ret < 0)
  102. return ret;
  103. return !!ret;
  104. }
  105. static int dln2_gpio_pin_get_out_val(struct dln2_gpio *dln2, unsigned int pin)
  106. {
  107. int ret;
  108. ret = dln2_gpio_pin_val(dln2, DLN2_GPIO_PIN_GET_OUT_VAL, pin);
  109. if (ret < 0)
  110. return ret;
  111. return !!ret;
  112. }
  113. static int dln2_gpio_pin_set_out_val(struct dln2_gpio *dln2,
  114. unsigned int pin, int value)
  115. {
  116. struct dln2_gpio_pin_val req = {
  117. .pin = cpu_to_le16(pin),
  118. .value = value,
  119. };
  120. return dln2_transfer_tx(dln2->pdev, DLN2_GPIO_PIN_SET_OUT_VAL, &req,
  121. sizeof(req));
  122. }
  123. #define DLN2_GPIO_DIRECTION_IN 0
  124. #define DLN2_GPIO_DIRECTION_OUT 1
  125. static int dln2_gpio_request(struct gpio_chip *chip, unsigned offset)
  126. {
  127. struct dln2_gpio *dln2 = gpiochip_get_data(chip);
  128. struct dln2_gpio_pin req = {
  129. .pin = cpu_to_le16(offset),
  130. };
  131. struct dln2_gpio_pin_val rsp;
  132. int len = sizeof(rsp);
  133. int ret;
  134. ret = dln2_gpio_pin_cmd(dln2, DLN2_GPIO_PIN_ENABLE, offset);
  135. if (ret < 0)
  136. return ret;
  137. /* cache the pin direction */
  138. ret = dln2_transfer(dln2->pdev, DLN2_GPIO_PIN_GET_DIRECTION,
  139. &req, sizeof(req), &rsp, &len);
  140. if (ret < 0)
  141. return ret;
  142. if (len < sizeof(rsp) || req.pin != rsp.pin) {
  143. ret = -EPROTO;
  144. goto out_disable;
  145. }
  146. switch (rsp.value) {
  147. case DLN2_GPIO_DIRECTION_IN:
  148. clear_bit(offset, dln2->output_enabled);
  149. return 0;
  150. case DLN2_GPIO_DIRECTION_OUT:
  151. set_bit(offset, dln2->output_enabled);
  152. return 0;
  153. default:
  154. ret = -EPROTO;
  155. goto out_disable;
  156. }
  157. out_disable:
  158. dln2_gpio_pin_cmd(dln2, DLN2_GPIO_PIN_DISABLE, offset);
  159. return ret;
  160. }
  161. static void dln2_gpio_free(struct gpio_chip *chip, unsigned offset)
  162. {
  163. struct dln2_gpio *dln2 = gpiochip_get_data(chip);
  164. dln2_gpio_pin_cmd(dln2, DLN2_GPIO_PIN_DISABLE, offset);
  165. }
  166. static int dln2_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
  167. {
  168. struct dln2_gpio *dln2 = gpiochip_get_data(chip);
  169. if (test_bit(offset, dln2->output_enabled))
  170. return GPIO_LINE_DIRECTION_OUT;
  171. return GPIO_LINE_DIRECTION_IN;
  172. }
  173. static int dln2_gpio_get(struct gpio_chip *chip, unsigned int offset)
  174. {
  175. struct dln2_gpio *dln2 = gpiochip_get_data(chip);
  176. int dir;
  177. dir = dln2_gpio_get_direction(chip, offset);
  178. if (dir < 0)
  179. return dir;
  180. if (dir == GPIO_LINE_DIRECTION_IN)
  181. return dln2_gpio_pin_get_in_val(dln2, offset);
  182. return dln2_gpio_pin_get_out_val(dln2, offset);
  183. }
  184. static void dln2_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
  185. {
  186. struct dln2_gpio *dln2 = gpiochip_get_data(chip);
  187. dln2_gpio_pin_set_out_val(dln2, offset, value);
  188. }
  189. static int dln2_gpio_set_direction(struct gpio_chip *chip, unsigned offset,
  190. unsigned dir)
  191. {
  192. struct dln2_gpio *dln2 = gpiochip_get_data(chip);
  193. struct dln2_gpio_pin_val req = {
  194. .pin = cpu_to_le16(offset),
  195. .value = dir,
  196. };
  197. int ret;
  198. ret = dln2_transfer_tx(dln2->pdev, DLN2_GPIO_PIN_SET_DIRECTION,
  199. &req, sizeof(req));
  200. if (ret < 0)
  201. return ret;
  202. if (dir == DLN2_GPIO_DIRECTION_OUT)
  203. set_bit(offset, dln2->output_enabled);
  204. else
  205. clear_bit(offset, dln2->output_enabled);
  206. return ret;
  207. }
  208. static int dln2_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
  209. {
  210. return dln2_gpio_set_direction(chip, offset, DLN2_GPIO_DIRECTION_IN);
  211. }
  212. static int dln2_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
  213. int value)
  214. {
  215. struct dln2_gpio *dln2 = gpiochip_get_data(chip);
  216. int ret;
  217. ret = dln2_gpio_pin_set_out_val(dln2, offset, value);
  218. if (ret < 0)
  219. return ret;
  220. return dln2_gpio_set_direction(chip, offset, DLN2_GPIO_DIRECTION_OUT);
  221. }
  222. static int dln2_gpio_set_config(struct gpio_chip *chip, unsigned offset,
  223. unsigned long config)
  224. {
  225. struct dln2_gpio *dln2 = gpiochip_get_data(chip);
  226. __le32 duration;
  227. if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
  228. return -ENOTSUPP;
  229. duration = cpu_to_le32(pinconf_to_config_argument(config));
  230. return dln2_transfer_tx(dln2->pdev, DLN2_GPIO_SET_DEBOUNCE,
  231. &duration, sizeof(duration));
  232. }
  233. static int dln2_gpio_set_event_cfg(struct dln2_gpio *dln2, unsigned pin,
  234. unsigned type, unsigned period)
  235. {
  236. struct {
  237. __le16 pin;
  238. u8 type;
  239. __le16 period;
  240. } __packed req = {
  241. .pin = cpu_to_le16(pin),
  242. .type = type,
  243. .period = cpu_to_le16(period),
  244. };
  245. return dln2_transfer_tx(dln2->pdev, DLN2_GPIO_PIN_SET_EVENT_CFG,
  246. &req, sizeof(req));
  247. }
  248. static void dln2_irq_unmask(struct irq_data *irqd)
  249. {
  250. struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
  251. struct dln2_gpio *dln2 = gpiochip_get_data(gc);
  252. int pin = irqd_to_hwirq(irqd);
  253. set_bit(pin, dln2->unmasked_irqs);
  254. }
  255. static void dln2_irq_mask(struct irq_data *irqd)
  256. {
  257. struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
  258. struct dln2_gpio *dln2 = gpiochip_get_data(gc);
  259. int pin = irqd_to_hwirq(irqd);
  260. clear_bit(pin, dln2->unmasked_irqs);
  261. }
  262. static int dln2_irq_set_type(struct irq_data *irqd, unsigned type)
  263. {
  264. struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
  265. struct dln2_gpio *dln2 = gpiochip_get_data(gc);
  266. int pin = irqd_to_hwirq(irqd);
  267. switch (type) {
  268. case IRQ_TYPE_LEVEL_HIGH:
  269. dln2->irq_type[pin] = DLN2_GPIO_EVENT_LVL_HIGH;
  270. break;
  271. case IRQ_TYPE_LEVEL_LOW:
  272. dln2->irq_type[pin] = DLN2_GPIO_EVENT_LVL_LOW;
  273. break;
  274. case IRQ_TYPE_EDGE_BOTH:
  275. dln2->irq_type[pin] = DLN2_GPIO_EVENT_CHANGE;
  276. break;
  277. case IRQ_TYPE_EDGE_RISING:
  278. dln2->irq_type[pin] = DLN2_GPIO_EVENT_CHANGE_RISING;
  279. break;
  280. case IRQ_TYPE_EDGE_FALLING:
  281. dln2->irq_type[pin] = DLN2_GPIO_EVENT_CHANGE_FALLING;
  282. break;
  283. default:
  284. return -EINVAL;
  285. }
  286. return 0;
  287. }
  288. static void dln2_irq_bus_lock(struct irq_data *irqd)
  289. {
  290. struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
  291. struct dln2_gpio *dln2 = gpiochip_get_data(gc);
  292. mutex_lock(&dln2->irq_lock);
  293. }
  294. static void dln2_irq_bus_unlock(struct irq_data *irqd)
  295. {
  296. struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
  297. struct dln2_gpio *dln2 = gpiochip_get_data(gc);
  298. int pin = irqd_to_hwirq(irqd);
  299. int enabled, unmasked;
  300. unsigned type;
  301. int ret;
  302. enabled = test_bit(pin, dln2->enabled_irqs);
  303. unmasked = test_bit(pin, dln2->unmasked_irqs);
  304. if (enabled != unmasked) {
  305. if (unmasked) {
  306. type = dln2->irq_type[pin] & DLN2_GPIO_EVENT_MASK;
  307. set_bit(pin, dln2->enabled_irqs);
  308. } else {
  309. type = DLN2_GPIO_EVENT_NONE;
  310. clear_bit(pin, dln2->enabled_irqs);
  311. }
  312. ret = dln2_gpio_set_event_cfg(dln2, pin, type, 0);
  313. if (ret)
  314. dev_err(dln2->gpio.parent, "failed to set event\n");
  315. }
  316. mutex_unlock(&dln2->irq_lock);
  317. }
  318. static void dln2_gpio_event(struct platform_device *pdev, u16 echo,
  319. const void *data, int len)
  320. {
  321. int pin, irq;
  322. const struct {
  323. __le16 count;
  324. __u8 type;
  325. __le16 pin;
  326. __u8 value;
  327. } __packed *event = data;
  328. struct dln2_gpio *dln2 = platform_get_drvdata(pdev);
  329. if (len < sizeof(*event)) {
  330. dev_err(dln2->gpio.parent, "short event message\n");
  331. return;
  332. }
  333. pin = le16_to_cpu(event->pin);
  334. if (pin >= dln2->gpio.ngpio) {
  335. dev_err(dln2->gpio.parent, "out of bounds pin %d\n", pin);
  336. return;
  337. }
  338. irq = irq_find_mapping(dln2->gpio.irq.domain, pin);
  339. if (!irq) {
  340. dev_err(dln2->gpio.parent, "pin %d not mapped to IRQ\n", pin);
  341. return;
  342. }
  343. switch (dln2->irq_type[pin]) {
  344. case DLN2_GPIO_EVENT_CHANGE_RISING:
  345. if (event->value)
  346. generic_handle_irq(irq);
  347. break;
  348. case DLN2_GPIO_EVENT_CHANGE_FALLING:
  349. if (!event->value)
  350. generic_handle_irq(irq);
  351. break;
  352. default:
  353. generic_handle_irq(irq);
  354. }
  355. }
  356. static int dln2_gpio_probe(struct platform_device *pdev)
  357. {
  358. struct dln2_gpio *dln2;
  359. struct device *dev = &pdev->dev;
  360. struct gpio_irq_chip *girq;
  361. int pins;
  362. int ret;
  363. pins = dln2_gpio_get_pin_count(pdev);
  364. if (pins < 0) {
  365. dev_err(dev, "failed to get pin count: %d\n", pins);
  366. return pins;
  367. }
  368. if (pins > DLN2_GPIO_MAX_PINS) {
  369. pins = DLN2_GPIO_MAX_PINS;
  370. dev_warn(dev, "clamping pins to %d\n", DLN2_GPIO_MAX_PINS);
  371. }
  372. dln2 = devm_kzalloc(&pdev->dev, sizeof(*dln2), GFP_KERNEL);
  373. if (!dln2)
  374. return -ENOMEM;
  375. mutex_init(&dln2->irq_lock);
  376. dln2->pdev = pdev;
  377. dln2->gpio.label = "dln2";
  378. dln2->gpio.parent = dev;
  379. dln2->gpio.owner = THIS_MODULE;
  380. dln2->gpio.base = -1;
  381. dln2->gpio.ngpio = pins;
  382. dln2->gpio.can_sleep = true;
  383. dln2->gpio.set = dln2_gpio_set;
  384. dln2->gpio.get = dln2_gpio_get;
  385. dln2->gpio.request = dln2_gpio_request;
  386. dln2->gpio.free = dln2_gpio_free;
  387. dln2->gpio.get_direction = dln2_gpio_get_direction;
  388. dln2->gpio.direction_input = dln2_gpio_direction_input;
  389. dln2->gpio.direction_output = dln2_gpio_direction_output;
  390. dln2->gpio.set_config = dln2_gpio_set_config;
  391. dln2->irqchip.name = "dln2-irq",
  392. dln2->irqchip.irq_mask = dln2_irq_mask,
  393. dln2->irqchip.irq_unmask = dln2_irq_unmask,
  394. dln2->irqchip.irq_set_type = dln2_irq_set_type,
  395. dln2->irqchip.irq_bus_lock = dln2_irq_bus_lock,
  396. dln2->irqchip.irq_bus_sync_unlock = dln2_irq_bus_unlock,
  397. girq = &dln2->gpio.irq;
  398. girq->chip = &dln2->irqchip;
  399. /* The event comes from the outside so no parent handler */
  400. girq->parent_handler = NULL;
  401. girq->num_parents = 0;
  402. girq->parents = NULL;
  403. girq->default_type = IRQ_TYPE_NONE;
  404. girq->handler = handle_simple_irq;
  405. platform_set_drvdata(pdev, dln2);
  406. ret = devm_gpiochip_add_data(dev, &dln2->gpio, dln2);
  407. if (ret < 0) {
  408. dev_err(dev, "failed to add gpio chip: %d\n", ret);
  409. return ret;
  410. }
  411. ret = dln2_register_event_cb(pdev, DLN2_GPIO_CONDITION_MET_EV,
  412. dln2_gpio_event);
  413. if (ret) {
  414. dev_err(dev, "failed to register event cb: %d\n", ret);
  415. return ret;
  416. }
  417. return 0;
  418. }
  419. static int dln2_gpio_remove(struct platform_device *pdev)
  420. {
  421. dln2_unregister_event_cb(pdev, DLN2_GPIO_CONDITION_MET_EV);
  422. return 0;
  423. }
  424. static struct platform_driver dln2_gpio_driver = {
  425. .driver.name = "dln2-gpio",
  426. .probe = dln2_gpio_probe,
  427. .remove = dln2_gpio_remove,
  428. };
  429. module_platform_driver(dln2_gpio_driver);
  430. MODULE_AUTHOR("Daniel Baluta <daniel.baluta@intel.com");
  431. MODULE_DESCRIPTION("Driver for the Diolan DLN2 GPIO interface");
  432. MODULE_LICENSE("GPL v2");
  433. MODULE_ALIAS("platform:dln2-gpio");