gpio-davinci.c 17 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651
  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * TI DaVinci GPIO Support
  4. *
  5. * Copyright (c) 2006-2007 David Brownell
  6. * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
  7. */
  8. #include <linux/gpio/driver.h>
  9. #include <linux/errno.h>
  10. #include <linux/kernel.h>
  11. #include <linux/clk.h>
  12. #include <linux/err.h>
  13. #include <linux/io.h>
  14. #include <linux/irq.h>
  15. #include <linux/irqdomain.h>
  16. #include <linux/module.h>
  17. #include <linux/of.h>
  18. #include <linux/of_device.h>
  19. #include <linux/pinctrl/consumer.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/platform_data/gpio-davinci.h>
  22. #include <linux/irqchip/chained_irq.h>
  23. #include <linux/spinlock.h>
  24. #include <asm-generic/gpio.h>
  25. #define MAX_REGS_BANKS 5
  26. #define MAX_INT_PER_BANK 32
  27. struct davinci_gpio_regs {
  28. u32 dir;
  29. u32 out_data;
  30. u32 set_data;
  31. u32 clr_data;
  32. u32 in_data;
  33. u32 set_rising;
  34. u32 clr_rising;
  35. u32 set_falling;
  36. u32 clr_falling;
  37. u32 intstat;
  38. };
  39. typedef struct irq_chip *(*gpio_get_irq_chip_cb_t)(unsigned int irq);
  40. #define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */
  41. static void __iomem *gpio_base;
  42. static unsigned int offset_array[5] = {0x10, 0x38, 0x60, 0x88, 0xb0};
  43. struct davinci_gpio_irq_data {
  44. void __iomem *regs;
  45. struct davinci_gpio_controller *chip;
  46. int bank_num;
  47. };
  48. struct davinci_gpio_controller {
  49. struct gpio_chip chip;
  50. struct irq_domain *irq_domain;
  51. /* Serialize access to GPIO registers */
  52. spinlock_t lock;
  53. void __iomem *regs[MAX_REGS_BANKS];
  54. int gpio_unbanked;
  55. int irqs[MAX_INT_PER_BANK];
  56. };
  57. static inline u32 __gpio_mask(unsigned gpio)
  58. {
  59. return 1 << (gpio % 32);
  60. }
  61. static inline struct davinci_gpio_regs __iomem *irq2regs(struct irq_data *d)
  62. {
  63. struct davinci_gpio_regs __iomem *g;
  64. g = (__force struct davinci_gpio_regs __iomem *)irq_data_get_irq_chip_data(d);
  65. return g;
  66. }
  67. static int davinci_gpio_irq_setup(struct platform_device *pdev);
  68. /*--------------------------------------------------------------------------*/
  69. /* board setup code *MUST* setup pinmux and enable the GPIO clock. */
  70. static inline int __davinci_direction(struct gpio_chip *chip,
  71. unsigned offset, bool out, int value)
  72. {
  73. struct davinci_gpio_controller *d = gpiochip_get_data(chip);
  74. struct davinci_gpio_regs __iomem *g;
  75. unsigned long flags;
  76. u32 temp;
  77. int bank = offset / 32;
  78. u32 mask = __gpio_mask(offset);
  79. g = d->regs[bank];
  80. spin_lock_irqsave(&d->lock, flags);
  81. temp = readl_relaxed(&g->dir);
  82. if (out) {
  83. temp &= ~mask;
  84. writel_relaxed(mask, value ? &g->set_data : &g->clr_data);
  85. } else {
  86. temp |= mask;
  87. }
  88. writel_relaxed(temp, &g->dir);
  89. spin_unlock_irqrestore(&d->lock, flags);
  90. return 0;
  91. }
  92. static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
  93. {
  94. return __davinci_direction(chip, offset, false, 0);
  95. }
  96. static int
  97. davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
  98. {
  99. return __davinci_direction(chip, offset, true, value);
  100. }
  101. /*
  102. * Read the pin's value (works even if it's set up as output);
  103. * returns zero/nonzero.
  104. *
  105. * Note that changes are synched to the GPIO clock, so reading values back
  106. * right after you've set them may give old values.
  107. */
  108. static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
  109. {
  110. struct davinci_gpio_controller *d = gpiochip_get_data(chip);
  111. struct davinci_gpio_regs __iomem *g;
  112. int bank = offset / 32;
  113. g = d->regs[bank];
  114. return !!(__gpio_mask(offset) & readl_relaxed(&g->in_data));
  115. }
  116. /*
  117. * Assuming the pin is muxed as a gpio output, set its output value.
  118. */
  119. static void
  120. davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
  121. {
  122. struct davinci_gpio_controller *d = gpiochip_get_data(chip);
  123. struct davinci_gpio_regs __iomem *g;
  124. int bank = offset / 32;
  125. g = d->regs[bank];
  126. writel_relaxed(__gpio_mask(offset),
  127. value ? &g->set_data : &g->clr_data);
  128. }
  129. static struct davinci_gpio_platform_data *
  130. davinci_gpio_get_pdata(struct platform_device *pdev)
  131. {
  132. struct device_node *dn = pdev->dev.of_node;
  133. struct davinci_gpio_platform_data *pdata;
  134. int ret;
  135. u32 val;
  136. if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node)
  137. return dev_get_platdata(&pdev->dev);
  138. pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
  139. if (!pdata)
  140. return NULL;
  141. ret = of_property_read_u32(dn, "ti,ngpio", &val);
  142. if (ret)
  143. goto of_err;
  144. pdata->ngpio = val;
  145. ret = of_property_read_u32(dn, "ti,davinci-gpio-unbanked", &val);
  146. if (ret)
  147. goto of_err;
  148. pdata->gpio_unbanked = val;
  149. return pdata;
  150. of_err:
  151. dev_err(&pdev->dev, "Populating pdata from DT failed: err %d\n", ret);
  152. return NULL;
  153. }
  154. static int davinci_gpio_probe(struct platform_device *pdev)
  155. {
  156. int bank, i, ret = 0;
  157. unsigned int ngpio, nbank, nirq;
  158. struct davinci_gpio_controller *chips;
  159. struct davinci_gpio_platform_data *pdata;
  160. struct device *dev = &pdev->dev;
  161. pdata = davinci_gpio_get_pdata(pdev);
  162. if (!pdata) {
  163. dev_err(dev, "No platform data found\n");
  164. return -EINVAL;
  165. }
  166. dev->platform_data = pdata;
  167. /*
  168. * The gpio banks conceptually expose a segmented bitmap,
  169. * and "ngpio" is one more than the largest zero-based
  170. * bit index that's valid.
  171. */
  172. ngpio = pdata->ngpio;
  173. if (ngpio == 0) {
  174. dev_err(dev, "How many GPIOs?\n");
  175. return -EINVAL;
  176. }
  177. if (WARN_ON(ARCH_NR_GPIOS < ngpio))
  178. ngpio = ARCH_NR_GPIOS;
  179. /*
  180. * If there are unbanked interrupts then the number of
  181. * interrupts is equal to number of gpios else all are banked so
  182. * number of interrupts is equal to number of banks(each with 16 gpios)
  183. */
  184. if (pdata->gpio_unbanked)
  185. nirq = pdata->gpio_unbanked;
  186. else
  187. nirq = DIV_ROUND_UP(ngpio, 16);
  188. chips = devm_kzalloc(dev, sizeof(*chips), GFP_KERNEL);
  189. if (!chips)
  190. return -ENOMEM;
  191. gpio_base = devm_platform_ioremap_resource(pdev, 0);
  192. if (IS_ERR(gpio_base))
  193. return PTR_ERR(gpio_base);
  194. for (i = 0; i < nirq; i++) {
  195. chips->irqs[i] = platform_get_irq(pdev, i);
  196. if (chips->irqs[i] < 0)
  197. return dev_err_probe(dev, chips->irqs[i], "IRQ not populated\n");
  198. }
  199. chips->chip.label = dev_name(dev);
  200. chips->chip.direction_input = davinci_direction_in;
  201. chips->chip.get = davinci_gpio_get;
  202. chips->chip.direction_output = davinci_direction_out;
  203. chips->chip.set = davinci_gpio_set;
  204. chips->chip.ngpio = ngpio;
  205. chips->chip.base = pdata->no_auto_base ? pdata->base : -1;
  206. #ifdef CONFIG_OF_GPIO
  207. chips->chip.of_gpio_n_cells = 2;
  208. chips->chip.parent = dev;
  209. chips->chip.of_node = dev->of_node;
  210. chips->chip.request = gpiochip_generic_request;
  211. chips->chip.free = gpiochip_generic_free;
  212. #endif
  213. spin_lock_init(&chips->lock);
  214. nbank = DIV_ROUND_UP(ngpio, 32);
  215. for (bank = 0; bank < nbank; bank++)
  216. chips->regs[bank] = gpio_base + offset_array[bank];
  217. ret = devm_gpiochip_add_data(dev, &chips->chip, chips);
  218. if (ret)
  219. return ret;
  220. platform_set_drvdata(pdev, chips);
  221. ret = davinci_gpio_irq_setup(pdev);
  222. if (ret)
  223. return ret;
  224. return 0;
  225. }
  226. /*--------------------------------------------------------------------------*/
  227. /*
  228. * We expect irqs will normally be set up as input pins, but they can also be
  229. * used as output pins ... which is convenient for testing.
  230. *
  231. * NOTE: The first few GPIOs also have direct INTC hookups in addition
  232. * to their GPIOBNK0 irq, with a bit less overhead.
  233. *
  234. * All those INTC hookups (direct, plus several IRQ banks) can also
  235. * serve as EDMA event triggers.
  236. */
  237. static void gpio_irq_disable(struct irq_data *d)
  238. {
  239. struct davinci_gpio_regs __iomem *g = irq2regs(d);
  240. uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d);
  241. writel_relaxed(mask, &g->clr_falling);
  242. writel_relaxed(mask, &g->clr_rising);
  243. }
  244. static void gpio_irq_enable(struct irq_data *d)
  245. {
  246. struct davinci_gpio_regs __iomem *g = irq2regs(d);
  247. uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d);
  248. unsigned status = irqd_get_trigger_type(d);
  249. status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
  250. if (!status)
  251. status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
  252. if (status & IRQ_TYPE_EDGE_FALLING)
  253. writel_relaxed(mask, &g->set_falling);
  254. if (status & IRQ_TYPE_EDGE_RISING)
  255. writel_relaxed(mask, &g->set_rising);
  256. }
  257. static int gpio_irq_type(struct irq_data *d, unsigned trigger)
  258. {
  259. if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
  260. return -EINVAL;
  261. return 0;
  262. }
  263. static struct irq_chip gpio_irqchip = {
  264. .name = "GPIO",
  265. .irq_enable = gpio_irq_enable,
  266. .irq_disable = gpio_irq_disable,
  267. .irq_set_type = gpio_irq_type,
  268. .flags = IRQCHIP_SET_TYPE_MASKED,
  269. };
  270. static void gpio_irq_handler(struct irq_desc *desc)
  271. {
  272. struct davinci_gpio_regs __iomem *g;
  273. u32 mask = 0xffff;
  274. int bank_num;
  275. struct davinci_gpio_controller *d;
  276. struct davinci_gpio_irq_data *irqdata;
  277. irqdata = (struct davinci_gpio_irq_data *)irq_desc_get_handler_data(desc);
  278. bank_num = irqdata->bank_num;
  279. g = irqdata->regs;
  280. d = irqdata->chip;
  281. /* we only care about one bank */
  282. if ((bank_num % 2) == 1)
  283. mask <<= 16;
  284. /* temporarily mask (level sensitive) parent IRQ */
  285. chained_irq_enter(irq_desc_get_chip(desc), desc);
  286. while (1) {
  287. u32 status;
  288. int bit;
  289. irq_hw_number_t hw_irq;
  290. /* ack any irqs */
  291. status = readl_relaxed(&g->intstat) & mask;
  292. if (!status)
  293. break;
  294. writel_relaxed(status, &g->intstat);
  295. /* now demux them to the right lowlevel handler */
  296. while (status) {
  297. bit = __ffs(status);
  298. status &= ~BIT(bit);
  299. /* Max number of gpios per controller is 144 so
  300. * hw_irq will be in [0..143]
  301. */
  302. hw_irq = (bank_num / 2) * 32 + bit;
  303. generic_handle_irq(
  304. irq_find_mapping(d->irq_domain, hw_irq));
  305. }
  306. }
  307. chained_irq_exit(irq_desc_get_chip(desc), desc);
  308. /* now it may re-trigger */
  309. }
  310. static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
  311. {
  312. struct davinci_gpio_controller *d = gpiochip_get_data(chip);
  313. if (d->irq_domain)
  314. return irq_create_mapping(d->irq_domain, offset);
  315. else
  316. return -ENXIO;
  317. }
  318. static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
  319. {
  320. struct davinci_gpio_controller *d = gpiochip_get_data(chip);
  321. /*
  322. * NOTE: we assume for now that only irqs in the first gpio_chip
  323. * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
  324. */
  325. if (offset < d->gpio_unbanked)
  326. return d->irqs[offset];
  327. else
  328. return -ENODEV;
  329. }
  330. static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger)
  331. {
  332. struct davinci_gpio_controller *d;
  333. struct davinci_gpio_regs __iomem *g;
  334. u32 mask, i;
  335. d = (struct davinci_gpio_controller *)irq_data_get_irq_handler_data(data);
  336. g = (struct davinci_gpio_regs __iomem *)d->regs[0];
  337. for (i = 0; i < MAX_INT_PER_BANK; i++)
  338. if (data->irq == d->irqs[i])
  339. break;
  340. if (i == MAX_INT_PER_BANK)
  341. return -EINVAL;
  342. mask = __gpio_mask(i);
  343. if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
  344. return -EINVAL;
  345. writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
  346. ? &g->set_falling : &g->clr_falling);
  347. writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING)
  348. ? &g->set_rising : &g->clr_rising);
  349. return 0;
  350. }
  351. static int
  352. davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq,
  353. irq_hw_number_t hw)
  354. {
  355. struct davinci_gpio_controller *chips =
  356. (struct davinci_gpio_controller *)d->host_data;
  357. struct davinci_gpio_regs __iomem *g = chips->regs[hw / 32];
  358. irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq,
  359. "davinci_gpio");
  360. irq_set_irq_type(irq, IRQ_TYPE_NONE);
  361. irq_set_chip_data(irq, (__force void *)g);
  362. irq_set_handler_data(irq, (void *)(uintptr_t)__gpio_mask(hw));
  363. return 0;
  364. }
  365. static const struct irq_domain_ops davinci_gpio_irq_ops = {
  366. .map = davinci_gpio_irq_map,
  367. .xlate = irq_domain_xlate_onetwocell,
  368. };
  369. static struct irq_chip *davinci_gpio_get_irq_chip(unsigned int irq)
  370. {
  371. static struct irq_chip_type gpio_unbanked;
  372. gpio_unbanked = *irq_data_get_chip_type(irq_get_irq_data(irq));
  373. return &gpio_unbanked.chip;
  374. };
  375. static struct irq_chip *keystone_gpio_get_irq_chip(unsigned int irq)
  376. {
  377. static struct irq_chip gpio_unbanked;
  378. gpio_unbanked = *irq_get_chip(irq);
  379. return &gpio_unbanked;
  380. };
  381. static const struct of_device_id davinci_gpio_ids[];
  382. /*
  383. * NOTE: for suspend/resume, probably best to make a platform_device with
  384. * suspend_late/resume_resume calls hooking into results of the set_wake()
  385. * calls ... so if no gpios are wakeup events the clock can be disabled,
  386. * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
  387. * (dm6446) can be set appropriately for GPIOV33 pins.
  388. */
  389. static int davinci_gpio_irq_setup(struct platform_device *pdev)
  390. {
  391. unsigned gpio, bank;
  392. int irq;
  393. int ret;
  394. struct clk *clk;
  395. u32 binten = 0;
  396. unsigned ngpio;
  397. struct device *dev = &pdev->dev;
  398. struct davinci_gpio_controller *chips = platform_get_drvdata(pdev);
  399. struct davinci_gpio_platform_data *pdata = dev->platform_data;
  400. struct davinci_gpio_regs __iomem *g;
  401. struct irq_domain *irq_domain = NULL;
  402. const struct of_device_id *match;
  403. struct irq_chip *irq_chip;
  404. struct davinci_gpio_irq_data *irqdata;
  405. gpio_get_irq_chip_cb_t gpio_get_irq_chip;
  406. /*
  407. * Use davinci_gpio_get_irq_chip by default to handle non DT cases
  408. */
  409. gpio_get_irq_chip = davinci_gpio_get_irq_chip;
  410. match = of_match_device(of_match_ptr(davinci_gpio_ids),
  411. dev);
  412. if (match)
  413. gpio_get_irq_chip = (gpio_get_irq_chip_cb_t)match->data;
  414. ngpio = pdata->ngpio;
  415. clk = devm_clk_get(dev, "gpio");
  416. if (IS_ERR(clk)) {
  417. dev_err(dev, "Error %ld getting gpio clock\n", PTR_ERR(clk));
  418. return PTR_ERR(clk);
  419. }
  420. ret = clk_prepare_enable(clk);
  421. if (ret)
  422. return ret;
  423. if (!pdata->gpio_unbanked) {
  424. irq = devm_irq_alloc_descs(dev, -1, 0, ngpio, 0);
  425. if (irq < 0) {
  426. dev_err(dev, "Couldn't allocate IRQ numbers\n");
  427. clk_disable_unprepare(clk);
  428. return irq;
  429. }
  430. irq_domain = irq_domain_add_legacy(dev->of_node, ngpio, irq, 0,
  431. &davinci_gpio_irq_ops,
  432. chips);
  433. if (!irq_domain) {
  434. dev_err(dev, "Couldn't register an IRQ domain\n");
  435. clk_disable_unprepare(clk);
  436. return -ENODEV;
  437. }
  438. }
  439. /*
  440. * Arrange gpio_to_irq() support, handling either direct IRQs or
  441. * banked IRQs. Having GPIOs in the first GPIO bank use direct
  442. * IRQs, while the others use banked IRQs, would need some setup
  443. * tweaks to recognize hardware which can do that.
  444. */
  445. chips->chip.to_irq = gpio_to_irq_banked;
  446. chips->irq_domain = irq_domain;
  447. /*
  448. * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
  449. * controller only handling trigger modes. We currently assume no
  450. * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
  451. */
  452. if (pdata->gpio_unbanked) {
  453. /* pass "bank 0" GPIO IRQs to AINTC */
  454. chips->chip.to_irq = gpio_to_irq_unbanked;
  455. chips->gpio_unbanked = pdata->gpio_unbanked;
  456. binten = GENMASK(pdata->gpio_unbanked / 16, 0);
  457. /* AINTC handles mask/unmask; GPIO handles triggering */
  458. irq = chips->irqs[0];
  459. irq_chip = gpio_get_irq_chip(irq);
  460. irq_chip->name = "GPIO-AINTC";
  461. irq_chip->irq_set_type = gpio_irq_type_unbanked;
  462. /* default trigger: both edges */
  463. g = chips->regs[0];
  464. writel_relaxed(~0, &g->set_falling);
  465. writel_relaxed(~0, &g->set_rising);
  466. /* set the direct IRQs up to use that irqchip */
  467. for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++) {
  468. irq_set_chip(chips->irqs[gpio], irq_chip);
  469. irq_set_handler_data(chips->irqs[gpio], chips);
  470. irq_set_status_flags(chips->irqs[gpio],
  471. IRQ_TYPE_EDGE_BOTH);
  472. }
  473. goto done;
  474. }
  475. /*
  476. * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
  477. * then chain through our own handler.
  478. */
  479. for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 16) {
  480. /* disabled by default, enabled only as needed
  481. * There are register sets for 32 GPIOs. 2 banks of 16
  482. * GPIOs are covered by each set of registers hence divide by 2
  483. */
  484. g = chips->regs[bank / 2];
  485. writel_relaxed(~0, &g->clr_falling);
  486. writel_relaxed(~0, &g->clr_rising);
  487. /*
  488. * Each chip handles 32 gpios, and each irq bank consists of 16
  489. * gpio irqs. Pass the irq bank's corresponding controller to
  490. * the chained irq handler.
  491. */
  492. irqdata = devm_kzalloc(&pdev->dev,
  493. sizeof(struct
  494. davinci_gpio_irq_data),
  495. GFP_KERNEL);
  496. if (!irqdata) {
  497. clk_disable_unprepare(clk);
  498. return -ENOMEM;
  499. }
  500. irqdata->regs = g;
  501. irqdata->bank_num = bank;
  502. irqdata->chip = chips;
  503. irq_set_chained_handler_and_data(chips->irqs[bank],
  504. gpio_irq_handler, irqdata);
  505. binten |= BIT(bank);
  506. }
  507. done:
  508. /*
  509. * BINTEN -- per-bank interrupt enable. genirq would also let these
  510. * bits be set/cleared dynamically.
  511. */
  512. writel_relaxed(binten, gpio_base + BINTEN);
  513. return 0;
  514. }
  515. static const struct of_device_id davinci_gpio_ids[] = {
  516. { .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip},
  517. { .compatible = "ti,am654-gpio", keystone_gpio_get_irq_chip},
  518. { .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip},
  519. { /* sentinel */ },
  520. };
  521. MODULE_DEVICE_TABLE(of, davinci_gpio_ids);
  522. static struct platform_driver davinci_gpio_driver = {
  523. .probe = davinci_gpio_probe,
  524. .driver = {
  525. .name = "davinci_gpio",
  526. .of_match_table = of_match_ptr(davinci_gpio_ids),
  527. },
  528. };
  529. /**
  530. * GPIO driver registration needs to be done before machine_init functions
  531. * access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall.
  532. */
  533. static int __init davinci_gpio_drv_reg(void)
  534. {
  535. return platform_driver_register(&davinci_gpio_driver);
  536. }
  537. postcore_initcall(davinci_gpio_drv_reg);