gpio-crystalcove.c 9.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Intel Crystal Cove GPIO Driver
  4. *
  5. * Copyright (C) 2012, 2014 Intel Corporation. All rights reserved.
  6. *
  7. * Author: Yang, Bin <bin.yang@intel.com>
  8. */
  9. #include <linux/bitops.h>
  10. #include <linux/gpio/driver.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/mfd/intel_soc_pmic.h>
  13. #include <linux/module.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/regmap.h>
  16. #include <linux/seq_file.h>
  17. #define CRYSTALCOVE_GPIO_NUM 16
  18. #define CRYSTALCOVE_VGPIO_NUM 95
  19. #define UPDATE_IRQ_TYPE BIT(0)
  20. #define UPDATE_IRQ_MASK BIT(1)
  21. #define GPIO0IRQ 0x0b
  22. #define GPIO1IRQ 0x0c
  23. #define MGPIO0IRQS0 0x19
  24. #define MGPIO1IRQS0 0x1a
  25. #define MGPIO0IRQSX 0x1b
  26. #define MGPIO1IRQSX 0x1c
  27. #define GPIO0P0CTLO 0x2b
  28. #define GPIO0P0CTLI 0x33
  29. #define GPIO1P0CTLO 0x3b
  30. #define GPIO1P0CTLI 0x43
  31. #define GPIOPANELCTL 0x52
  32. #define CTLI_INTCNT_DIS (0)
  33. #define CTLI_INTCNT_NE (1 << 1)
  34. #define CTLI_INTCNT_PE (2 << 1)
  35. #define CTLI_INTCNT_BE (3 << 1)
  36. #define CTLO_DIR_IN (0)
  37. #define CTLO_DIR_OUT (1 << 5)
  38. #define CTLO_DRV_CMOS (0)
  39. #define CTLO_DRV_OD (1 << 4)
  40. #define CTLO_DRV_REN (1 << 3)
  41. #define CTLO_RVAL_2KDW (0)
  42. #define CTLO_RVAL_2KUP (1 << 1)
  43. #define CTLO_RVAL_50KDW (2 << 1)
  44. #define CTLO_RVAL_50KUP (3 << 1)
  45. #define CTLO_INPUT_SET (CTLO_DRV_CMOS | CTLO_DRV_REN | CTLO_RVAL_2KUP)
  46. #define CTLO_OUTPUT_SET (CTLO_DIR_OUT | CTLO_INPUT_SET)
  47. enum ctrl_register {
  48. CTRL_IN,
  49. CTRL_OUT,
  50. };
  51. /**
  52. * struct crystalcove_gpio - Crystal Cove GPIO controller
  53. * @buslock: for bus lock/sync and unlock.
  54. * @chip: the abstract gpio_chip structure.
  55. * @regmap: the regmap from the parent device.
  56. * @update: pending IRQ setting update, to be written to the chip upon unlock.
  57. * @intcnt_value: the Interrupt Detect value to be written.
  58. * @set_irq_mask: true if the IRQ mask needs to be set, false to clear.
  59. */
  60. struct crystalcove_gpio {
  61. struct mutex buslock; /* irq_bus_lock */
  62. struct gpio_chip chip;
  63. struct regmap *regmap;
  64. int update;
  65. int intcnt_value;
  66. bool set_irq_mask;
  67. };
  68. static inline int to_reg(int gpio, enum ctrl_register reg_type)
  69. {
  70. int reg;
  71. if (gpio >= CRYSTALCOVE_GPIO_NUM) {
  72. /*
  73. * Virtual GPIO called from ACPI, for now we only support
  74. * the panel ctl.
  75. */
  76. switch (gpio) {
  77. case 0x5e:
  78. return GPIOPANELCTL;
  79. default:
  80. return -EOPNOTSUPP;
  81. }
  82. }
  83. if (reg_type == CTRL_IN) {
  84. if (gpio < 8)
  85. reg = GPIO0P0CTLI;
  86. else
  87. reg = GPIO1P0CTLI;
  88. } else {
  89. if (gpio < 8)
  90. reg = GPIO0P0CTLO;
  91. else
  92. reg = GPIO1P0CTLO;
  93. }
  94. return reg + gpio % 8;
  95. }
  96. static void crystalcove_update_irq_mask(struct crystalcove_gpio *cg,
  97. int gpio)
  98. {
  99. u8 mirqs0 = gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0;
  100. int mask = BIT(gpio % 8);
  101. if (cg->set_irq_mask)
  102. regmap_update_bits(cg->regmap, mirqs0, mask, mask);
  103. else
  104. regmap_update_bits(cg->regmap, mirqs0, mask, 0);
  105. }
  106. static void crystalcove_update_irq_ctrl(struct crystalcove_gpio *cg, int gpio)
  107. {
  108. int reg = to_reg(gpio, CTRL_IN);
  109. regmap_update_bits(cg->regmap, reg, CTLI_INTCNT_BE, cg->intcnt_value);
  110. }
  111. static int crystalcove_gpio_dir_in(struct gpio_chip *chip, unsigned int gpio)
  112. {
  113. struct crystalcove_gpio *cg = gpiochip_get_data(chip);
  114. int reg = to_reg(gpio, CTRL_OUT);
  115. if (reg < 0)
  116. return 0;
  117. return regmap_write(cg->regmap, reg, CTLO_INPUT_SET);
  118. }
  119. static int crystalcove_gpio_dir_out(struct gpio_chip *chip, unsigned int gpio,
  120. int value)
  121. {
  122. struct crystalcove_gpio *cg = gpiochip_get_data(chip);
  123. int reg = to_reg(gpio, CTRL_OUT);
  124. if (reg < 0)
  125. return 0;
  126. return regmap_write(cg->regmap, reg, CTLO_OUTPUT_SET | value);
  127. }
  128. static int crystalcove_gpio_get(struct gpio_chip *chip, unsigned int gpio)
  129. {
  130. struct crystalcove_gpio *cg = gpiochip_get_data(chip);
  131. unsigned int val;
  132. int ret, reg = to_reg(gpio, CTRL_IN);
  133. if (reg < 0)
  134. return 0;
  135. ret = regmap_read(cg->regmap, reg, &val);
  136. if (ret)
  137. return ret;
  138. return val & 0x1;
  139. }
  140. static void crystalcove_gpio_set(struct gpio_chip *chip,
  141. unsigned int gpio, int value)
  142. {
  143. struct crystalcove_gpio *cg = gpiochip_get_data(chip);
  144. int reg = to_reg(gpio, CTRL_OUT);
  145. if (reg < 0)
  146. return;
  147. if (value)
  148. regmap_update_bits(cg->regmap, reg, 1, 1);
  149. else
  150. regmap_update_bits(cg->regmap, reg, 1, 0);
  151. }
  152. static int crystalcove_irq_type(struct irq_data *data, unsigned int type)
  153. {
  154. struct crystalcove_gpio *cg =
  155. gpiochip_get_data(irq_data_get_irq_chip_data(data));
  156. if (data->hwirq >= CRYSTALCOVE_GPIO_NUM)
  157. return 0;
  158. switch (type) {
  159. case IRQ_TYPE_NONE:
  160. cg->intcnt_value = CTLI_INTCNT_DIS;
  161. break;
  162. case IRQ_TYPE_EDGE_BOTH:
  163. cg->intcnt_value = CTLI_INTCNT_BE;
  164. break;
  165. case IRQ_TYPE_EDGE_RISING:
  166. cg->intcnt_value = CTLI_INTCNT_PE;
  167. break;
  168. case IRQ_TYPE_EDGE_FALLING:
  169. cg->intcnt_value = CTLI_INTCNT_NE;
  170. break;
  171. default:
  172. return -EINVAL;
  173. }
  174. cg->update |= UPDATE_IRQ_TYPE;
  175. return 0;
  176. }
  177. static void crystalcove_bus_lock(struct irq_data *data)
  178. {
  179. struct crystalcove_gpio *cg =
  180. gpiochip_get_data(irq_data_get_irq_chip_data(data));
  181. mutex_lock(&cg->buslock);
  182. }
  183. static void crystalcove_bus_sync_unlock(struct irq_data *data)
  184. {
  185. struct crystalcove_gpio *cg =
  186. gpiochip_get_data(irq_data_get_irq_chip_data(data));
  187. int gpio = data->hwirq;
  188. if (cg->update & UPDATE_IRQ_TYPE)
  189. crystalcove_update_irq_ctrl(cg, gpio);
  190. if (cg->update & UPDATE_IRQ_MASK)
  191. crystalcove_update_irq_mask(cg, gpio);
  192. cg->update = 0;
  193. mutex_unlock(&cg->buslock);
  194. }
  195. static void crystalcove_irq_unmask(struct irq_data *data)
  196. {
  197. struct crystalcove_gpio *cg =
  198. gpiochip_get_data(irq_data_get_irq_chip_data(data));
  199. if (data->hwirq < CRYSTALCOVE_GPIO_NUM) {
  200. cg->set_irq_mask = false;
  201. cg->update |= UPDATE_IRQ_MASK;
  202. }
  203. }
  204. static void crystalcove_irq_mask(struct irq_data *data)
  205. {
  206. struct crystalcove_gpio *cg =
  207. gpiochip_get_data(irq_data_get_irq_chip_data(data));
  208. if (data->hwirq < CRYSTALCOVE_GPIO_NUM) {
  209. cg->set_irq_mask = true;
  210. cg->update |= UPDATE_IRQ_MASK;
  211. }
  212. }
  213. static struct irq_chip crystalcove_irqchip = {
  214. .name = "Crystal Cove",
  215. .irq_mask = crystalcove_irq_mask,
  216. .irq_unmask = crystalcove_irq_unmask,
  217. .irq_set_type = crystalcove_irq_type,
  218. .irq_bus_lock = crystalcove_bus_lock,
  219. .irq_bus_sync_unlock = crystalcove_bus_sync_unlock,
  220. .flags = IRQCHIP_SKIP_SET_WAKE,
  221. };
  222. static irqreturn_t crystalcove_gpio_irq_handler(int irq, void *data)
  223. {
  224. struct crystalcove_gpio *cg = data;
  225. unsigned long pending;
  226. unsigned int p0, p1;
  227. int gpio;
  228. unsigned int virq;
  229. if (regmap_read(cg->regmap, GPIO0IRQ, &p0) ||
  230. regmap_read(cg->regmap, GPIO1IRQ, &p1))
  231. return IRQ_NONE;
  232. regmap_write(cg->regmap, GPIO0IRQ, p0);
  233. regmap_write(cg->regmap, GPIO1IRQ, p1);
  234. pending = p0 | p1 << 8;
  235. for_each_set_bit(gpio, &pending, CRYSTALCOVE_GPIO_NUM) {
  236. virq = irq_find_mapping(cg->chip.irq.domain, gpio);
  237. handle_nested_irq(virq);
  238. }
  239. return IRQ_HANDLED;
  240. }
  241. static void crystalcove_gpio_dbg_show(struct seq_file *s,
  242. struct gpio_chip *chip)
  243. {
  244. struct crystalcove_gpio *cg = gpiochip_get_data(chip);
  245. int gpio, offset;
  246. unsigned int ctlo, ctli, mirqs0, mirqsx, irq;
  247. for (gpio = 0; gpio < CRYSTALCOVE_GPIO_NUM; gpio++) {
  248. regmap_read(cg->regmap, to_reg(gpio, CTRL_OUT), &ctlo);
  249. regmap_read(cg->regmap, to_reg(gpio, CTRL_IN), &ctli);
  250. regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0,
  251. &mirqs0);
  252. regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQSX : MGPIO1IRQSX,
  253. &mirqsx);
  254. regmap_read(cg->regmap, gpio < 8 ? GPIO0IRQ : GPIO1IRQ,
  255. &irq);
  256. offset = gpio % 8;
  257. seq_printf(s, " gpio-%-2d %s %s %s %s ctlo=%2x,%s %s %s\n",
  258. gpio, ctlo & CTLO_DIR_OUT ? "out" : "in ",
  259. ctli & 0x1 ? "hi" : "lo",
  260. ctli & CTLI_INTCNT_NE ? "fall" : " ",
  261. ctli & CTLI_INTCNT_PE ? "rise" : " ",
  262. ctlo,
  263. mirqs0 & BIT(offset) ? "s0 mask " : "s0 unmask",
  264. mirqsx & BIT(offset) ? "sx mask " : "sx unmask",
  265. irq & BIT(offset) ? "pending" : " ");
  266. }
  267. }
  268. static int crystalcove_gpio_probe(struct platform_device *pdev)
  269. {
  270. int irq = platform_get_irq(pdev, 0);
  271. struct crystalcove_gpio *cg;
  272. int retval;
  273. struct device *dev = pdev->dev.parent;
  274. struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
  275. struct gpio_irq_chip *girq;
  276. if (irq < 0)
  277. return irq;
  278. cg = devm_kzalloc(&pdev->dev, sizeof(*cg), GFP_KERNEL);
  279. if (!cg)
  280. return -ENOMEM;
  281. platform_set_drvdata(pdev, cg);
  282. mutex_init(&cg->buslock);
  283. cg->chip.label = KBUILD_MODNAME;
  284. cg->chip.direction_input = crystalcove_gpio_dir_in;
  285. cg->chip.direction_output = crystalcove_gpio_dir_out;
  286. cg->chip.get = crystalcove_gpio_get;
  287. cg->chip.set = crystalcove_gpio_set;
  288. cg->chip.base = -1;
  289. cg->chip.ngpio = CRYSTALCOVE_VGPIO_NUM;
  290. cg->chip.can_sleep = true;
  291. cg->chip.parent = dev;
  292. cg->chip.dbg_show = crystalcove_gpio_dbg_show;
  293. cg->regmap = pmic->regmap;
  294. girq = &cg->chip.irq;
  295. girq->chip = &crystalcove_irqchip;
  296. /* This will let us handle the parent IRQ in the driver */
  297. girq->parent_handler = NULL;
  298. girq->num_parents = 0;
  299. girq->parents = NULL;
  300. girq->default_type = IRQ_TYPE_NONE;
  301. girq->handler = handle_simple_irq;
  302. girq->threaded = true;
  303. retval = devm_request_threaded_irq(&pdev->dev, irq, NULL,
  304. crystalcove_gpio_irq_handler,
  305. IRQF_ONESHOT, KBUILD_MODNAME, cg);
  306. if (retval) {
  307. dev_warn(&pdev->dev, "request irq failed: %d\n", retval);
  308. return retval;
  309. }
  310. retval = devm_gpiochip_add_data(&pdev->dev, &cg->chip, cg);
  311. if (retval) {
  312. dev_warn(&pdev->dev, "add gpio chip error: %d\n", retval);
  313. return retval;
  314. }
  315. return 0;
  316. }
  317. static struct platform_driver crystalcove_gpio_driver = {
  318. .probe = crystalcove_gpio_probe,
  319. .driver = {
  320. .name = "crystal_cove_gpio",
  321. },
  322. };
  323. module_platform_driver(crystalcove_gpio_driver);
  324. MODULE_AUTHOR("Yang, Bin <bin.yang@intel.com>");
  325. MODULE_DESCRIPTION("Intel Crystal Cove GPIO Driver");
  326. MODULE_LICENSE("GPL v2");