gpio-cadence.c 7.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2017-2018 Cadence
  4. *
  5. * Authors:
  6. * Jan Kotas <jank@cadence.com>
  7. * Boris Brezillon <boris.brezillon@free-electrons.com>
  8. */
  9. #include <linux/gpio/driver.h>
  10. #include <linux/clk.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/kernel.h>
  13. #include <linux/module.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/spinlock.h>
  16. #define CDNS_GPIO_BYPASS_MODE 0x00
  17. #define CDNS_GPIO_DIRECTION_MODE 0x04
  18. #define CDNS_GPIO_OUTPUT_EN 0x08
  19. #define CDNS_GPIO_OUTPUT_VALUE 0x0c
  20. #define CDNS_GPIO_INPUT_VALUE 0x10
  21. #define CDNS_GPIO_IRQ_MASK 0x14
  22. #define CDNS_GPIO_IRQ_EN 0x18
  23. #define CDNS_GPIO_IRQ_DIS 0x1c
  24. #define CDNS_GPIO_IRQ_STATUS 0x20
  25. #define CDNS_GPIO_IRQ_TYPE 0x24
  26. #define CDNS_GPIO_IRQ_VALUE 0x28
  27. #define CDNS_GPIO_IRQ_ANY_EDGE 0x2c
  28. struct cdns_gpio_chip {
  29. struct gpio_chip gc;
  30. struct clk *pclk;
  31. void __iomem *regs;
  32. u32 bypass_orig;
  33. };
  34. static int cdns_gpio_request(struct gpio_chip *chip, unsigned int offset)
  35. {
  36. struct cdns_gpio_chip *cgpio = gpiochip_get_data(chip);
  37. unsigned long flags;
  38. spin_lock_irqsave(&chip->bgpio_lock, flags);
  39. iowrite32(ioread32(cgpio->regs + CDNS_GPIO_BYPASS_MODE) & ~BIT(offset),
  40. cgpio->regs + CDNS_GPIO_BYPASS_MODE);
  41. spin_unlock_irqrestore(&chip->bgpio_lock, flags);
  42. return 0;
  43. }
  44. static void cdns_gpio_free(struct gpio_chip *chip, unsigned int offset)
  45. {
  46. struct cdns_gpio_chip *cgpio = gpiochip_get_data(chip);
  47. unsigned long flags;
  48. spin_lock_irqsave(&chip->bgpio_lock, flags);
  49. iowrite32(ioread32(cgpio->regs + CDNS_GPIO_BYPASS_MODE) |
  50. (BIT(offset) & cgpio->bypass_orig),
  51. cgpio->regs + CDNS_GPIO_BYPASS_MODE);
  52. spin_unlock_irqrestore(&chip->bgpio_lock, flags);
  53. }
  54. static void cdns_gpio_irq_mask(struct irq_data *d)
  55. {
  56. struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
  57. struct cdns_gpio_chip *cgpio = gpiochip_get_data(chip);
  58. iowrite32(BIT(d->hwirq), cgpio->regs + CDNS_GPIO_IRQ_DIS);
  59. }
  60. static void cdns_gpio_irq_unmask(struct irq_data *d)
  61. {
  62. struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
  63. struct cdns_gpio_chip *cgpio = gpiochip_get_data(chip);
  64. iowrite32(BIT(d->hwirq), cgpio->regs + CDNS_GPIO_IRQ_EN);
  65. }
  66. static int cdns_gpio_irq_set_type(struct irq_data *d, unsigned int type)
  67. {
  68. struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
  69. struct cdns_gpio_chip *cgpio = gpiochip_get_data(chip);
  70. unsigned long flags;
  71. u32 int_value;
  72. u32 int_type;
  73. u32 mask = BIT(d->hwirq);
  74. int ret = 0;
  75. spin_lock_irqsave(&chip->bgpio_lock, flags);
  76. int_value = ioread32(cgpio->regs + CDNS_GPIO_IRQ_VALUE) & ~mask;
  77. int_type = ioread32(cgpio->regs + CDNS_GPIO_IRQ_TYPE) & ~mask;
  78. /*
  79. * The GPIO controller doesn't have an ACK register.
  80. * All interrupt statuses are cleared on a status register read.
  81. * Don't support edge interrupts for now.
  82. */
  83. if (type == IRQ_TYPE_LEVEL_HIGH) {
  84. int_type |= mask;
  85. int_value |= mask;
  86. } else if (type == IRQ_TYPE_LEVEL_LOW) {
  87. int_type |= mask;
  88. } else {
  89. ret = -EINVAL;
  90. goto err_irq_type;
  91. }
  92. iowrite32(int_value, cgpio->regs + CDNS_GPIO_IRQ_VALUE);
  93. iowrite32(int_type, cgpio->regs + CDNS_GPIO_IRQ_TYPE);
  94. err_irq_type:
  95. spin_unlock_irqrestore(&chip->bgpio_lock, flags);
  96. return ret;
  97. }
  98. static void cdns_gpio_irq_handler(struct irq_desc *desc)
  99. {
  100. struct gpio_chip *chip = irq_desc_get_handler_data(desc);
  101. struct cdns_gpio_chip *cgpio = gpiochip_get_data(chip);
  102. struct irq_chip *irqchip = irq_desc_get_chip(desc);
  103. unsigned long status;
  104. int hwirq;
  105. chained_irq_enter(irqchip, desc);
  106. status = ioread32(cgpio->regs + CDNS_GPIO_IRQ_STATUS) &
  107. ~ioread32(cgpio->regs + CDNS_GPIO_IRQ_MASK);
  108. for_each_set_bit(hwirq, &status, chip->ngpio)
  109. generic_handle_irq(irq_find_mapping(chip->irq.domain, hwirq));
  110. chained_irq_exit(irqchip, desc);
  111. }
  112. static struct irq_chip cdns_gpio_irqchip = {
  113. .name = "cdns-gpio",
  114. .irq_mask = cdns_gpio_irq_mask,
  115. .irq_unmask = cdns_gpio_irq_unmask,
  116. .irq_set_type = cdns_gpio_irq_set_type
  117. };
  118. static int cdns_gpio_probe(struct platform_device *pdev)
  119. {
  120. struct cdns_gpio_chip *cgpio;
  121. int ret, irq;
  122. u32 dir_prev;
  123. u32 num_gpios = 32;
  124. cgpio = devm_kzalloc(&pdev->dev, sizeof(*cgpio), GFP_KERNEL);
  125. if (!cgpio)
  126. return -ENOMEM;
  127. cgpio->regs = devm_platform_ioremap_resource(pdev, 0);
  128. if (IS_ERR(cgpio->regs))
  129. return PTR_ERR(cgpio->regs);
  130. of_property_read_u32(pdev->dev.of_node, "ngpios", &num_gpios);
  131. if (num_gpios > 32) {
  132. dev_err(&pdev->dev, "ngpios must be less or equal 32\n");
  133. return -EINVAL;
  134. }
  135. /*
  136. * Set all pins as inputs by default, otherwise:
  137. * gpiochip_lock_as_irq:
  138. * tried to flag a GPIO set as output for IRQ
  139. * Generic GPIO driver stores the direction value internally,
  140. * so it needs to be changed before bgpio_init() is called.
  141. */
  142. dir_prev = ioread32(cgpio->regs + CDNS_GPIO_DIRECTION_MODE);
  143. iowrite32(GENMASK(num_gpios - 1, 0),
  144. cgpio->regs + CDNS_GPIO_DIRECTION_MODE);
  145. ret = bgpio_init(&cgpio->gc, &pdev->dev, 4,
  146. cgpio->regs + CDNS_GPIO_INPUT_VALUE,
  147. cgpio->regs + CDNS_GPIO_OUTPUT_VALUE,
  148. NULL,
  149. NULL,
  150. cgpio->regs + CDNS_GPIO_DIRECTION_MODE,
  151. BGPIOF_READ_OUTPUT_REG_SET);
  152. if (ret) {
  153. dev_err(&pdev->dev, "Failed to register generic gpio, %d\n",
  154. ret);
  155. goto err_revert_dir;
  156. }
  157. cgpio->gc.label = dev_name(&pdev->dev);
  158. cgpio->gc.ngpio = num_gpios;
  159. cgpio->gc.parent = &pdev->dev;
  160. cgpio->gc.base = -1;
  161. cgpio->gc.owner = THIS_MODULE;
  162. cgpio->gc.request = cdns_gpio_request;
  163. cgpio->gc.free = cdns_gpio_free;
  164. cgpio->pclk = devm_clk_get(&pdev->dev, NULL);
  165. if (IS_ERR(cgpio->pclk)) {
  166. ret = PTR_ERR(cgpio->pclk);
  167. dev_err(&pdev->dev,
  168. "Failed to retrieve peripheral clock, %d\n", ret);
  169. goto err_revert_dir;
  170. }
  171. ret = clk_prepare_enable(cgpio->pclk);
  172. if (ret) {
  173. dev_err(&pdev->dev,
  174. "Failed to enable the peripheral clock, %d\n", ret);
  175. goto err_revert_dir;
  176. }
  177. /*
  178. * Optional irq_chip support
  179. */
  180. irq = platform_get_irq(pdev, 0);
  181. if (irq >= 0) {
  182. struct gpio_irq_chip *girq;
  183. girq = &cgpio->gc.irq;
  184. girq->chip = &cdns_gpio_irqchip;
  185. girq->parent_handler = cdns_gpio_irq_handler;
  186. girq->num_parents = 1;
  187. girq->parents = devm_kcalloc(&pdev->dev, 1,
  188. sizeof(*girq->parents),
  189. GFP_KERNEL);
  190. if (!girq->parents) {
  191. ret = -ENOMEM;
  192. goto err_disable_clk;
  193. }
  194. girq->parents[0] = irq;
  195. girq->default_type = IRQ_TYPE_NONE;
  196. girq->handler = handle_level_irq;
  197. }
  198. ret = devm_gpiochip_add_data(&pdev->dev, &cgpio->gc, cgpio);
  199. if (ret < 0) {
  200. dev_err(&pdev->dev, "Could not register gpiochip, %d\n", ret);
  201. goto err_disable_clk;
  202. }
  203. cgpio->bypass_orig = ioread32(cgpio->regs + CDNS_GPIO_BYPASS_MODE);
  204. /*
  205. * Enable gpio outputs, ignored for input direction
  206. */
  207. iowrite32(GENMASK(num_gpios - 1, 0),
  208. cgpio->regs + CDNS_GPIO_OUTPUT_EN);
  209. iowrite32(0, cgpio->regs + CDNS_GPIO_BYPASS_MODE);
  210. platform_set_drvdata(pdev, cgpio);
  211. return 0;
  212. err_disable_clk:
  213. clk_disable_unprepare(cgpio->pclk);
  214. err_revert_dir:
  215. iowrite32(dir_prev, cgpio->regs + CDNS_GPIO_DIRECTION_MODE);
  216. return ret;
  217. }
  218. static int cdns_gpio_remove(struct platform_device *pdev)
  219. {
  220. struct cdns_gpio_chip *cgpio = platform_get_drvdata(pdev);
  221. iowrite32(cgpio->bypass_orig, cgpio->regs + CDNS_GPIO_BYPASS_MODE);
  222. clk_disable_unprepare(cgpio->pclk);
  223. return 0;
  224. }
  225. static const struct of_device_id cdns_of_ids[] = {
  226. { .compatible = "cdns,gpio-r1p02" },
  227. { /* sentinel */ },
  228. };
  229. MODULE_DEVICE_TABLE(of, cdns_of_ids);
  230. static struct platform_driver cdns_gpio_driver = {
  231. .driver = {
  232. .name = "cdns-gpio",
  233. .of_match_table = cdns_of_ids,
  234. },
  235. .probe = cdns_gpio_probe,
  236. .remove = cdns_gpio_remove,
  237. };
  238. module_platform_driver(cdns_gpio_driver);
  239. MODULE_AUTHOR("Jan Kotas <jank@cadence.com>");
  240. MODULE_DESCRIPTION("Cadence GPIO driver");
  241. MODULE_LICENSE("GPL v2");
  242. MODULE_ALIAS("platform:cdns-gpio");