gpio-brcmstb.c 22 KB

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  1. /*
  2. * Copyright (C) 2015-2017 Broadcom
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License as
  6. * published by the Free Software Foundation version 2.
  7. *
  8. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  9. * kind, whether express or implied; without even the implied warranty
  10. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. */
  13. #include <linux/bitops.h>
  14. #include <linux/gpio/driver.h>
  15. #include <linux/of_device.h>
  16. #include <linux/of_irq.h>
  17. #include <linux/module.h>
  18. #include <linux/irqdomain.h>
  19. #include <linux/irqchip/chained_irq.h>
  20. #include <linux/interrupt.h>
  21. enum gio_reg_index {
  22. GIO_REG_ODEN = 0,
  23. GIO_REG_DATA,
  24. GIO_REG_IODIR,
  25. GIO_REG_EC,
  26. GIO_REG_EI,
  27. GIO_REG_MASK,
  28. GIO_REG_LEVEL,
  29. GIO_REG_STAT,
  30. NUMBER_OF_GIO_REGISTERS
  31. };
  32. #define GIO_BANK_SIZE (NUMBER_OF_GIO_REGISTERS * sizeof(u32))
  33. #define GIO_BANK_OFF(bank, off) (((bank) * GIO_BANK_SIZE) + (off * sizeof(u32)))
  34. #define GIO_ODEN(bank) GIO_BANK_OFF(bank, GIO_REG_ODEN)
  35. #define GIO_DATA(bank) GIO_BANK_OFF(bank, GIO_REG_DATA)
  36. #define GIO_IODIR(bank) GIO_BANK_OFF(bank, GIO_REG_IODIR)
  37. #define GIO_EC(bank) GIO_BANK_OFF(bank, GIO_REG_EC)
  38. #define GIO_EI(bank) GIO_BANK_OFF(bank, GIO_REG_EI)
  39. #define GIO_MASK(bank) GIO_BANK_OFF(bank, GIO_REG_MASK)
  40. #define GIO_LEVEL(bank) GIO_BANK_OFF(bank, GIO_REG_LEVEL)
  41. #define GIO_STAT(bank) GIO_BANK_OFF(bank, GIO_REG_STAT)
  42. struct brcmstb_gpio_bank {
  43. struct list_head node;
  44. int id;
  45. struct gpio_chip gc;
  46. struct brcmstb_gpio_priv *parent_priv;
  47. u32 width;
  48. u32 wake_active;
  49. u32 saved_regs[GIO_REG_STAT]; /* Don't save and restore GIO_REG_STAT */
  50. };
  51. struct brcmstb_gpio_priv {
  52. struct list_head bank_list;
  53. void __iomem *reg_base;
  54. struct platform_device *pdev;
  55. struct irq_domain *irq_domain;
  56. struct irq_chip irq_chip;
  57. int parent_irq;
  58. int gpio_base;
  59. int num_gpios;
  60. int parent_wake_irq;
  61. };
  62. #define MAX_GPIO_PER_BANK 32
  63. #define GPIO_BANK(gpio) ((gpio) >> 5)
  64. /* assumes MAX_GPIO_PER_BANK is a multiple of 2 */
  65. #define GPIO_BIT(gpio) ((gpio) & (MAX_GPIO_PER_BANK - 1))
  66. static inline struct brcmstb_gpio_priv *
  67. brcmstb_gpio_gc_to_priv(struct gpio_chip *gc)
  68. {
  69. struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
  70. return bank->parent_priv;
  71. }
  72. static unsigned long
  73. __brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank)
  74. {
  75. void __iomem *reg_base = bank->parent_priv->reg_base;
  76. return bank->gc.read_reg(reg_base + GIO_STAT(bank->id)) &
  77. bank->gc.read_reg(reg_base + GIO_MASK(bank->id));
  78. }
  79. static unsigned long
  80. brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank)
  81. {
  82. unsigned long status;
  83. unsigned long flags;
  84. spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
  85. status = __brcmstb_gpio_get_active_irqs(bank);
  86. spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
  87. return status;
  88. }
  89. static int brcmstb_gpio_hwirq_to_offset(irq_hw_number_t hwirq,
  90. struct brcmstb_gpio_bank *bank)
  91. {
  92. return hwirq - (bank->gc.base - bank->parent_priv->gpio_base);
  93. }
  94. static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank,
  95. unsigned int hwirq, bool enable)
  96. {
  97. struct gpio_chip *gc = &bank->gc;
  98. struct brcmstb_gpio_priv *priv = bank->parent_priv;
  99. u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(hwirq, bank));
  100. u32 imask;
  101. unsigned long flags;
  102. spin_lock_irqsave(&gc->bgpio_lock, flags);
  103. imask = gc->read_reg(priv->reg_base + GIO_MASK(bank->id));
  104. if (enable)
  105. imask |= mask;
  106. else
  107. imask &= ~mask;
  108. gc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask);
  109. spin_unlock_irqrestore(&gc->bgpio_lock, flags);
  110. }
  111. static int brcmstb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
  112. {
  113. struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
  114. /* gc_offset is relative to this gpio_chip; want real offset */
  115. int hwirq = offset + (gc->base - priv->gpio_base);
  116. if (hwirq >= priv->num_gpios)
  117. return -ENXIO;
  118. return irq_create_mapping(priv->irq_domain, hwirq);
  119. }
  120. /* -------------------- IRQ chip functions -------------------- */
  121. static void brcmstb_gpio_irq_mask(struct irq_data *d)
  122. {
  123. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  124. struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
  125. brcmstb_gpio_set_imask(bank, d->hwirq, false);
  126. }
  127. static void brcmstb_gpio_irq_unmask(struct irq_data *d)
  128. {
  129. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  130. struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
  131. brcmstb_gpio_set_imask(bank, d->hwirq, true);
  132. }
  133. static void brcmstb_gpio_irq_ack(struct irq_data *d)
  134. {
  135. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  136. struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
  137. struct brcmstb_gpio_priv *priv = bank->parent_priv;
  138. u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
  139. gc->write_reg(priv->reg_base + GIO_STAT(bank->id), mask);
  140. }
  141. static int brcmstb_gpio_irq_set_type(struct irq_data *d, unsigned int type)
  142. {
  143. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  144. struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
  145. struct brcmstb_gpio_priv *priv = bank->parent_priv;
  146. u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
  147. u32 edge_insensitive, iedge_insensitive;
  148. u32 edge_config, iedge_config;
  149. u32 level, ilevel;
  150. unsigned long flags;
  151. switch (type) {
  152. case IRQ_TYPE_LEVEL_LOW:
  153. level = mask;
  154. edge_config = 0;
  155. edge_insensitive = 0;
  156. break;
  157. case IRQ_TYPE_LEVEL_HIGH:
  158. level = mask;
  159. edge_config = mask;
  160. edge_insensitive = 0;
  161. break;
  162. case IRQ_TYPE_EDGE_FALLING:
  163. level = 0;
  164. edge_config = 0;
  165. edge_insensitive = 0;
  166. break;
  167. case IRQ_TYPE_EDGE_RISING:
  168. level = 0;
  169. edge_config = mask;
  170. edge_insensitive = 0;
  171. break;
  172. case IRQ_TYPE_EDGE_BOTH:
  173. level = 0;
  174. edge_config = 0; /* don't care, but want known value */
  175. edge_insensitive = mask;
  176. break;
  177. default:
  178. return -EINVAL;
  179. }
  180. spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
  181. iedge_config = bank->gc.read_reg(priv->reg_base +
  182. GIO_EC(bank->id)) & ~mask;
  183. iedge_insensitive = bank->gc.read_reg(priv->reg_base +
  184. GIO_EI(bank->id)) & ~mask;
  185. ilevel = bank->gc.read_reg(priv->reg_base +
  186. GIO_LEVEL(bank->id)) & ~mask;
  187. bank->gc.write_reg(priv->reg_base + GIO_EC(bank->id),
  188. iedge_config | edge_config);
  189. bank->gc.write_reg(priv->reg_base + GIO_EI(bank->id),
  190. iedge_insensitive | edge_insensitive);
  191. bank->gc.write_reg(priv->reg_base + GIO_LEVEL(bank->id),
  192. ilevel | level);
  193. spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
  194. return 0;
  195. }
  196. static int brcmstb_gpio_priv_set_wake(struct brcmstb_gpio_priv *priv,
  197. unsigned int enable)
  198. {
  199. int ret = 0;
  200. if (enable)
  201. ret = enable_irq_wake(priv->parent_wake_irq);
  202. else
  203. ret = disable_irq_wake(priv->parent_wake_irq);
  204. if (ret)
  205. dev_err(&priv->pdev->dev, "failed to %s wake-up interrupt\n",
  206. enable ? "enable" : "disable");
  207. return ret;
  208. }
  209. static int brcmstb_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
  210. {
  211. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  212. struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
  213. struct brcmstb_gpio_priv *priv = bank->parent_priv;
  214. u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
  215. /*
  216. * Do not do anything specific for now, suspend/resume callbacks will
  217. * configure the interrupt mask appropriately
  218. */
  219. if (enable)
  220. bank->wake_active |= mask;
  221. else
  222. bank->wake_active &= ~mask;
  223. return brcmstb_gpio_priv_set_wake(priv, enable);
  224. }
  225. static irqreturn_t brcmstb_gpio_wake_irq_handler(int irq, void *data)
  226. {
  227. struct brcmstb_gpio_priv *priv = data;
  228. if (!priv || irq != priv->parent_wake_irq)
  229. return IRQ_NONE;
  230. /* Nothing to do */
  231. return IRQ_HANDLED;
  232. }
  233. static void brcmstb_gpio_irq_bank_handler(struct brcmstb_gpio_bank *bank)
  234. {
  235. struct brcmstb_gpio_priv *priv = bank->parent_priv;
  236. struct irq_domain *domain = priv->irq_domain;
  237. int hwbase = bank->gc.base - priv->gpio_base;
  238. unsigned long status;
  239. while ((status = brcmstb_gpio_get_active_irqs(bank))) {
  240. unsigned int irq, offset;
  241. for_each_set_bit(offset, &status, 32) {
  242. if (offset >= bank->width)
  243. dev_warn(&priv->pdev->dev,
  244. "IRQ for invalid GPIO (bank=%d, offset=%d)\n",
  245. bank->id, offset);
  246. irq = irq_linear_revmap(domain, hwbase + offset);
  247. generic_handle_irq(irq);
  248. }
  249. }
  250. }
  251. /* Each UPG GIO block has one IRQ for all banks */
  252. static void brcmstb_gpio_irq_handler(struct irq_desc *desc)
  253. {
  254. struct brcmstb_gpio_priv *priv = irq_desc_get_handler_data(desc);
  255. struct irq_chip *chip = irq_desc_get_chip(desc);
  256. struct brcmstb_gpio_bank *bank;
  257. /* Interrupts weren't properly cleared during probe */
  258. BUG_ON(!priv || !chip);
  259. chained_irq_enter(chip, desc);
  260. list_for_each_entry(bank, &priv->bank_list, node)
  261. brcmstb_gpio_irq_bank_handler(bank);
  262. chained_irq_exit(chip, desc);
  263. }
  264. static struct brcmstb_gpio_bank *brcmstb_gpio_hwirq_to_bank(
  265. struct brcmstb_gpio_priv *priv, irq_hw_number_t hwirq)
  266. {
  267. struct brcmstb_gpio_bank *bank;
  268. int i = 0;
  269. /* banks are in descending order */
  270. list_for_each_entry_reverse(bank, &priv->bank_list, node) {
  271. i += bank->gc.ngpio;
  272. if (hwirq < i)
  273. return bank;
  274. }
  275. return NULL;
  276. }
  277. /*
  278. * This lock class tells lockdep that GPIO irqs are in a different
  279. * category than their parents, so it won't report false recursion.
  280. */
  281. static struct lock_class_key brcmstb_gpio_irq_lock_class;
  282. static struct lock_class_key brcmstb_gpio_irq_request_class;
  283. static int brcmstb_gpio_irq_map(struct irq_domain *d, unsigned int irq,
  284. irq_hw_number_t hwirq)
  285. {
  286. struct brcmstb_gpio_priv *priv = d->host_data;
  287. struct brcmstb_gpio_bank *bank =
  288. brcmstb_gpio_hwirq_to_bank(priv, hwirq);
  289. struct platform_device *pdev = priv->pdev;
  290. int ret;
  291. if (!bank)
  292. return -EINVAL;
  293. dev_dbg(&pdev->dev, "Mapping irq %d for gpio line %d (bank %d)\n",
  294. irq, (int)hwirq, bank->id);
  295. ret = irq_set_chip_data(irq, &bank->gc);
  296. if (ret < 0)
  297. return ret;
  298. irq_set_lockdep_class(irq, &brcmstb_gpio_irq_lock_class,
  299. &brcmstb_gpio_irq_request_class);
  300. irq_set_chip_and_handler(irq, &priv->irq_chip, handle_level_irq);
  301. irq_set_noprobe(irq);
  302. return 0;
  303. }
  304. static void brcmstb_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
  305. {
  306. irq_set_chip_and_handler(irq, NULL, NULL);
  307. irq_set_chip_data(irq, NULL);
  308. }
  309. static const struct irq_domain_ops brcmstb_gpio_irq_domain_ops = {
  310. .map = brcmstb_gpio_irq_map,
  311. .unmap = brcmstb_gpio_irq_unmap,
  312. .xlate = irq_domain_xlate_twocell,
  313. };
  314. /* Make sure that the number of banks matches up between properties */
  315. static int brcmstb_gpio_sanity_check_banks(struct device *dev,
  316. struct device_node *np, struct resource *res)
  317. {
  318. int res_num_banks = resource_size(res) / GIO_BANK_SIZE;
  319. int num_banks =
  320. of_property_count_u32_elems(np, "brcm,gpio-bank-widths");
  321. if (res_num_banks != num_banks) {
  322. dev_err(dev, "Mismatch in banks: res had %d, bank-widths had %d\n",
  323. res_num_banks, num_banks);
  324. return -EINVAL;
  325. } else {
  326. return 0;
  327. }
  328. }
  329. static int brcmstb_gpio_remove(struct platform_device *pdev)
  330. {
  331. struct brcmstb_gpio_priv *priv = platform_get_drvdata(pdev);
  332. struct brcmstb_gpio_bank *bank;
  333. int offset, ret = 0, virq;
  334. if (!priv) {
  335. dev_err(&pdev->dev, "called %s without drvdata!\n", __func__);
  336. return -EFAULT;
  337. }
  338. if (priv->parent_irq > 0)
  339. irq_set_chained_handler_and_data(priv->parent_irq, NULL, NULL);
  340. /* Remove all IRQ mappings and delete the domain */
  341. if (priv->irq_domain) {
  342. for (offset = 0; offset < priv->num_gpios; offset++) {
  343. virq = irq_find_mapping(priv->irq_domain, offset);
  344. irq_dispose_mapping(virq);
  345. }
  346. irq_domain_remove(priv->irq_domain);
  347. }
  348. /*
  349. * You can lose return values below, but we report all errors, and it's
  350. * more important to actually perform all of the steps.
  351. */
  352. list_for_each_entry(bank, &priv->bank_list, node)
  353. gpiochip_remove(&bank->gc);
  354. return ret;
  355. }
  356. static int brcmstb_gpio_of_xlate(struct gpio_chip *gc,
  357. const struct of_phandle_args *gpiospec, u32 *flags)
  358. {
  359. struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
  360. struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
  361. int offset;
  362. if (gc->of_gpio_n_cells != 2) {
  363. WARN_ON(1);
  364. return -EINVAL;
  365. }
  366. if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
  367. return -EINVAL;
  368. offset = gpiospec->args[0] - (gc->base - priv->gpio_base);
  369. if (offset >= gc->ngpio || offset < 0)
  370. return -EINVAL;
  371. if (unlikely(offset >= bank->width)) {
  372. dev_warn_ratelimited(&priv->pdev->dev,
  373. "Received request for invalid GPIO offset %d\n",
  374. gpiospec->args[0]);
  375. }
  376. if (flags)
  377. *flags = gpiospec->args[1];
  378. return offset;
  379. }
  380. /* priv->parent_irq and priv->num_gpios must be set before calling */
  381. static int brcmstb_gpio_irq_setup(struct platform_device *pdev,
  382. struct brcmstb_gpio_priv *priv)
  383. {
  384. struct device *dev = &pdev->dev;
  385. struct device_node *np = dev->of_node;
  386. int err;
  387. priv->irq_domain =
  388. irq_domain_add_linear(np, priv->num_gpios,
  389. &brcmstb_gpio_irq_domain_ops,
  390. priv);
  391. if (!priv->irq_domain) {
  392. dev_err(dev, "Couldn't allocate IRQ domain\n");
  393. return -ENXIO;
  394. }
  395. if (of_property_read_bool(np, "wakeup-source")) {
  396. priv->parent_wake_irq = platform_get_irq(pdev, 1);
  397. if (priv->parent_wake_irq < 0) {
  398. priv->parent_wake_irq = 0;
  399. dev_warn(dev,
  400. "Couldn't get wake IRQ - GPIOs will not be able to wake from sleep");
  401. } else {
  402. /*
  403. * Set wakeup capability so we can process boot-time
  404. * "wakeups" (e.g., from S5 cold boot)
  405. */
  406. device_set_wakeup_capable(dev, true);
  407. device_wakeup_enable(dev);
  408. err = devm_request_irq(dev, priv->parent_wake_irq,
  409. brcmstb_gpio_wake_irq_handler,
  410. IRQF_SHARED,
  411. "brcmstb-gpio-wake", priv);
  412. if (err < 0) {
  413. dev_err(dev, "Couldn't request wake IRQ");
  414. goto out_free_domain;
  415. }
  416. }
  417. }
  418. priv->irq_chip.name = dev_name(dev);
  419. priv->irq_chip.irq_disable = brcmstb_gpio_irq_mask;
  420. priv->irq_chip.irq_mask = brcmstb_gpio_irq_mask;
  421. priv->irq_chip.irq_unmask = brcmstb_gpio_irq_unmask;
  422. priv->irq_chip.irq_ack = brcmstb_gpio_irq_ack;
  423. priv->irq_chip.irq_set_type = brcmstb_gpio_irq_set_type;
  424. if (priv->parent_wake_irq)
  425. priv->irq_chip.irq_set_wake = brcmstb_gpio_irq_set_wake;
  426. irq_set_chained_handler_and_data(priv->parent_irq,
  427. brcmstb_gpio_irq_handler, priv);
  428. irq_set_status_flags(priv->parent_irq, IRQ_DISABLE_UNLAZY);
  429. return 0;
  430. out_free_domain:
  431. irq_domain_remove(priv->irq_domain);
  432. return err;
  433. }
  434. static void brcmstb_gpio_bank_save(struct brcmstb_gpio_priv *priv,
  435. struct brcmstb_gpio_bank *bank)
  436. {
  437. struct gpio_chip *gc = &bank->gc;
  438. unsigned int i;
  439. for (i = 0; i < GIO_REG_STAT; i++)
  440. bank->saved_regs[i] = gc->read_reg(priv->reg_base +
  441. GIO_BANK_OFF(bank->id, i));
  442. }
  443. static void brcmstb_gpio_quiesce(struct device *dev, bool save)
  444. {
  445. struct brcmstb_gpio_priv *priv = dev_get_drvdata(dev);
  446. struct brcmstb_gpio_bank *bank;
  447. struct gpio_chip *gc;
  448. u32 imask;
  449. /* disable non-wake interrupt */
  450. if (priv->parent_irq >= 0)
  451. disable_irq(priv->parent_irq);
  452. list_for_each_entry(bank, &priv->bank_list, node) {
  453. gc = &bank->gc;
  454. if (save)
  455. brcmstb_gpio_bank_save(priv, bank);
  456. /* Unmask GPIOs which have been flagged as wake-up sources */
  457. if (priv->parent_wake_irq)
  458. imask = bank->wake_active;
  459. else
  460. imask = 0;
  461. gc->write_reg(priv->reg_base + GIO_MASK(bank->id),
  462. imask);
  463. }
  464. }
  465. static void brcmstb_gpio_shutdown(struct platform_device *pdev)
  466. {
  467. /* Enable GPIO for S5 cold boot */
  468. brcmstb_gpio_quiesce(&pdev->dev, false);
  469. }
  470. #ifdef CONFIG_PM_SLEEP
  471. static void brcmstb_gpio_bank_restore(struct brcmstb_gpio_priv *priv,
  472. struct brcmstb_gpio_bank *bank)
  473. {
  474. struct gpio_chip *gc = &bank->gc;
  475. unsigned int i;
  476. for (i = 0; i < GIO_REG_STAT; i++)
  477. gc->write_reg(priv->reg_base + GIO_BANK_OFF(bank->id, i),
  478. bank->saved_regs[i]);
  479. }
  480. static int brcmstb_gpio_suspend(struct device *dev)
  481. {
  482. brcmstb_gpio_quiesce(dev, true);
  483. return 0;
  484. }
  485. static int brcmstb_gpio_resume(struct device *dev)
  486. {
  487. struct brcmstb_gpio_priv *priv = dev_get_drvdata(dev);
  488. struct brcmstb_gpio_bank *bank;
  489. bool need_wakeup_event = false;
  490. list_for_each_entry(bank, &priv->bank_list, node) {
  491. need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank);
  492. brcmstb_gpio_bank_restore(priv, bank);
  493. }
  494. if (priv->parent_wake_irq && need_wakeup_event)
  495. pm_wakeup_event(dev, 0);
  496. /* enable non-wake interrupt */
  497. if (priv->parent_irq >= 0)
  498. enable_irq(priv->parent_irq);
  499. return 0;
  500. }
  501. #else
  502. #define brcmstb_gpio_suspend NULL
  503. #define brcmstb_gpio_resume NULL
  504. #endif /* CONFIG_PM_SLEEP */
  505. static const struct dev_pm_ops brcmstb_gpio_pm_ops = {
  506. .suspend_noirq = brcmstb_gpio_suspend,
  507. .resume_noirq = brcmstb_gpio_resume,
  508. };
  509. static void brcmstb_gpio_set_names(struct device *dev,
  510. struct brcmstb_gpio_bank *bank)
  511. {
  512. struct device_node *np = dev->of_node;
  513. const char **names;
  514. int nstrings, base;
  515. unsigned int i;
  516. base = bank->id * MAX_GPIO_PER_BANK;
  517. nstrings = of_property_count_strings(np, "gpio-line-names");
  518. if (nstrings <= base)
  519. /* Line names not present */
  520. return;
  521. names = devm_kcalloc(dev, MAX_GPIO_PER_BANK, sizeof(*names),
  522. GFP_KERNEL);
  523. if (!names)
  524. return;
  525. /*
  526. * Make sure to not index beyond the end of the number of descriptors
  527. * of the GPIO device.
  528. */
  529. for (i = 0; i < bank->width; i++) {
  530. const char *name;
  531. int ret;
  532. ret = of_property_read_string_index(np, "gpio-line-names",
  533. base + i, &name);
  534. if (ret) {
  535. if (ret != -ENODATA)
  536. dev_err(dev, "unable to name line %d: %d\n",
  537. base + i, ret);
  538. break;
  539. }
  540. if (*name)
  541. names[i] = name;
  542. }
  543. bank->gc.names = names;
  544. }
  545. static int brcmstb_gpio_probe(struct platform_device *pdev)
  546. {
  547. struct device *dev = &pdev->dev;
  548. struct device_node *np = dev->of_node;
  549. void __iomem *reg_base;
  550. struct brcmstb_gpio_priv *priv;
  551. struct resource *res;
  552. struct property *prop;
  553. const __be32 *p;
  554. u32 bank_width;
  555. int num_banks = 0;
  556. int err;
  557. static int gpio_base;
  558. unsigned long flags = 0;
  559. bool need_wakeup_event = false;
  560. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  561. if (!priv)
  562. return -ENOMEM;
  563. platform_set_drvdata(pdev, priv);
  564. INIT_LIST_HEAD(&priv->bank_list);
  565. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  566. reg_base = devm_ioremap_resource(dev, res);
  567. if (IS_ERR(reg_base))
  568. return PTR_ERR(reg_base);
  569. priv->gpio_base = gpio_base;
  570. priv->reg_base = reg_base;
  571. priv->pdev = pdev;
  572. if (of_property_read_bool(np, "interrupt-controller")) {
  573. priv->parent_irq = platform_get_irq(pdev, 0);
  574. if (priv->parent_irq <= 0)
  575. return -ENOENT;
  576. } else {
  577. priv->parent_irq = -ENOENT;
  578. }
  579. if (brcmstb_gpio_sanity_check_banks(dev, np, res))
  580. return -EINVAL;
  581. /*
  582. * MIPS endianness is configured by boot strap, which also reverses all
  583. * bus endianness (i.e., big-endian CPU + big endian bus ==> native
  584. * endian I/O).
  585. *
  586. * Other architectures (e.g., ARM) either do not support big endian, or
  587. * else leave I/O in little endian mode.
  588. */
  589. #if defined(CONFIG_MIPS) && defined(__BIG_ENDIAN)
  590. flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER;
  591. #endif
  592. of_property_for_each_u32(np, "brcm,gpio-bank-widths", prop, p,
  593. bank_width) {
  594. struct brcmstb_gpio_bank *bank;
  595. struct gpio_chip *gc;
  596. /*
  597. * If bank_width is 0, then there is an empty bank in the
  598. * register block. Special handling for this case.
  599. */
  600. if (bank_width == 0) {
  601. dev_dbg(dev, "Width 0 found: Empty bank @ %d\n",
  602. num_banks);
  603. num_banks++;
  604. gpio_base += MAX_GPIO_PER_BANK;
  605. continue;
  606. }
  607. bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
  608. if (!bank) {
  609. err = -ENOMEM;
  610. goto fail;
  611. }
  612. bank->parent_priv = priv;
  613. bank->id = num_banks;
  614. if (bank_width <= 0 || bank_width > MAX_GPIO_PER_BANK) {
  615. dev_err(dev, "Invalid bank width %d\n", bank_width);
  616. err = -EINVAL;
  617. goto fail;
  618. } else {
  619. bank->width = bank_width;
  620. }
  621. /*
  622. * Regs are 4 bytes wide, have data reg, no set/clear regs,
  623. * and direction bits have 0 = output and 1 = input
  624. */
  625. gc = &bank->gc;
  626. err = bgpio_init(gc, dev, 4,
  627. reg_base + GIO_DATA(bank->id),
  628. NULL, NULL, NULL,
  629. reg_base + GIO_IODIR(bank->id), flags);
  630. if (err) {
  631. dev_err(dev, "bgpio_init() failed\n");
  632. goto fail;
  633. }
  634. gc->of_node = np;
  635. gc->owner = THIS_MODULE;
  636. gc->label = devm_kasprintf(dev, GFP_KERNEL, "%pOF", dev->of_node);
  637. if (!gc->label) {
  638. err = -ENOMEM;
  639. goto fail;
  640. }
  641. gc->base = gpio_base;
  642. gc->of_gpio_n_cells = 2;
  643. gc->of_xlate = brcmstb_gpio_of_xlate;
  644. /* not all ngpio lines are valid, will use bank width later */
  645. gc->ngpio = MAX_GPIO_PER_BANK;
  646. if (priv->parent_irq > 0)
  647. gc->to_irq = brcmstb_gpio_to_irq;
  648. /*
  649. * Mask all interrupts by default, since wakeup interrupts may
  650. * be retained from S5 cold boot
  651. */
  652. need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank);
  653. gc->write_reg(reg_base + GIO_MASK(bank->id), 0);
  654. brcmstb_gpio_set_names(dev, bank);
  655. err = gpiochip_add_data(gc, bank);
  656. if (err) {
  657. dev_err(dev, "Could not add gpiochip for bank %d\n",
  658. bank->id);
  659. goto fail;
  660. }
  661. gpio_base += gc->ngpio;
  662. dev_dbg(dev, "bank=%d, base=%d, ngpio=%d, width=%d\n", bank->id,
  663. gc->base, gc->ngpio, bank->width);
  664. /* Everything looks good, so add bank to list */
  665. list_add(&bank->node, &priv->bank_list);
  666. num_banks++;
  667. }
  668. priv->num_gpios = gpio_base - priv->gpio_base;
  669. if (priv->parent_irq > 0) {
  670. err = brcmstb_gpio_irq_setup(pdev, priv);
  671. if (err)
  672. goto fail;
  673. }
  674. if (priv->parent_wake_irq && need_wakeup_event)
  675. pm_wakeup_event(dev, 0);
  676. return 0;
  677. fail:
  678. (void) brcmstb_gpio_remove(pdev);
  679. return err;
  680. }
  681. static const struct of_device_id brcmstb_gpio_of_match[] = {
  682. { .compatible = "brcm,brcmstb-gpio" },
  683. {},
  684. };
  685. MODULE_DEVICE_TABLE(of, brcmstb_gpio_of_match);
  686. static struct platform_driver brcmstb_gpio_driver = {
  687. .driver = {
  688. .name = "brcmstb-gpio",
  689. .of_match_table = brcmstb_gpio_of_match,
  690. .pm = &brcmstb_gpio_pm_ops,
  691. },
  692. .probe = brcmstb_gpio_probe,
  693. .remove = brcmstb_gpio_remove,
  694. .shutdown = brcmstb_gpio_shutdown,
  695. };
  696. module_platform_driver(brcmstb_gpio_driver);
  697. MODULE_AUTHOR("Gregory Fong");
  698. MODULE_DESCRIPTION("Driver for Broadcom BRCMSTB SoC UPG GPIO");
  699. MODULE_LICENSE("GPL v2");