gpio-bcm-kona.c 18 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674
  1. /*
  2. * Broadcom Kona GPIO Driver
  3. *
  4. * Author: Broadcom Corporation <bcm-kernel-feedback-list@broadcom.com>
  5. * Copyright (C) 2012-2014 Broadcom Corporation
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation version 2.
  10. *
  11. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12. * kind, whether express or implied; without even the implied warranty
  13. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. */
  16. #include <linux/bitops.h>
  17. #include <linux/err.h>
  18. #include <linux/io.h>
  19. #include <linux/gpio/driver.h>
  20. #include <linux/of_device.h>
  21. #include <linux/init.h>
  22. #include <linux/irqdomain.h>
  23. #include <linux/irqchip/chained_irq.h>
  24. #define BCM_GPIO_PASSWD 0x00a5a501
  25. #define GPIO_PER_BANK 32
  26. #define GPIO_MAX_BANK_NUM 8
  27. #define GPIO_BANK(gpio) ((gpio) >> 5)
  28. #define GPIO_BIT(gpio) ((gpio) & (GPIO_PER_BANK - 1))
  29. /* There is a GPIO control register for each GPIO */
  30. #define GPIO_CONTROL(gpio) (0x00000100 + ((gpio) << 2))
  31. /* The remaining registers are per GPIO bank */
  32. #define GPIO_OUT_STATUS(bank) (0x00000000 + ((bank) << 2))
  33. #define GPIO_IN_STATUS(bank) (0x00000020 + ((bank) << 2))
  34. #define GPIO_OUT_SET(bank) (0x00000040 + ((bank) << 2))
  35. #define GPIO_OUT_CLEAR(bank) (0x00000060 + ((bank) << 2))
  36. #define GPIO_INT_STATUS(bank) (0x00000080 + ((bank) << 2))
  37. #define GPIO_INT_MASK(bank) (0x000000a0 + ((bank) << 2))
  38. #define GPIO_INT_MSKCLR(bank) (0x000000c0 + ((bank) << 2))
  39. #define GPIO_PWD_STATUS(bank) (0x00000500 + ((bank) << 2))
  40. #define GPIO_GPPWR_OFFSET 0x00000520
  41. #define GPIO_GPCTR0_DBR_SHIFT 5
  42. #define GPIO_GPCTR0_DBR_MASK 0x000001e0
  43. #define GPIO_GPCTR0_ITR_SHIFT 3
  44. #define GPIO_GPCTR0_ITR_MASK 0x00000018
  45. #define GPIO_GPCTR0_ITR_CMD_RISING_EDGE 0x00000001
  46. #define GPIO_GPCTR0_ITR_CMD_FALLING_EDGE 0x00000002
  47. #define GPIO_GPCTR0_ITR_CMD_BOTH_EDGE 0x00000003
  48. #define GPIO_GPCTR0_IOTR_MASK 0x00000001
  49. #define GPIO_GPCTR0_IOTR_CMD_0UTPUT 0x00000000
  50. #define GPIO_GPCTR0_IOTR_CMD_INPUT 0x00000001
  51. #define GPIO_GPCTR0_DB_ENABLE_MASK 0x00000100
  52. #define LOCK_CODE 0xffffffff
  53. #define UNLOCK_CODE 0x00000000
  54. struct bcm_kona_gpio {
  55. void __iomem *reg_base;
  56. int num_bank;
  57. raw_spinlock_t lock;
  58. struct gpio_chip gpio_chip;
  59. struct irq_domain *irq_domain;
  60. struct bcm_kona_gpio_bank *banks;
  61. struct platform_device *pdev;
  62. };
  63. struct bcm_kona_gpio_bank {
  64. int id;
  65. int irq;
  66. /* Used in the interrupt handler */
  67. struct bcm_kona_gpio *kona_gpio;
  68. };
  69. static inline void bcm_kona_gpio_write_lock_regs(void __iomem *reg_base,
  70. int bank_id, u32 lockcode)
  71. {
  72. writel(BCM_GPIO_PASSWD, reg_base + GPIO_GPPWR_OFFSET);
  73. writel(lockcode, reg_base + GPIO_PWD_STATUS(bank_id));
  74. }
  75. static void bcm_kona_gpio_lock_gpio(struct bcm_kona_gpio *kona_gpio,
  76. unsigned gpio)
  77. {
  78. u32 val;
  79. unsigned long flags;
  80. int bank_id = GPIO_BANK(gpio);
  81. raw_spin_lock_irqsave(&kona_gpio->lock, flags);
  82. val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));
  83. val |= BIT(gpio);
  84. bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);
  85. raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
  86. }
  87. static void bcm_kona_gpio_unlock_gpio(struct bcm_kona_gpio *kona_gpio,
  88. unsigned gpio)
  89. {
  90. u32 val;
  91. unsigned long flags;
  92. int bank_id = GPIO_BANK(gpio);
  93. raw_spin_lock_irqsave(&kona_gpio->lock, flags);
  94. val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));
  95. val &= ~BIT(gpio);
  96. bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);
  97. raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
  98. }
  99. static int bcm_kona_gpio_get_dir(struct gpio_chip *chip, unsigned gpio)
  100. {
  101. struct bcm_kona_gpio *kona_gpio = gpiochip_get_data(chip);
  102. void __iomem *reg_base = kona_gpio->reg_base;
  103. u32 val;
  104. val = readl(reg_base + GPIO_CONTROL(gpio)) & GPIO_GPCTR0_IOTR_MASK;
  105. return val ? GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT;
  106. }
  107. static void bcm_kona_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
  108. {
  109. struct bcm_kona_gpio *kona_gpio;
  110. void __iomem *reg_base;
  111. int bank_id = GPIO_BANK(gpio);
  112. int bit = GPIO_BIT(gpio);
  113. u32 val, reg_offset;
  114. unsigned long flags;
  115. kona_gpio = gpiochip_get_data(chip);
  116. reg_base = kona_gpio->reg_base;
  117. raw_spin_lock_irqsave(&kona_gpio->lock, flags);
  118. /* this function only applies to output pin */
  119. if (bcm_kona_gpio_get_dir(chip, gpio) == GPIO_LINE_DIRECTION_IN)
  120. goto out;
  121. reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
  122. val = readl(reg_base + reg_offset);
  123. val |= BIT(bit);
  124. writel(val, reg_base + reg_offset);
  125. out:
  126. raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
  127. }
  128. static int bcm_kona_gpio_get(struct gpio_chip *chip, unsigned gpio)
  129. {
  130. struct bcm_kona_gpio *kona_gpio;
  131. void __iomem *reg_base;
  132. int bank_id = GPIO_BANK(gpio);
  133. int bit = GPIO_BIT(gpio);
  134. u32 val, reg_offset;
  135. unsigned long flags;
  136. kona_gpio = gpiochip_get_data(chip);
  137. reg_base = kona_gpio->reg_base;
  138. raw_spin_lock_irqsave(&kona_gpio->lock, flags);
  139. if (bcm_kona_gpio_get_dir(chip, gpio) == GPIO_LINE_DIRECTION_IN)
  140. reg_offset = GPIO_IN_STATUS(bank_id);
  141. else
  142. reg_offset = GPIO_OUT_STATUS(bank_id);
  143. /* read the GPIO bank status */
  144. val = readl(reg_base + reg_offset);
  145. raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
  146. /* return the specified bit status */
  147. return !!(val & BIT(bit));
  148. }
  149. static int bcm_kona_gpio_request(struct gpio_chip *chip, unsigned gpio)
  150. {
  151. struct bcm_kona_gpio *kona_gpio = gpiochip_get_data(chip);
  152. bcm_kona_gpio_unlock_gpio(kona_gpio, gpio);
  153. return 0;
  154. }
  155. static void bcm_kona_gpio_free(struct gpio_chip *chip, unsigned gpio)
  156. {
  157. struct bcm_kona_gpio *kona_gpio = gpiochip_get_data(chip);
  158. bcm_kona_gpio_lock_gpio(kona_gpio, gpio);
  159. }
  160. static int bcm_kona_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
  161. {
  162. struct bcm_kona_gpio *kona_gpio;
  163. void __iomem *reg_base;
  164. u32 val;
  165. unsigned long flags;
  166. kona_gpio = gpiochip_get_data(chip);
  167. reg_base = kona_gpio->reg_base;
  168. raw_spin_lock_irqsave(&kona_gpio->lock, flags);
  169. val = readl(reg_base + GPIO_CONTROL(gpio));
  170. val &= ~GPIO_GPCTR0_IOTR_MASK;
  171. val |= GPIO_GPCTR0_IOTR_CMD_INPUT;
  172. writel(val, reg_base + GPIO_CONTROL(gpio));
  173. raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
  174. return 0;
  175. }
  176. static int bcm_kona_gpio_direction_output(struct gpio_chip *chip,
  177. unsigned gpio, int value)
  178. {
  179. struct bcm_kona_gpio *kona_gpio;
  180. void __iomem *reg_base;
  181. int bank_id = GPIO_BANK(gpio);
  182. int bit = GPIO_BIT(gpio);
  183. u32 val, reg_offset;
  184. unsigned long flags;
  185. kona_gpio = gpiochip_get_data(chip);
  186. reg_base = kona_gpio->reg_base;
  187. raw_spin_lock_irqsave(&kona_gpio->lock, flags);
  188. val = readl(reg_base + GPIO_CONTROL(gpio));
  189. val &= ~GPIO_GPCTR0_IOTR_MASK;
  190. val |= GPIO_GPCTR0_IOTR_CMD_0UTPUT;
  191. writel(val, reg_base + GPIO_CONTROL(gpio));
  192. reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
  193. val = readl(reg_base + reg_offset);
  194. val |= BIT(bit);
  195. writel(val, reg_base + reg_offset);
  196. raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
  197. return 0;
  198. }
  199. static int bcm_kona_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
  200. {
  201. struct bcm_kona_gpio *kona_gpio;
  202. kona_gpio = gpiochip_get_data(chip);
  203. if (gpio >= kona_gpio->gpio_chip.ngpio)
  204. return -ENXIO;
  205. return irq_create_mapping(kona_gpio->irq_domain, gpio);
  206. }
  207. static int bcm_kona_gpio_set_debounce(struct gpio_chip *chip, unsigned gpio,
  208. unsigned debounce)
  209. {
  210. struct bcm_kona_gpio *kona_gpio;
  211. void __iomem *reg_base;
  212. u32 val, res;
  213. unsigned long flags;
  214. kona_gpio = gpiochip_get_data(chip);
  215. reg_base = kona_gpio->reg_base;
  216. /* debounce must be 1-128ms (or 0) */
  217. if ((debounce > 0 && debounce < 1000) || debounce > 128000) {
  218. dev_err(chip->parent, "Debounce value %u not in range\n",
  219. debounce);
  220. return -EINVAL;
  221. }
  222. /* calculate debounce bit value */
  223. if (debounce != 0) {
  224. /* Convert to ms */
  225. debounce /= 1000;
  226. /* find the MSB */
  227. res = fls(debounce) - 1;
  228. /* Check if MSB-1 is set (round up or down) */
  229. if (res > 0 && (debounce & BIT(res - 1)))
  230. res++;
  231. }
  232. /* spin lock for read-modify-write of the GPIO register */
  233. raw_spin_lock_irqsave(&kona_gpio->lock, flags);
  234. val = readl(reg_base + GPIO_CONTROL(gpio));
  235. val &= ~GPIO_GPCTR0_DBR_MASK;
  236. if (debounce == 0) {
  237. /* disable debounce */
  238. val &= ~GPIO_GPCTR0_DB_ENABLE_MASK;
  239. } else {
  240. val |= GPIO_GPCTR0_DB_ENABLE_MASK |
  241. (res << GPIO_GPCTR0_DBR_SHIFT);
  242. }
  243. writel(val, reg_base + GPIO_CONTROL(gpio));
  244. raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
  245. return 0;
  246. }
  247. static int bcm_kona_gpio_set_config(struct gpio_chip *chip, unsigned gpio,
  248. unsigned long config)
  249. {
  250. u32 debounce;
  251. if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
  252. return -ENOTSUPP;
  253. debounce = pinconf_to_config_argument(config);
  254. return bcm_kona_gpio_set_debounce(chip, gpio, debounce);
  255. }
  256. static const struct gpio_chip template_chip = {
  257. .label = "bcm-kona-gpio",
  258. .owner = THIS_MODULE,
  259. .request = bcm_kona_gpio_request,
  260. .free = bcm_kona_gpio_free,
  261. .get_direction = bcm_kona_gpio_get_dir,
  262. .direction_input = bcm_kona_gpio_direction_input,
  263. .get = bcm_kona_gpio_get,
  264. .direction_output = bcm_kona_gpio_direction_output,
  265. .set = bcm_kona_gpio_set,
  266. .set_config = bcm_kona_gpio_set_config,
  267. .to_irq = bcm_kona_gpio_to_irq,
  268. .base = 0,
  269. };
  270. static void bcm_kona_gpio_irq_ack(struct irq_data *d)
  271. {
  272. struct bcm_kona_gpio *kona_gpio;
  273. void __iomem *reg_base;
  274. unsigned gpio = d->hwirq;
  275. int bank_id = GPIO_BANK(gpio);
  276. int bit = GPIO_BIT(gpio);
  277. u32 val;
  278. unsigned long flags;
  279. kona_gpio = irq_data_get_irq_chip_data(d);
  280. reg_base = kona_gpio->reg_base;
  281. raw_spin_lock_irqsave(&kona_gpio->lock, flags);
  282. val = readl(reg_base + GPIO_INT_STATUS(bank_id));
  283. val |= BIT(bit);
  284. writel(val, reg_base + GPIO_INT_STATUS(bank_id));
  285. raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
  286. }
  287. static void bcm_kona_gpio_irq_mask(struct irq_data *d)
  288. {
  289. struct bcm_kona_gpio *kona_gpio;
  290. void __iomem *reg_base;
  291. unsigned gpio = d->hwirq;
  292. int bank_id = GPIO_BANK(gpio);
  293. int bit = GPIO_BIT(gpio);
  294. u32 val;
  295. unsigned long flags;
  296. kona_gpio = irq_data_get_irq_chip_data(d);
  297. reg_base = kona_gpio->reg_base;
  298. raw_spin_lock_irqsave(&kona_gpio->lock, flags);
  299. val = readl(reg_base + GPIO_INT_MASK(bank_id));
  300. val |= BIT(bit);
  301. writel(val, reg_base + GPIO_INT_MASK(bank_id));
  302. gpiochip_disable_irq(&kona_gpio->gpio_chip, gpio);
  303. raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
  304. }
  305. static void bcm_kona_gpio_irq_unmask(struct irq_data *d)
  306. {
  307. struct bcm_kona_gpio *kona_gpio;
  308. void __iomem *reg_base;
  309. unsigned gpio = d->hwirq;
  310. int bank_id = GPIO_BANK(gpio);
  311. int bit = GPIO_BIT(gpio);
  312. u32 val;
  313. unsigned long flags;
  314. kona_gpio = irq_data_get_irq_chip_data(d);
  315. reg_base = kona_gpio->reg_base;
  316. raw_spin_lock_irqsave(&kona_gpio->lock, flags);
  317. val = readl(reg_base + GPIO_INT_MSKCLR(bank_id));
  318. val |= BIT(bit);
  319. writel(val, reg_base + GPIO_INT_MSKCLR(bank_id));
  320. gpiochip_enable_irq(&kona_gpio->gpio_chip, gpio);
  321. raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
  322. }
  323. static int bcm_kona_gpio_irq_set_type(struct irq_data *d, unsigned int type)
  324. {
  325. struct bcm_kona_gpio *kona_gpio;
  326. void __iomem *reg_base;
  327. unsigned gpio = d->hwirq;
  328. u32 lvl_type;
  329. u32 val;
  330. unsigned long flags;
  331. kona_gpio = irq_data_get_irq_chip_data(d);
  332. reg_base = kona_gpio->reg_base;
  333. switch (type & IRQ_TYPE_SENSE_MASK) {
  334. case IRQ_TYPE_EDGE_RISING:
  335. lvl_type = GPIO_GPCTR0_ITR_CMD_RISING_EDGE;
  336. break;
  337. case IRQ_TYPE_EDGE_FALLING:
  338. lvl_type = GPIO_GPCTR0_ITR_CMD_FALLING_EDGE;
  339. break;
  340. case IRQ_TYPE_EDGE_BOTH:
  341. lvl_type = GPIO_GPCTR0_ITR_CMD_BOTH_EDGE;
  342. break;
  343. case IRQ_TYPE_LEVEL_HIGH:
  344. case IRQ_TYPE_LEVEL_LOW:
  345. /* BCM GPIO doesn't support level triggering */
  346. default:
  347. dev_err(kona_gpio->gpio_chip.parent,
  348. "Invalid BCM GPIO irq type 0x%x\n", type);
  349. return -EINVAL;
  350. }
  351. raw_spin_lock_irqsave(&kona_gpio->lock, flags);
  352. val = readl(reg_base + GPIO_CONTROL(gpio));
  353. val &= ~GPIO_GPCTR0_ITR_MASK;
  354. val |= lvl_type << GPIO_GPCTR0_ITR_SHIFT;
  355. writel(val, reg_base + GPIO_CONTROL(gpio));
  356. raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
  357. return 0;
  358. }
  359. static void bcm_kona_gpio_irq_handler(struct irq_desc *desc)
  360. {
  361. void __iomem *reg_base;
  362. int bit, bank_id;
  363. unsigned long sta;
  364. struct bcm_kona_gpio_bank *bank = irq_desc_get_handler_data(desc);
  365. struct irq_chip *chip = irq_desc_get_chip(desc);
  366. chained_irq_enter(chip, desc);
  367. /*
  368. * For bank interrupts, we can't use chip_data to store the kona_gpio
  369. * pointer, since GIC needs it for its own purposes. Therefore, we get
  370. * our pointer from the bank structure.
  371. */
  372. reg_base = bank->kona_gpio->reg_base;
  373. bank_id = bank->id;
  374. while ((sta = readl(reg_base + GPIO_INT_STATUS(bank_id)) &
  375. (~(readl(reg_base + GPIO_INT_MASK(bank_id)))))) {
  376. for_each_set_bit(bit, &sta, 32) {
  377. int hwirq = GPIO_PER_BANK * bank_id + bit;
  378. int child_irq =
  379. irq_find_mapping(bank->kona_gpio->irq_domain,
  380. hwirq);
  381. /*
  382. * Clear interrupt before handler is called so we don't
  383. * miss any interrupt occurred during executing them.
  384. */
  385. writel(readl(reg_base + GPIO_INT_STATUS(bank_id)) |
  386. BIT(bit), reg_base + GPIO_INT_STATUS(bank_id));
  387. /* Invoke interrupt handler */
  388. generic_handle_irq(child_irq);
  389. }
  390. }
  391. chained_irq_exit(chip, desc);
  392. }
  393. static int bcm_kona_gpio_irq_reqres(struct irq_data *d)
  394. {
  395. struct bcm_kona_gpio *kona_gpio = irq_data_get_irq_chip_data(d);
  396. return gpiochip_reqres_irq(&kona_gpio->gpio_chip, d->hwirq);
  397. }
  398. static void bcm_kona_gpio_irq_relres(struct irq_data *d)
  399. {
  400. struct bcm_kona_gpio *kona_gpio = irq_data_get_irq_chip_data(d);
  401. gpiochip_relres_irq(&kona_gpio->gpio_chip, d->hwirq);
  402. }
  403. static struct irq_chip bcm_gpio_irq_chip = {
  404. .name = "bcm-kona-gpio",
  405. .irq_ack = bcm_kona_gpio_irq_ack,
  406. .irq_mask = bcm_kona_gpio_irq_mask,
  407. .irq_unmask = bcm_kona_gpio_irq_unmask,
  408. .irq_set_type = bcm_kona_gpio_irq_set_type,
  409. .irq_request_resources = bcm_kona_gpio_irq_reqres,
  410. .irq_release_resources = bcm_kona_gpio_irq_relres,
  411. };
  412. static struct of_device_id const bcm_kona_gpio_of_match[] = {
  413. { .compatible = "brcm,kona-gpio" },
  414. {}
  415. };
  416. /*
  417. * This lock class tells lockdep that GPIO irqs are in a different
  418. * category than their parents, so it won't report false recursion.
  419. */
  420. static struct lock_class_key gpio_lock_class;
  421. static struct lock_class_key gpio_request_class;
  422. static int bcm_kona_gpio_irq_map(struct irq_domain *d, unsigned int irq,
  423. irq_hw_number_t hwirq)
  424. {
  425. int ret;
  426. ret = irq_set_chip_data(irq, d->host_data);
  427. if (ret < 0)
  428. return ret;
  429. irq_set_lockdep_class(irq, &gpio_lock_class, &gpio_request_class);
  430. irq_set_chip_and_handler(irq, &bcm_gpio_irq_chip, handle_simple_irq);
  431. irq_set_noprobe(irq);
  432. return 0;
  433. }
  434. static void bcm_kona_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
  435. {
  436. irq_set_chip_and_handler(irq, NULL, NULL);
  437. irq_set_chip_data(irq, NULL);
  438. }
  439. static const struct irq_domain_ops bcm_kona_irq_ops = {
  440. .map = bcm_kona_gpio_irq_map,
  441. .unmap = bcm_kona_gpio_irq_unmap,
  442. .xlate = irq_domain_xlate_twocell,
  443. };
  444. static void bcm_kona_gpio_reset(struct bcm_kona_gpio *kona_gpio)
  445. {
  446. void __iomem *reg_base;
  447. int i;
  448. reg_base = kona_gpio->reg_base;
  449. /* disable interrupts and clear status */
  450. for (i = 0; i < kona_gpio->num_bank; i++) {
  451. /* Unlock the entire bank first */
  452. bcm_kona_gpio_write_lock_regs(reg_base, i, UNLOCK_CODE);
  453. writel(0xffffffff, reg_base + GPIO_INT_MASK(i));
  454. writel(0xffffffff, reg_base + GPIO_INT_STATUS(i));
  455. /* Now re-lock the bank */
  456. bcm_kona_gpio_write_lock_regs(reg_base, i, LOCK_CODE);
  457. }
  458. }
  459. static int bcm_kona_gpio_probe(struct platform_device *pdev)
  460. {
  461. struct device *dev = &pdev->dev;
  462. const struct of_device_id *match;
  463. struct bcm_kona_gpio_bank *bank;
  464. struct bcm_kona_gpio *kona_gpio;
  465. struct gpio_chip *chip;
  466. int ret;
  467. int i;
  468. match = of_match_device(bcm_kona_gpio_of_match, dev);
  469. if (!match) {
  470. dev_err(dev, "Failed to find gpio controller\n");
  471. return -ENODEV;
  472. }
  473. kona_gpio = devm_kzalloc(dev, sizeof(*kona_gpio), GFP_KERNEL);
  474. if (!kona_gpio)
  475. return -ENOMEM;
  476. kona_gpio->gpio_chip = template_chip;
  477. chip = &kona_gpio->gpio_chip;
  478. ret = platform_irq_count(pdev);
  479. if (!ret) {
  480. dev_err(dev, "Couldn't determine # GPIO banks\n");
  481. return -ENOENT;
  482. } else if (ret < 0) {
  483. return dev_err_probe(dev, ret, "Couldn't determine GPIO banks\n");
  484. }
  485. kona_gpio->num_bank = ret;
  486. if (kona_gpio->num_bank > GPIO_MAX_BANK_NUM) {
  487. dev_err(dev, "Too many GPIO banks configured (max=%d)\n",
  488. GPIO_MAX_BANK_NUM);
  489. return -ENXIO;
  490. }
  491. kona_gpio->banks = devm_kcalloc(dev,
  492. kona_gpio->num_bank,
  493. sizeof(*kona_gpio->banks),
  494. GFP_KERNEL);
  495. if (!kona_gpio->banks)
  496. return -ENOMEM;
  497. kona_gpio->pdev = pdev;
  498. platform_set_drvdata(pdev, kona_gpio);
  499. chip->of_node = dev->of_node;
  500. chip->ngpio = kona_gpio->num_bank * GPIO_PER_BANK;
  501. kona_gpio->irq_domain = irq_domain_add_linear(dev->of_node,
  502. chip->ngpio,
  503. &bcm_kona_irq_ops,
  504. kona_gpio);
  505. if (!kona_gpio->irq_domain) {
  506. dev_err(dev, "Couldn't allocate IRQ domain\n");
  507. return -ENXIO;
  508. }
  509. kona_gpio->reg_base = devm_platform_ioremap_resource(pdev, 0);
  510. if (IS_ERR(kona_gpio->reg_base)) {
  511. ret = PTR_ERR(kona_gpio->reg_base);
  512. goto err_irq_domain;
  513. }
  514. for (i = 0; i < kona_gpio->num_bank; i++) {
  515. bank = &kona_gpio->banks[i];
  516. bank->id = i;
  517. bank->irq = platform_get_irq(pdev, i);
  518. bank->kona_gpio = kona_gpio;
  519. if (bank->irq < 0) {
  520. dev_err(dev, "Couldn't get IRQ for bank %d", i);
  521. ret = -ENOENT;
  522. goto err_irq_domain;
  523. }
  524. }
  525. dev_info(&pdev->dev, "Setting up Kona GPIO\n");
  526. bcm_kona_gpio_reset(kona_gpio);
  527. ret = devm_gpiochip_add_data(dev, chip, kona_gpio);
  528. if (ret < 0) {
  529. dev_err(dev, "Couldn't add GPIO chip -- %d\n", ret);
  530. goto err_irq_domain;
  531. }
  532. for (i = 0; i < kona_gpio->num_bank; i++) {
  533. bank = &kona_gpio->banks[i];
  534. irq_set_chained_handler_and_data(bank->irq,
  535. bcm_kona_gpio_irq_handler,
  536. bank);
  537. }
  538. raw_spin_lock_init(&kona_gpio->lock);
  539. return 0;
  540. err_irq_domain:
  541. irq_domain_remove(kona_gpio->irq_domain);
  542. return ret;
  543. }
  544. static struct platform_driver bcm_kona_gpio_driver = {
  545. .driver = {
  546. .name = "bcm-kona-gpio",
  547. .of_match_table = bcm_kona_gpio_of_match,
  548. },
  549. .probe = bcm_kona_gpio_probe,
  550. };
  551. builtin_platform_driver(bcm_kona_gpio_driver);