gpio-ath79.c 8.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Atheros AR71XX/AR724X/AR913X GPIO API support
  4. *
  5. * Copyright (C) 2015 Alban Bedel <albeu@free.fr>
  6. * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
  7. * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
  8. * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  9. */
  10. #include <linux/gpio/driver.h>
  11. #include <linux/platform_data/gpio-ath79.h>
  12. #include <linux/of_device.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/module.h>
  15. #include <linux/irq.h>
  16. #define AR71XX_GPIO_REG_OE 0x00
  17. #define AR71XX_GPIO_REG_IN 0x04
  18. #define AR71XX_GPIO_REG_SET 0x0c
  19. #define AR71XX_GPIO_REG_CLEAR 0x10
  20. #define AR71XX_GPIO_REG_INT_ENABLE 0x14
  21. #define AR71XX_GPIO_REG_INT_TYPE 0x18
  22. #define AR71XX_GPIO_REG_INT_POLARITY 0x1c
  23. #define AR71XX_GPIO_REG_INT_PENDING 0x20
  24. #define AR71XX_GPIO_REG_INT_MASK 0x24
  25. struct ath79_gpio_ctrl {
  26. struct gpio_chip gc;
  27. void __iomem *base;
  28. raw_spinlock_t lock;
  29. unsigned long both_edges;
  30. };
  31. static struct ath79_gpio_ctrl *irq_data_to_ath79_gpio(struct irq_data *data)
  32. {
  33. struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
  34. return container_of(gc, struct ath79_gpio_ctrl, gc);
  35. }
  36. static u32 ath79_gpio_read(struct ath79_gpio_ctrl *ctrl, unsigned reg)
  37. {
  38. return readl(ctrl->base + reg);
  39. }
  40. static void ath79_gpio_write(struct ath79_gpio_ctrl *ctrl,
  41. unsigned reg, u32 val)
  42. {
  43. writel(val, ctrl->base + reg);
  44. }
  45. static bool ath79_gpio_update_bits(
  46. struct ath79_gpio_ctrl *ctrl, unsigned reg, u32 mask, u32 bits)
  47. {
  48. u32 old_val, new_val;
  49. old_val = ath79_gpio_read(ctrl, reg);
  50. new_val = (old_val & ~mask) | (bits & mask);
  51. if (new_val != old_val)
  52. ath79_gpio_write(ctrl, reg, new_val);
  53. return new_val != old_val;
  54. }
  55. static void ath79_gpio_irq_unmask(struct irq_data *data)
  56. {
  57. struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
  58. u32 mask = BIT(irqd_to_hwirq(data));
  59. unsigned long flags;
  60. raw_spin_lock_irqsave(&ctrl->lock, flags);
  61. ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask);
  62. raw_spin_unlock_irqrestore(&ctrl->lock, flags);
  63. }
  64. static void ath79_gpio_irq_mask(struct irq_data *data)
  65. {
  66. struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
  67. u32 mask = BIT(irqd_to_hwirq(data));
  68. unsigned long flags;
  69. raw_spin_lock_irqsave(&ctrl->lock, flags);
  70. ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0);
  71. raw_spin_unlock_irqrestore(&ctrl->lock, flags);
  72. }
  73. static void ath79_gpio_irq_enable(struct irq_data *data)
  74. {
  75. struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
  76. u32 mask = BIT(irqd_to_hwirq(data));
  77. unsigned long flags;
  78. raw_spin_lock_irqsave(&ctrl->lock, flags);
  79. ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask);
  80. ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask);
  81. raw_spin_unlock_irqrestore(&ctrl->lock, flags);
  82. }
  83. static void ath79_gpio_irq_disable(struct irq_data *data)
  84. {
  85. struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
  86. u32 mask = BIT(irqd_to_hwirq(data));
  87. unsigned long flags;
  88. raw_spin_lock_irqsave(&ctrl->lock, flags);
  89. ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0);
  90. ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, 0);
  91. raw_spin_unlock_irqrestore(&ctrl->lock, flags);
  92. }
  93. static int ath79_gpio_irq_set_type(struct irq_data *data,
  94. unsigned int flow_type)
  95. {
  96. struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
  97. u32 mask = BIT(irqd_to_hwirq(data));
  98. u32 type = 0, polarity = 0;
  99. unsigned long flags;
  100. bool disabled;
  101. switch (flow_type) {
  102. case IRQ_TYPE_EDGE_RISING:
  103. polarity |= mask;
  104. case IRQ_TYPE_EDGE_FALLING:
  105. case IRQ_TYPE_EDGE_BOTH:
  106. break;
  107. case IRQ_TYPE_LEVEL_HIGH:
  108. polarity |= mask;
  109. fallthrough;
  110. case IRQ_TYPE_LEVEL_LOW:
  111. type |= mask;
  112. break;
  113. default:
  114. return -EINVAL;
  115. }
  116. raw_spin_lock_irqsave(&ctrl->lock, flags);
  117. if (flow_type == IRQ_TYPE_EDGE_BOTH) {
  118. ctrl->both_edges |= mask;
  119. polarity = ~ath79_gpio_read(ctrl, AR71XX_GPIO_REG_IN);
  120. } else {
  121. ctrl->both_edges &= ~mask;
  122. }
  123. /* As the IRQ configuration can't be loaded atomically we
  124. * have to disable the interrupt while the configuration state
  125. * is invalid.
  126. */
  127. disabled = ath79_gpio_update_bits(
  128. ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, 0);
  129. ath79_gpio_update_bits(
  130. ctrl, AR71XX_GPIO_REG_INT_TYPE, mask, type);
  131. ath79_gpio_update_bits(
  132. ctrl, AR71XX_GPIO_REG_INT_POLARITY, mask, polarity);
  133. if (disabled)
  134. ath79_gpio_update_bits(
  135. ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask);
  136. raw_spin_unlock_irqrestore(&ctrl->lock, flags);
  137. return 0;
  138. }
  139. static struct irq_chip ath79_gpio_irqchip = {
  140. .name = "gpio-ath79",
  141. .irq_enable = ath79_gpio_irq_enable,
  142. .irq_disable = ath79_gpio_irq_disable,
  143. .irq_mask = ath79_gpio_irq_mask,
  144. .irq_unmask = ath79_gpio_irq_unmask,
  145. .irq_set_type = ath79_gpio_irq_set_type,
  146. };
  147. static void ath79_gpio_irq_handler(struct irq_desc *desc)
  148. {
  149. struct gpio_chip *gc = irq_desc_get_handler_data(desc);
  150. struct irq_chip *irqchip = irq_desc_get_chip(desc);
  151. struct ath79_gpio_ctrl *ctrl =
  152. container_of(gc, struct ath79_gpio_ctrl, gc);
  153. unsigned long flags, pending;
  154. u32 both_edges, state;
  155. int irq;
  156. chained_irq_enter(irqchip, desc);
  157. raw_spin_lock_irqsave(&ctrl->lock, flags);
  158. pending = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_INT_PENDING);
  159. /* Update the polarity of the both edges irqs */
  160. both_edges = ctrl->both_edges & pending;
  161. if (both_edges) {
  162. state = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_IN);
  163. ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_POLARITY,
  164. both_edges, ~state);
  165. }
  166. raw_spin_unlock_irqrestore(&ctrl->lock, flags);
  167. if (pending) {
  168. for_each_set_bit(irq, &pending, gc->ngpio)
  169. generic_handle_irq(
  170. irq_linear_revmap(gc->irq.domain, irq));
  171. }
  172. chained_irq_exit(irqchip, desc);
  173. }
  174. static const struct of_device_id ath79_gpio_of_match[] = {
  175. { .compatible = "qca,ar7100-gpio" },
  176. { .compatible = "qca,ar9340-gpio" },
  177. {},
  178. };
  179. MODULE_DEVICE_TABLE(of, ath79_gpio_of_match);
  180. static int ath79_gpio_probe(struct platform_device *pdev)
  181. {
  182. struct ath79_gpio_platform_data *pdata = dev_get_platdata(&pdev->dev);
  183. struct device *dev = &pdev->dev;
  184. struct device_node *np = dev->of_node;
  185. struct ath79_gpio_ctrl *ctrl;
  186. struct gpio_irq_chip *girq;
  187. u32 ath79_gpio_count;
  188. bool oe_inverted;
  189. int err;
  190. ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
  191. if (!ctrl)
  192. return -ENOMEM;
  193. platform_set_drvdata(pdev, ctrl);
  194. if (np) {
  195. err = of_property_read_u32(np, "ngpios", &ath79_gpio_count);
  196. if (err) {
  197. dev_err(dev, "ngpios property is not valid\n");
  198. return err;
  199. }
  200. oe_inverted = of_device_is_compatible(np, "qca,ar9340-gpio");
  201. } else if (pdata) {
  202. ath79_gpio_count = pdata->ngpios;
  203. oe_inverted = pdata->oe_inverted;
  204. } else {
  205. dev_err(dev, "No DT node or platform data found\n");
  206. return -EINVAL;
  207. }
  208. if (ath79_gpio_count >= 32) {
  209. dev_err(dev, "ngpios must be less than 32\n");
  210. return -EINVAL;
  211. }
  212. ctrl->base = devm_platform_ioremap_resource(pdev, 0);
  213. if (IS_ERR(ctrl->base))
  214. return PTR_ERR(ctrl->base);
  215. raw_spin_lock_init(&ctrl->lock);
  216. err = bgpio_init(&ctrl->gc, dev, 4,
  217. ctrl->base + AR71XX_GPIO_REG_IN,
  218. ctrl->base + AR71XX_GPIO_REG_SET,
  219. ctrl->base + AR71XX_GPIO_REG_CLEAR,
  220. oe_inverted ? NULL : ctrl->base + AR71XX_GPIO_REG_OE,
  221. oe_inverted ? ctrl->base + AR71XX_GPIO_REG_OE : NULL,
  222. 0);
  223. if (err) {
  224. dev_err(dev, "bgpio_init failed\n");
  225. return err;
  226. }
  227. /* Use base 0 to stay compatible with legacy platforms */
  228. ctrl->gc.base = 0;
  229. /* Optional interrupt setup */
  230. if (!np || of_property_read_bool(np, "interrupt-controller")) {
  231. girq = &ctrl->gc.irq;
  232. girq->chip = &ath79_gpio_irqchip;
  233. girq->parent_handler = ath79_gpio_irq_handler;
  234. girq->num_parents = 1;
  235. girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),
  236. GFP_KERNEL);
  237. if (!girq->parents)
  238. return -ENOMEM;
  239. girq->parents[0] = platform_get_irq(pdev, 0);
  240. girq->default_type = IRQ_TYPE_NONE;
  241. girq->handler = handle_simple_irq;
  242. }
  243. err = devm_gpiochip_add_data(dev, &ctrl->gc, ctrl);
  244. if (err) {
  245. dev_err(dev,
  246. "cannot add AR71xx GPIO chip, error=%d", err);
  247. return err;
  248. }
  249. return 0;
  250. }
  251. static struct platform_driver ath79_gpio_driver = {
  252. .driver = {
  253. .name = "ath79-gpio",
  254. .of_match_table = ath79_gpio_of_match,
  255. },
  256. .probe = ath79_gpio_probe,
  257. };
  258. module_platform_driver(ath79_gpio_driver);
  259. MODULE_DESCRIPTION("Atheros AR71XX/AR724X/AR913X GPIO API support");
  260. MODULE_LICENSE("GPL v2");