gpio-aspeed.c 32 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright 2015 IBM Corp.
  4. *
  5. * Joel Stanley <joel@jms.id.au>
  6. */
  7. #include <asm/div64.h>
  8. #include <linux/clk.h>
  9. #include <linux/gpio/driver.h>
  10. #include <linux/gpio/aspeed.h>
  11. #include <linux/hashtable.h>
  12. #include <linux/init.h>
  13. #include <linux/io.h>
  14. #include <linux/kernel.h>
  15. #include <linux/module.h>
  16. #include <linux/pinctrl/consumer.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/spinlock.h>
  19. #include <linux/string.h>
  20. /*
  21. * These two headers aren't meant to be used by GPIO drivers. We need
  22. * them in order to access gpio_chip_hwgpio() which we need to implement
  23. * the aspeed specific API which allows the coprocessor to request
  24. * access to some GPIOs and to arbitrate between coprocessor and ARM.
  25. */
  26. #include <linux/gpio/consumer.h>
  27. #include "gpiolib.h"
  28. struct aspeed_bank_props {
  29. unsigned int bank;
  30. u32 input;
  31. u32 output;
  32. };
  33. struct aspeed_gpio_config {
  34. unsigned int nr_gpios;
  35. const struct aspeed_bank_props *props;
  36. };
  37. /*
  38. * @offset_timer: Maps an offset to an @timer_users index, or zero if disabled
  39. * @timer_users: Tracks the number of users for each timer
  40. *
  41. * The @timer_users has four elements but the first element is unused. This is
  42. * to simplify accounting and indexing, as a zero value in @offset_timer
  43. * represents disabled debouncing for the GPIO. Any other value for an element
  44. * of @offset_timer is used as an index into @timer_users. This behaviour of
  45. * the zero value aligns with the behaviour of zero built from the timer
  46. * configuration registers (i.e. debouncing is disabled).
  47. */
  48. struct aspeed_gpio {
  49. struct gpio_chip chip;
  50. struct irq_chip irqc;
  51. raw_spinlock_t lock;
  52. void __iomem *base;
  53. int irq;
  54. const struct aspeed_gpio_config *config;
  55. u8 *offset_timer;
  56. unsigned int timer_users[4];
  57. struct clk *clk;
  58. u32 *dcache;
  59. u8 *cf_copro_bankmap;
  60. };
  61. struct aspeed_gpio_bank {
  62. uint16_t val_regs; /* +0: Rd: read input value, Wr: set write latch
  63. * +4: Rd/Wr: Direction (0=in, 1=out)
  64. */
  65. uint16_t rdata_reg; /* Rd: read write latch, Wr: <none> */
  66. uint16_t irq_regs;
  67. uint16_t debounce_regs;
  68. uint16_t tolerance_regs;
  69. uint16_t cmdsrc_regs;
  70. const char names[4][3];
  71. };
  72. /*
  73. * Note: The "value" register returns the input value sampled on the
  74. * line even when the GPIO is configured as an output. Since
  75. * that input goes through synchronizers, writing, then reading
  76. * back may not return the written value right away.
  77. *
  78. * The "rdata" register returns the content of the write latch
  79. * and thus can be used to read back what was last written
  80. * reliably.
  81. */
  82. static const int debounce_timers[4] = { 0x00, 0x50, 0x54, 0x58 };
  83. static const struct aspeed_gpio_copro_ops *copro_ops;
  84. static void *copro_data;
  85. static const struct aspeed_gpio_bank aspeed_gpio_banks[] = {
  86. {
  87. .val_regs = 0x0000,
  88. .rdata_reg = 0x00c0,
  89. .irq_regs = 0x0008,
  90. .debounce_regs = 0x0040,
  91. .tolerance_regs = 0x001c,
  92. .cmdsrc_regs = 0x0060,
  93. .names = { "A", "B", "C", "D" },
  94. },
  95. {
  96. .val_regs = 0x0020,
  97. .rdata_reg = 0x00c4,
  98. .irq_regs = 0x0028,
  99. .debounce_regs = 0x0048,
  100. .tolerance_regs = 0x003c,
  101. .cmdsrc_regs = 0x0068,
  102. .names = { "E", "F", "G", "H" },
  103. },
  104. {
  105. .val_regs = 0x0070,
  106. .rdata_reg = 0x00c8,
  107. .irq_regs = 0x0098,
  108. .debounce_regs = 0x00b0,
  109. .tolerance_regs = 0x00ac,
  110. .cmdsrc_regs = 0x0090,
  111. .names = { "I", "J", "K", "L" },
  112. },
  113. {
  114. .val_regs = 0x0078,
  115. .rdata_reg = 0x00cc,
  116. .irq_regs = 0x00e8,
  117. .debounce_regs = 0x0100,
  118. .tolerance_regs = 0x00fc,
  119. .cmdsrc_regs = 0x00e0,
  120. .names = { "M", "N", "O", "P" },
  121. },
  122. {
  123. .val_regs = 0x0080,
  124. .rdata_reg = 0x00d0,
  125. .irq_regs = 0x0118,
  126. .debounce_regs = 0x0130,
  127. .tolerance_regs = 0x012c,
  128. .cmdsrc_regs = 0x0110,
  129. .names = { "Q", "R", "S", "T" },
  130. },
  131. {
  132. .val_regs = 0x0088,
  133. .rdata_reg = 0x00d4,
  134. .irq_regs = 0x0148,
  135. .debounce_regs = 0x0160,
  136. .tolerance_regs = 0x015c,
  137. .cmdsrc_regs = 0x0140,
  138. .names = { "U", "V", "W", "X" },
  139. },
  140. {
  141. .val_regs = 0x01E0,
  142. .rdata_reg = 0x00d8,
  143. .irq_regs = 0x0178,
  144. .debounce_regs = 0x0190,
  145. .tolerance_regs = 0x018c,
  146. .cmdsrc_regs = 0x0170,
  147. .names = { "Y", "Z", "AA", "AB" },
  148. },
  149. {
  150. .val_regs = 0x01e8,
  151. .rdata_reg = 0x00dc,
  152. .irq_regs = 0x01a8,
  153. .debounce_regs = 0x01c0,
  154. .tolerance_regs = 0x01bc,
  155. .cmdsrc_regs = 0x01a0,
  156. .names = { "AC", "", "", "" },
  157. },
  158. };
  159. enum aspeed_gpio_reg {
  160. reg_val,
  161. reg_rdata,
  162. reg_dir,
  163. reg_irq_enable,
  164. reg_irq_type0,
  165. reg_irq_type1,
  166. reg_irq_type2,
  167. reg_irq_status,
  168. reg_debounce_sel1,
  169. reg_debounce_sel2,
  170. reg_tolerance,
  171. reg_cmdsrc0,
  172. reg_cmdsrc1,
  173. };
  174. #define GPIO_VAL_VALUE 0x00
  175. #define GPIO_VAL_DIR 0x04
  176. #define GPIO_IRQ_ENABLE 0x00
  177. #define GPIO_IRQ_TYPE0 0x04
  178. #define GPIO_IRQ_TYPE1 0x08
  179. #define GPIO_IRQ_TYPE2 0x0c
  180. #define GPIO_IRQ_STATUS 0x10
  181. #define GPIO_DEBOUNCE_SEL1 0x00
  182. #define GPIO_DEBOUNCE_SEL2 0x04
  183. #define GPIO_CMDSRC_0 0x00
  184. #define GPIO_CMDSRC_1 0x04
  185. #define GPIO_CMDSRC_ARM 0
  186. #define GPIO_CMDSRC_LPC 1
  187. #define GPIO_CMDSRC_COLDFIRE 2
  188. #define GPIO_CMDSRC_RESERVED 3
  189. /* This will be resolved at compile time */
  190. static inline void __iomem *bank_reg(struct aspeed_gpio *gpio,
  191. const struct aspeed_gpio_bank *bank,
  192. const enum aspeed_gpio_reg reg)
  193. {
  194. switch (reg) {
  195. case reg_val:
  196. return gpio->base + bank->val_regs + GPIO_VAL_VALUE;
  197. case reg_rdata:
  198. return gpio->base + bank->rdata_reg;
  199. case reg_dir:
  200. return gpio->base + bank->val_regs + GPIO_VAL_DIR;
  201. case reg_irq_enable:
  202. return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE;
  203. case reg_irq_type0:
  204. return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0;
  205. case reg_irq_type1:
  206. return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1;
  207. case reg_irq_type2:
  208. return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2;
  209. case reg_irq_status:
  210. return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS;
  211. case reg_debounce_sel1:
  212. return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL1;
  213. case reg_debounce_sel2:
  214. return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL2;
  215. case reg_tolerance:
  216. return gpio->base + bank->tolerance_regs;
  217. case reg_cmdsrc0:
  218. return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_0;
  219. case reg_cmdsrc1:
  220. return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_1;
  221. }
  222. BUG();
  223. }
  224. #define GPIO_BANK(x) ((x) >> 5)
  225. #define GPIO_OFFSET(x) ((x) & 0x1f)
  226. #define GPIO_BIT(x) BIT(GPIO_OFFSET(x))
  227. #define _GPIO_SET_DEBOUNCE(t, o, i) ((!!((t) & BIT(i))) << GPIO_OFFSET(o))
  228. #define GPIO_SET_DEBOUNCE1(t, o) _GPIO_SET_DEBOUNCE(t, o, 1)
  229. #define GPIO_SET_DEBOUNCE2(t, o) _GPIO_SET_DEBOUNCE(t, o, 0)
  230. static const struct aspeed_gpio_bank *to_bank(unsigned int offset)
  231. {
  232. unsigned int bank = GPIO_BANK(offset);
  233. WARN_ON(bank >= ARRAY_SIZE(aspeed_gpio_banks));
  234. return &aspeed_gpio_banks[bank];
  235. }
  236. static inline bool is_bank_props_sentinel(const struct aspeed_bank_props *props)
  237. {
  238. return !(props->input || props->output);
  239. }
  240. static inline const struct aspeed_bank_props *find_bank_props(
  241. struct aspeed_gpio *gpio, unsigned int offset)
  242. {
  243. const struct aspeed_bank_props *props = gpio->config->props;
  244. while (!is_bank_props_sentinel(props)) {
  245. if (props->bank == GPIO_BANK(offset))
  246. return props;
  247. props++;
  248. }
  249. return NULL;
  250. }
  251. static inline bool have_gpio(struct aspeed_gpio *gpio, unsigned int offset)
  252. {
  253. const struct aspeed_bank_props *props = find_bank_props(gpio, offset);
  254. const struct aspeed_gpio_bank *bank = to_bank(offset);
  255. unsigned int group = GPIO_OFFSET(offset) / 8;
  256. return bank->names[group][0] != '\0' &&
  257. (!props || ((props->input | props->output) & GPIO_BIT(offset)));
  258. }
  259. static inline bool have_input(struct aspeed_gpio *gpio, unsigned int offset)
  260. {
  261. const struct aspeed_bank_props *props = find_bank_props(gpio, offset);
  262. return !props || (props->input & GPIO_BIT(offset));
  263. }
  264. #define have_irq(g, o) have_input((g), (o))
  265. #define have_debounce(g, o) have_input((g), (o))
  266. static inline bool have_output(struct aspeed_gpio *gpio, unsigned int offset)
  267. {
  268. const struct aspeed_bank_props *props = find_bank_props(gpio, offset);
  269. return !props || (props->output & GPIO_BIT(offset));
  270. }
  271. static void aspeed_gpio_change_cmd_source(struct aspeed_gpio *gpio,
  272. const struct aspeed_gpio_bank *bank,
  273. int bindex, int cmdsrc)
  274. {
  275. void __iomem *c0 = bank_reg(gpio, bank, reg_cmdsrc0);
  276. void __iomem *c1 = bank_reg(gpio, bank, reg_cmdsrc1);
  277. u32 bit, reg;
  278. /*
  279. * Each register controls 4 banks, so take the bottom 2
  280. * bits of the bank index, and use them to select the
  281. * right control bit (0, 8, 16 or 24).
  282. */
  283. bit = BIT((bindex & 3) << 3);
  284. /* Source 1 first to avoid illegal 11 combination */
  285. reg = ioread32(c1);
  286. if (cmdsrc & 2)
  287. reg |= bit;
  288. else
  289. reg &= ~bit;
  290. iowrite32(reg, c1);
  291. /* Then Source 0 */
  292. reg = ioread32(c0);
  293. if (cmdsrc & 1)
  294. reg |= bit;
  295. else
  296. reg &= ~bit;
  297. iowrite32(reg, c0);
  298. }
  299. static bool aspeed_gpio_copro_request(struct aspeed_gpio *gpio,
  300. unsigned int offset)
  301. {
  302. const struct aspeed_gpio_bank *bank = to_bank(offset);
  303. if (!copro_ops || !gpio->cf_copro_bankmap)
  304. return false;
  305. if (!gpio->cf_copro_bankmap[offset >> 3])
  306. return false;
  307. if (!copro_ops->request_access)
  308. return false;
  309. /* Pause the coprocessor */
  310. copro_ops->request_access(copro_data);
  311. /* Change command source back to ARM */
  312. aspeed_gpio_change_cmd_source(gpio, bank, offset >> 3, GPIO_CMDSRC_ARM);
  313. /* Update cache */
  314. gpio->dcache[GPIO_BANK(offset)] = ioread32(bank_reg(gpio, bank, reg_rdata));
  315. return true;
  316. }
  317. static void aspeed_gpio_copro_release(struct aspeed_gpio *gpio,
  318. unsigned int offset)
  319. {
  320. const struct aspeed_gpio_bank *bank = to_bank(offset);
  321. if (!copro_ops || !gpio->cf_copro_bankmap)
  322. return;
  323. if (!gpio->cf_copro_bankmap[offset >> 3])
  324. return;
  325. if (!copro_ops->release_access)
  326. return;
  327. /* Change command source back to ColdFire */
  328. aspeed_gpio_change_cmd_source(gpio, bank, offset >> 3,
  329. GPIO_CMDSRC_COLDFIRE);
  330. /* Restart the coprocessor */
  331. copro_ops->release_access(copro_data);
  332. }
  333. static int aspeed_gpio_get(struct gpio_chip *gc, unsigned int offset)
  334. {
  335. struct aspeed_gpio *gpio = gpiochip_get_data(gc);
  336. const struct aspeed_gpio_bank *bank = to_bank(offset);
  337. return !!(ioread32(bank_reg(gpio, bank, reg_val)) & GPIO_BIT(offset));
  338. }
  339. static void __aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset,
  340. int val)
  341. {
  342. struct aspeed_gpio *gpio = gpiochip_get_data(gc);
  343. const struct aspeed_gpio_bank *bank = to_bank(offset);
  344. void __iomem *addr;
  345. u32 reg;
  346. addr = bank_reg(gpio, bank, reg_val);
  347. reg = gpio->dcache[GPIO_BANK(offset)];
  348. if (val)
  349. reg |= GPIO_BIT(offset);
  350. else
  351. reg &= ~GPIO_BIT(offset);
  352. gpio->dcache[GPIO_BANK(offset)] = reg;
  353. iowrite32(reg, addr);
  354. }
  355. static void aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset,
  356. int val)
  357. {
  358. struct aspeed_gpio *gpio = gpiochip_get_data(gc);
  359. unsigned long flags;
  360. bool copro;
  361. raw_spin_lock_irqsave(&gpio->lock, flags);
  362. copro = aspeed_gpio_copro_request(gpio, offset);
  363. __aspeed_gpio_set(gc, offset, val);
  364. if (copro)
  365. aspeed_gpio_copro_release(gpio, offset);
  366. raw_spin_unlock_irqrestore(&gpio->lock, flags);
  367. }
  368. static int aspeed_gpio_dir_in(struct gpio_chip *gc, unsigned int offset)
  369. {
  370. struct aspeed_gpio *gpio = gpiochip_get_data(gc);
  371. const struct aspeed_gpio_bank *bank = to_bank(offset);
  372. void __iomem *addr = bank_reg(gpio, bank, reg_dir);
  373. unsigned long flags;
  374. bool copro;
  375. u32 reg;
  376. if (!have_input(gpio, offset))
  377. return -ENOTSUPP;
  378. raw_spin_lock_irqsave(&gpio->lock, flags);
  379. reg = ioread32(addr);
  380. reg &= ~GPIO_BIT(offset);
  381. copro = aspeed_gpio_copro_request(gpio, offset);
  382. iowrite32(reg, addr);
  383. if (copro)
  384. aspeed_gpio_copro_release(gpio, offset);
  385. raw_spin_unlock_irqrestore(&gpio->lock, flags);
  386. return 0;
  387. }
  388. static int aspeed_gpio_dir_out(struct gpio_chip *gc,
  389. unsigned int offset, int val)
  390. {
  391. struct aspeed_gpio *gpio = gpiochip_get_data(gc);
  392. const struct aspeed_gpio_bank *bank = to_bank(offset);
  393. void __iomem *addr = bank_reg(gpio, bank, reg_dir);
  394. unsigned long flags;
  395. bool copro;
  396. u32 reg;
  397. if (!have_output(gpio, offset))
  398. return -ENOTSUPP;
  399. raw_spin_lock_irqsave(&gpio->lock, flags);
  400. reg = ioread32(addr);
  401. reg |= GPIO_BIT(offset);
  402. copro = aspeed_gpio_copro_request(gpio, offset);
  403. __aspeed_gpio_set(gc, offset, val);
  404. iowrite32(reg, addr);
  405. if (copro)
  406. aspeed_gpio_copro_release(gpio, offset);
  407. raw_spin_unlock_irqrestore(&gpio->lock, flags);
  408. return 0;
  409. }
  410. static int aspeed_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
  411. {
  412. struct aspeed_gpio *gpio = gpiochip_get_data(gc);
  413. const struct aspeed_gpio_bank *bank = to_bank(offset);
  414. unsigned long flags;
  415. u32 val;
  416. if (!have_input(gpio, offset))
  417. return GPIO_LINE_DIRECTION_OUT;
  418. if (!have_output(gpio, offset))
  419. return GPIO_LINE_DIRECTION_IN;
  420. raw_spin_lock_irqsave(&gpio->lock, flags);
  421. val = ioread32(bank_reg(gpio, bank, reg_dir)) & GPIO_BIT(offset);
  422. raw_spin_unlock_irqrestore(&gpio->lock, flags);
  423. return val ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
  424. }
  425. static inline int irqd_to_aspeed_gpio_data(struct irq_data *d,
  426. struct aspeed_gpio **gpio,
  427. const struct aspeed_gpio_bank **bank,
  428. u32 *bit, int *offset)
  429. {
  430. struct aspeed_gpio *internal;
  431. *offset = irqd_to_hwirq(d);
  432. internal = irq_data_get_irq_chip_data(d);
  433. /* This might be a bit of a questionable place to check */
  434. if (!have_irq(internal, *offset))
  435. return -ENOTSUPP;
  436. *gpio = internal;
  437. *bank = to_bank(*offset);
  438. *bit = GPIO_BIT(*offset);
  439. return 0;
  440. }
  441. static void aspeed_gpio_irq_ack(struct irq_data *d)
  442. {
  443. const struct aspeed_gpio_bank *bank;
  444. struct aspeed_gpio *gpio;
  445. unsigned long flags;
  446. void __iomem *status_addr;
  447. int rc, offset;
  448. bool copro;
  449. u32 bit;
  450. rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset);
  451. if (rc)
  452. return;
  453. status_addr = bank_reg(gpio, bank, reg_irq_status);
  454. raw_spin_lock_irqsave(&gpio->lock, flags);
  455. copro = aspeed_gpio_copro_request(gpio, offset);
  456. iowrite32(bit, status_addr);
  457. if (copro)
  458. aspeed_gpio_copro_release(gpio, offset);
  459. raw_spin_unlock_irqrestore(&gpio->lock, flags);
  460. }
  461. static void aspeed_gpio_irq_set_mask(struct irq_data *d, bool set)
  462. {
  463. const struct aspeed_gpio_bank *bank;
  464. struct aspeed_gpio *gpio;
  465. unsigned long flags;
  466. u32 reg, bit;
  467. void __iomem *addr;
  468. int rc, offset;
  469. bool copro;
  470. rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset);
  471. if (rc)
  472. return;
  473. addr = bank_reg(gpio, bank, reg_irq_enable);
  474. raw_spin_lock_irqsave(&gpio->lock, flags);
  475. copro = aspeed_gpio_copro_request(gpio, offset);
  476. reg = ioread32(addr);
  477. if (set)
  478. reg |= bit;
  479. else
  480. reg &= ~bit;
  481. iowrite32(reg, addr);
  482. if (copro)
  483. aspeed_gpio_copro_release(gpio, offset);
  484. raw_spin_unlock_irqrestore(&gpio->lock, flags);
  485. }
  486. static void aspeed_gpio_irq_mask(struct irq_data *d)
  487. {
  488. aspeed_gpio_irq_set_mask(d, false);
  489. }
  490. static void aspeed_gpio_irq_unmask(struct irq_data *d)
  491. {
  492. aspeed_gpio_irq_set_mask(d, true);
  493. }
  494. static int aspeed_gpio_set_type(struct irq_data *d, unsigned int type)
  495. {
  496. u32 type0 = 0;
  497. u32 type1 = 0;
  498. u32 type2 = 0;
  499. u32 bit, reg;
  500. const struct aspeed_gpio_bank *bank;
  501. irq_flow_handler_t handler;
  502. struct aspeed_gpio *gpio;
  503. unsigned long flags;
  504. void __iomem *addr;
  505. int rc, offset;
  506. bool copro;
  507. rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset);
  508. if (rc)
  509. return -EINVAL;
  510. switch (type & IRQ_TYPE_SENSE_MASK) {
  511. case IRQ_TYPE_EDGE_BOTH:
  512. type2 |= bit;
  513. fallthrough;
  514. case IRQ_TYPE_EDGE_RISING:
  515. type0 |= bit;
  516. fallthrough;
  517. case IRQ_TYPE_EDGE_FALLING:
  518. handler = handle_edge_irq;
  519. break;
  520. case IRQ_TYPE_LEVEL_HIGH:
  521. type0 |= bit;
  522. fallthrough;
  523. case IRQ_TYPE_LEVEL_LOW:
  524. type1 |= bit;
  525. handler = handle_level_irq;
  526. break;
  527. default:
  528. return -EINVAL;
  529. }
  530. raw_spin_lock_irqsave(&gpio->lock, flags);
  531. copro = aspeed_gpio_copro_request(gpio, offset);
  532. addr = bank_reg(gpio, bank, reg_irq_type0);
  533. reg = ioread32(addr);
  534. reg = (reg & ~bit) | type0;
  535. iowrite32(reg, addr);
  536. addr = bank_reg(gpio, bank, reg_irq_type1);
  537. reg = ioread32(addr);
  538. reg = (reg & ~bit) | type1;
  539. iowrite32(reg, addr);
  540. addr = bank_reg(gpio, bank, reg_irq_type2);
  541. reg = ioread32(addr);
  542. reg = (reg & ~bit) | type2;
  543. iowrite32(reg, addr);
  544. if (copro)
  545. aspeed_gpio_copro_release(gpio, offset);
  546. raw_spin_unlock_irqrestore(&gpio->lock, flags);
  547. irq_set_handler_locked(d, handler);
  548. return 0;
  549. }
  550. static void aspeed_gpio_irq_handler(struct irq_desc *desc)
  551. {
  552. struct gpio_chip *gc = irq_desc_get_handler_data(desc);
  553. struct irq_chip *ic = irq_desc_get_chip(desc);
  554. struct aspeed_gpio *data = gpiochip_get_data(gc);
  555. unsigned int i, p, girq, banks;
  556. unsigned long reg;
  557. struct aspeed_gpio *gpio = gpiochip_get_data(gc);
  558. chained_irq_enter(ic, desc);
  559. banks = DIV_ROUND_UP(gpio->chip.ngpio, 32);
  560. for (i = 0; i < banks; i++) {
  561. const struct aspeed_gpio_bank *bank = &aspeed_gpio_banks[i];
  562. reg = ioread32(bank_reg(data, bank, reg_irq_status));
  563. for_each_set_bit(p, &reg, 32) {
  564. girq = irq_find_mapping(gc->irq.domain, i * 32 + p);
  565. generic_handle_irq(girq);
  566. }
  567. }
  568. chained_irq_exit(ic, desc);
  569. }
  570. static void aspeed_init_irq_valid_mask(struct gpio_chip *gc,
  571. unsigned long *valid_mask,
  572. unsigned int ngpios)
  573. {
  574. struct aspeed_gpio *gpio = gpiochip_get_data(gc);
  575. const struct aspeed_bank_props *props = gpio->config->props;
  576. while (!is_bank_props_sentinel(props)) {
  577. unsigned int offset;
  578. const unsigned long int input = props->input;
  579. /* Pretty crummy approach, but similar to GPIO core */
  580. for_each_clear_bit(offset, &input, 32) {
  581. unsigned int i = props->bank * 32 + offset;
  582. if (i >= gpio->chip.ngpio)
  583. break;
  584. clear_bit(i, valid_mask);
  585. }
  586. props++;
  587. }
  588. }
  589. static int aspeed_gpio_reset_tolerance(struct gpio_chip *chip,
  590. unsigned int offset, bool enable)
  591. {
  592. struct aspeed_gpio *gpio = gpiochip_get_data(chip);
  593. unsigned long flags;
  594. void __iomem *treg;
  595. bool copro;
  596. u32 val;
  597. treg = bank_reg(gpio, to_bank(offset), reg_tolerance);
  598. raw_spin_lock_irqsave(&gpio->lock, flags);
  599. copro = aspeed_gpio_copro_request(gpio, offset);
  600. val = readl(treg);
  601. if (enable)
  602. val |= GPIO_BIT(offset);
  603. else
  604. val &= ~GPIO_BIT(offset);
  605. writel(val, treg);
  606. if (copro)
  607. aspeed_gpio_copro_release(gpio, offset);
  608. raw_spin_unlock_irqrestore(&gpio->lock, flags);
  609. return 0;
  610. }
  611. static int aspeed_gpio_request(struct gpio_chip *chip, unsigned int offset)
  612. {
  613. if (!have_gpio(gpiochip_get_data(chip), offset))
  614. return -ENODEV;
  615. return pinctrl_gpio_request(chip->base + offset);
  616. }
  617. static void aspeed_gpio_free(struct gpio_chip *chip, unsigned int offset)
  618. {
  619. pinctrl_gpio_free(chip->base + offset);
  620. }
  621. static int usecs_to_cycles(struct aspeed_gpio *gpio, unsigned long usecs,
  622. u32 *cycles)
  623. {
  624. u64 rate;
  625. u64 n;
  626. u32 r;
  627. rate = clk_get_rate(gpio->clk);
  628. if (!rate)
  629. return -ENOTSUPP;
  630. n = rate * usecs;
  631. r = do_div(n, 1000000);
  632. if (n >= U32_MAX)
  633. return -ERANGE;
  634. /* At least as long as the requested time */
  635. *cycles = n + (!!r);
  636. return 0;
  637. }
  638. /* Call under gpio->lock */
  639. static int register_allocated_timer(struct aspeed_gpio *gpio,
  640. unsigned int offset, unsigned int timer)
  641. {
  642. if (WARN(gpio->offset_timer[offset] != 0,
  643. "Offset %d already allocated timer %d\n",
  644. offset, gpio->offset_timer[offset]))
  645. return -EINVAL;
  646. if (WARN(gpio->timer_users[timer] == UINT_MAX,
  647. "Timer user count would overflow\n"))
  648. return -EPERM;
  649. gpio->offset_timer[offset] = timer;
  650. gpio->timer_users[timer]++;
  651. return 0;
  652. }
  653. /* Call under gpio->lock */
  654. static int unregister_allocated_timer(struct aspeed_gpio *gpio,
  655. unsigned int offset)
  656. {
  657. if (WARN(gpio->offset_timer[offset] == 0,
  658. "No timer allocated to offset %d\n", offset))
  659. return -EINVAL;
  660. if (WARN(gpio->timer_users[gpio->offset_timer[offset]] == 0,
  661. "No users recorded for timer %d\n",
  662. gpio->offset_timer[offset]))
  663. return -EINVAL;
  664. gpio->timer_users[gpio->offset_timer[offset]]--;
  665. gpio->offset_timer[offset] = 0;
  666. return 0;
  667. }
  668. /* Call under gpio->lock */
  669. static inline bool timer_allocation_registered(struct aspeed_gpio *gpio,
  670. unsigned int offset)
  671. {
  672. return gpio->offset_timer[offset] > 0;
  673. }
  674. /* Call under gpio->lock */
  675. static void configure_timer(struct aspeed_gpio *gpio, unsigned int offset,
  676. unsigned int timer)
  677. {
  678. const struct aspeed_gpio_bank *bank = to_bank(offset);
  679. const u32 mask = GPIO_BIT(offset);
  680. void __iomem *addr;
  681. u32 val;
  682. /* Note: Debounce timer isn't under control of the command
  683. * source registers, so no need to sync with the coprocessor
  684. */
  685. addr = bank_reg(gpio, bank, reg_debounce_sel1);
  686. val = ioread32(addr);
  687. iowrite32((val & ~mask) | GPIO_SET_DEBOUNCE1(timer, offset), addr);
  688. addr = bank_reg(gpio, bank, reg_debounce_sel2);
  689. val = ioread32(addr);
  690. iowrite32((val & ~mask) | GPIO_SET_DEBOUNCE2(timer, offset), addr);
  691. }
  692. static int enable_debounce(struct gpio_chip *chip, unsigned int offset,
  693. unsigned long usecs)
  694. {
  695. struct aspeed_gpio *gpio = gpiochip_get_data(chip);
  696. u32 requested_cycles;
  697. unsigned long flags;
  698. int rc;
  699. int i;
  700. if (!gpio->clk)
  701. return -EINVAL;
  702. rc = usecs_to_cycles(gpio, usecs, &requested_cycles);
  703. if (rc < 0) {
  704. dev_warn(chip->parent, "Failed to convert %luus to cycles at %luHz: %d\n",
  705. usecs, clk_get_rate(gpio->clk), rc);
  706. return rc;
  707. }
  708. raw_spin_lock_irqsave(&gpio->lock, flags);
  709. if (timer_allocation_registered(gpio, offset)) {
  710. rc = unregister_allocated_timer(gpio, offset);
  711. if (rc < 0)
  712. goto out;
  713. }
  714. /* Try to find a timer already configured for the debounce period */
  715. for (i = 1; i < ARRAY_SIZE(debounce_timers); i++) {
  716. u32 cycles;
  717. cycles = ioread32(gpio->base + debounce_timers[i]);
  718. if (requested_cycles == cycles)
  719. break;
  720. }
  721. if (i == ARRAY_SIZE(debounce_timers)) {
  722. int j;
  723. /*
  724. * As there are no timers configured for the requested debounce
  725. * period, find an unused timer instead
  726. */
  727. for (j = 1; j < ARRAY_SIZE(gpio->timer_users); j++) {
  728. if (gpio->timer_users[j] == 0)
  729. break;
  730. }
  731. if (j == ARRAY_SIZE(gpio->timer_users)) {
  732. dev_warn(chip->parent,
  733. "Debounce timers exhausted, cannot debounce for period %luus\n",
  734. usecs);
  735. rc = -EPERM;
  736. /*
  737. * We already adjusted the accounting to remove @offset
  738. * as a user of its previous timer, so also configure
  739. * the hardware so @offset has timers disabled for
  740. * consistency.
  741. */
  742. configure_timer(gpio, offset, 0);
  743. goto out;
  744. }
  745. i = j;
  746. iowrite32(requested_cycles, gpio->base + debounce_timers[i]);
  747. }
  748. if (WARN(i == 0, "Cannot register index of disabled timer\n")) {
  749. rc = -EINVAL;
  750. goto out;
  751. }
  752. register_allocated_timer(gpio, offset, i);
  753. configure_timer(gpio, offset, i);
  754. out:
  755. raw_spin_unlock_irqrestore(&gpio->lock, flags);
  756. return rc;
  757. }
  758. static int disable_debounce(struct gpio_chip *chip, unsigned int offset)
  759. {
  760. struct aspeed_gpio *gpio = gpiochip_get_data(chip);
  761. unsigned long flags;
  762. int rc;
  763. raw_spin_lock_irqsave(&gpio->lock, flags);
  764. rc = unregister_allocated_timer(gpio, offset);
  765. if (!rc)
  766. configure_timer(gpio, offset, 0);
  767. raw_spin_unlock_irqrestore(&gpio->lock, flags);
  768. return rc;
  769. }
  770. static int set_debounce(struct gpio_chip *chip, unsigned int offset,
  771. unsigned long usecs)
  772. {
  773. struct aspeed_gpio *gpio = gpiochip_get_data(chip);
  774. if (!have_debounce(gpio, offset))
  775. return -ENOTSUPP;
  776. if (usecs)
  777. return enable_debounce(chip, offset, usecs);
  778. return disable_debounce(chip, offset);
  779. }
  780. static int aspeed_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
  781. unsigned long config)
  782. {
  783. unsigned long param = pinconf_to_config_param(config);
  784. u32 arg = pinconf_to_config_argument(config);
  785. if (param == PIN_CONFIG_INPUT_DEBOUNCE)
  786. return set_debounce(chip, offset, arg);
  787. else if (param == PIN_CONFIG_BIAS_DISABLE ||
  788. param == PIN_CONFIG_BIAS_PULL_DOWN ||
  789. param == PIN_CONFIG_DRIVE_STRENGTH)
  790. return pinctrl_gpio_set_config(offset, config);
  791. else if (param == PIN_CONFIG_DRIVE_OPEN_DRAIN ||
  792. param == PIN_CONFIG_DRIVE_OPEN_SOURCE)
  793. /* Return -ENOTSUPP to trigger emulation, as per datasheet */
  794. return -ENOTSUPP;
  795. else if (param == PIN_CONFIG_PERSIST_STATE)
  796. return aspeed_gpio_reset_tolerance(chip, offset, arg);
  797. return -ENOTSUPP;
  798. }
  799. /**
  800. * aspeed_gpio_copro_set_ops - Sets the callbacks used for handshaking with
  801. * the coprocessor for shared GPIO banks
  802. * @ops: The callbacks
  803. * @data: Pointer passed back to the callbacks
  804. */
  805. int aspeed_gpio_copro_set_ops(const struct aspeed_gpio_copro_ops *ops, void *data)
  806. {
  807. copro_data = data;
  808. copro_ops = ops;
  809. return 0;
  810. }
  811. EXPORT_SYMBOL_GPL(aspeed_gpio_copro_set_ops);
  812. /**
  813. * aspeed_gpio_copro_grab_gpio - Mark a GPIO used by the coprocessor. The entire
  814. * bank gets marked and any access from the ARM will
  815. * result in handshaking via callbacks.
  816. * @desc: The GPIO to be marked
  817. * @vreg_offset: If non-NULL, returns the value register offset in the GPIO space
  818. * @dreg_offset: If non-NULL, returns the data latch register offset in the GPIO space
  819. * @bit: If non-NULL, returns the bit number of the GPIO in the registers
  820. */
  821. int aspeed_gpio_copro_grab_gpio(struct gpio_desc *desc,
  822. u16 *vreg_offset, u16 *dreg_offset, u8 *bit)
  823. {
  824. struct gpio_chip *chip = gpiod_to_chip(desc);
  825. struct aspeed_gpio *gpio = gpiochip_get_data(chip);
  826. int rc = 0, bindex, offset = gpio_chip_hwgpio(desc);
  827. const struct aspeed_gpio_bank *bank = to_bank(offset);
  828. unsigned long flags;
  829. if (!gpio->cf_copro_bankmap)
  830. gpio->cf_copro_bankmap = kzalloc(gpio->chip.ngpio >> 3, GFP_KERNEL);
  831. if (!gpio->cf_copro_bankmap)
  832. return -ENOMEM;
  833. if (offset < 0 || offset > gpio->chip.ngpio)
  834. return -EINVAL;
  835. bindex = offset >> 3;
  836. raw_spin_lock_irqsave(&gpio->lock, flags);
  837. /* Sanity check, this shouldn't happen */
  838. if (gpio->cf_copro_bankmap[bindex] == 0xff) {
  839. rc = -EIO;
  840. goto bail;
  841. }
  842. gpio->cf_copro_bankmap[bindex]++;
  843. /* Switch command source */
  844. if (gpio->cf_copro_bankmap[bindex] == 1)
  845. aspeed_gpio_change_cmd_source(gpio, bank, bindex,
  846. GPIO_CMDSRC_COLDFIRE);
  847. if (vreg_offset)
  848. *vreg_offset = bank->val_regs;
  849. if (dreg_offset)
  850. *dreg_offset = bank->rdata_reg;
  851. if (bit)
  852. *bit = GPIO_OFFSET(offset);
  853. bail:
  854. raw_spin_unlock_irqrestore(&gpio->lock, flags);
  855. return rc;
  856. }
  857. EXPORT_SYMBOL_GPL(aspeed_gpio_copro_grab_gpio);
  858. /**
  859. * aspeed_gpio_copro_release_gpio - Unmark a GPIO used by the coprocessor.
  860. * @desc: The GPIO to be marked
  861. */
  862. int aspeed_gpio_copro_release_gpio(struct gpio_desc *desc)
  863. {
  864. struct gpio_chip *chip = gpiod_to_chip(desc);
  865. struct aspeed_gpio *gpio = gpiochip_get_data(chip);
  866. int rc = 0, bindex, offset = gpio_chip_hwgpio(desc);
  867. const struct aspeed_gpio_bank *bank = to_bank(offset);
  868. unsigned long flags;
  869. if (!gpio->cf_copro_bankmap)
  870. return -ENXIO;
  871. if (offset < 0 || offset > gpio->chip.ngpio)
  872. return -EINVAL;
  873. bindex = offset >> 3;
  874. raw_spin_lock_irqsave(&gpio->lock, flags);
  875. /* Sanity check, this shouldn't happen */
  876. if (gpio->cf_copro_bankmap[bindex] == 0) {
  877. rc = -EIO;
  878. goto bail;
  879. }
  880. gpio->cf_copro_bankmap[bindex]--;
  881. /* Switch command source */
  882. if (gpio->cf_copro_bankmap[bindex] == 0)
  883. aspeed_gpio_change_cmd_source(gpio, bank, bindex,
  884. GPIO_CMDSRC_ARM);
  885. bail:
  886. raw_spin_unlock_irqrestore(&gpio->lock, flags);
  887. return rc;
  888. }
  889. EXPORT_SYMBOL_GPL(aspeed_gpio_copro_release_gpio);
  890. /*
  891. * Any banks not specified in a struct aspeed_bank_props array are assumed to
  892. * have the properties:
  893. *
  894. * { .input = 0xffffffff, .output = 0xffffffff }
  895. */
  896. static const struct aspeed_bank_props ast2400_bank_props[] = {
  897. /* input output */
  898. { 5, 0xffffffff, 0x0000ffff }, /* U/V/W/X */
  899. { 6, 0x0000000f, 0x0fffff0f }, /* Y/Z/AA/AB, two 4-GPIO holes */
  900. { },
  901. };
  902. static const struct aspeed_gpio_config ast2400_config =
  903. /* 220 for simplicity, really 216 with two 4-GPIO holes, four at end */
  904. { .nr_gpios = 220, .props = ast2400_bank_props, };
  905. static const struct aspeed_bank_props ast2500_bank_props[] = {
  906. /* input output */
  907. { 5, 0xffffffff, 0x0000ffff }, /* U/V/W/X */
  908. { 6, 0x0fffffff, 0x0fffffff }, /* Y/Z/AA/AB, 4-GPIO hole */
  909. { 7, 0x000000ff, 0x000000ff }, /* AC */
  910. { },
  911. };
  912. static const struct aspeed_gpio_config ast2500_config =
  913. /* 232 for simplicity, actual number is 228 (4-GPIO hole in GPIOAB) */
  914. { .nr_gpios = 232, .props = ast2500_bank_props, };
  915. static const struct aspeed_bank_props ast2600_bank_props[] = {
  916. /* input output */
  917. {4, 0xffffffff, 0x00ffffff}, /* Q/R/S/T */
  918. {5, 0xffffffff, 0xffffff00}, /* U/V/W/X */
  919. {6, 0x0000ffff, 0x0000ffff}, /* Y/Z */
  920. { },
  921. };
  922. static const struct aspeed_gpio_config ast2600_config =
  923. /*
  924. * ast2600 has two controllers one with 208 GPIOs and one with 36 GPIOs.
  925. * We expect ngpio being set in the device tree and this is a fallback
  926. * option.
  927. */
  928. { .nr_gpios = 208, .props = ast2600_bank_props, };
  929. static const struct of_device_id aspeed_gpio_of_table[] = {
  930. { .compatible = "aspeed,ast2400-gpio", .data = &ast2400_config, },
  931. { .compatible = "aspeed,ast2500-gpio", .data = &ast2500_config, },
  932. { .compatible = "aspeed,ast2600-gpio", .data = &ast2600_config, },
  933. {}
  934. };
  935. MODULE_DEVICE_TABLE(of, aspeed_gpio_of_table);
  936. static int __init aspeed_gpio_probe(struct platform_device *pdev)
  937. {
  938. const struct of_device_id *gpio_id;
  939. struct aspeed_gpio *gpio;
  940. int rc, i, banks, err;
  941. u32 ngpio;
  942. gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
  943. if (!gpio)
  944. return -ENOMEM;
  945. gpio->base = devm_platform_ioremap_resource(pdev, 0);
  946. if (IS_ERR(gpio->base))
  947. return PTR_ERR(gpio->base);
  948. raw_spin_lock_init(&gpio->lock);
  949. gpio_id = of_match_node(aspeed_gpio_of_table, pdev->dev.of_node);
  950. if (!gpio_id)
  951. return -EINVAL;
  952. gpio->clk = of_clk_get(pdev->dev.of_node, 0);
  953. if (IS_ERR(gpio->clk)) {
  954. dev_warn(&pdev->dev,
  955. "Failed to get clock from devicetree, debouncing disabled\n");
  956. gpio->clk = NULL;
  957. }
  958. gpio->config = gpio_id->data;
  959. gpio->chip.parent = &pdev->dev;
  960. err = of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpio);
  961. gpio->chip.ngpio = (u16) ngpio;
  962. if (err)
  963. gpio->chip.ngpio = gpio->config->nr_gpios;
  964. gpio->chip.direction_input = aspeed_gpio_dir_in;
  965. gpio->chip.direction_output = aspeed_gpio_dir_out;
  966. gpio->chip.get_direction = aspeed_gpio_get_direction;
  967. gpio->chip.request = aspeed_gpio_request;
  968. gpio->chip.free = aspeed_gpio_free;
  969. gpio->chip.get = aspeed_gpio_get;
  970. gpio->chip.set = aspeed_gpio_set;
  971. gpio->chip.set_config = aspeed_gpio_set_config;
  972. gpio->chip.label = dev_name(&pdev->dev);
  973. gpio->chip.base = -1;
  974. /* Allocate a cache of the output registers */
  975. banks = DIV_ROUND_UP(gpio->chip.ngpio, 32);
  976. gpio->dcache = devm_kcalloc(&pdev->dev,
  977. banks, sizeof(u32), GFP_KERNEL);
  978. if (!gpio->dcache)
  979. return -ENOMEM;
  980. /*
  981. * Populate it with initial values read from the HW and switch
  982. * all command sources to the ARM by default
  983. */
  984. for (i = 0; i < banks; i++) {
  985. const struct aspeed_gpio_bank *bank = &aspeed_gpio_banks[i];
  986. void __iomem *addr = bank_reg(gpio, bank, reg_rdata);
  987. gpio->dcache[i] = ioread32(addr);
  988. aspeed_gpio_change_cmd_source(gpio, bank, 0, GPIO_CMDSRC_ARM);
  989. aspeed_gpio_change_cmd_source(gpio, bank, 1, GPIO_CMDSRC_ARM);
  990. aspeed_gpio_change_cmd_source(gpio, bank, 2, GPIO_CMDSRC_ARM);
  991. aspeed_gpio_change_cmd_source(gpio, bank, 3, GPIO_CMDSRC_ARM);
  992. }
  993. /* Optionally set up an irqchip if there is an IRQ */
  994. rc = platform_get_irq(pdev, 0);
  995. if (rc > 0) {
  996. struct gpio_irq_chip *girq;
  997. gpio->irq = rc;
  998. girq = &gpio->chip.irq;
  999. girq->chip = &gpio->irqc;
  1000. girq->chip->name = dev_name(&pdev->dev);
  1001. girq->chip->irq_ack = aspeed_gpio_irq_ack;
  1002. girq->chip->irq_mask = aspeed_gpio_irq_mask;
  1003. girq->chip->irq_unmask = aspeed_gpio_irq_unmask;
  1004. girq->chip->irq_set_type = aspeed_gpio_set_type;
  1005. girq->parent_handler = aspeed_gpio_irq_handler;
  1006. girq->num_parents = 1;
  1007. girq->parents = devm_kcalloc(&pdev->dev, 1,
  1008. sizeof(*girq->parents),
  1009. GFP_KERNEL);
  1010. if (!girq->parents)
  1011. return -ENOMEM;
  1012. girq->parents[0] = gpio->irq;
  1013. girq->default_type = IRQ_TYPE_NONE;
  1014. girq->handler = handle_bad_irq;
  1015. girq->init_valid_mask = aspeed_init_irq_valid_mask;
  1016. }
  1017. gpio->offset_timer =
  1018. devm_kzalloc(&pdev->dev, gpio->chip.ngpio, GFP_KERNEL);
  1019. if (!gpio->offset_timer)
  1020. return -ENOMEM;
  1021. rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);
  1022. if (rc < 0)
  1023. return rc;
  1024. return 0;
  1025. }
  1026. static struct platform_driver aspeed_gpio_driver = {
  1027. .driver = {
  1028. .name = KBUILD_MODNAME,
  1029. .of_match_table = aspeed_gpio_of_table,
  1030. },
  1031. };
  1032. module_platform_driver_probe(aspeed_gpio_driver, aspeed_gpio_probe);
  1033. MODULE_DESCRIPTION("Aspeed GPIO Driver");
  1034. MODULE_LICENSE("GPL");