gpio-aspeed-sgpio.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright 2019 American Megatrends International LLC.
  4. *
  5. * Author: Karthikeyan Mani <karthikeyanm@amiindia.co.in>
  6. */
  7. #include <linux/bitfield.h>
  8. #include <linux/clk.h>
  9. #include <linux/gpio/driver.h>
  10. #include <linux/hashtable.h>
  11. #include <linux/init.h>
  12. #include <linux/io.h>
  13. #include <linux/kernel.h>
  14. #include <linux/module.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/spinlock.h>
  17. #include <linux/string.h>
  18. /*
  19. * MAX_NR_HW_GPIO represents the number of actual hardware-supported GPIOs (ie,
  20. * slots within the clocked serial GPIO data). Since each HW GPIO is both an
  21. * input and an output, we provide MAX_NR_HW_GPIO * 2 lines on our gpiochip
  22. * device.
  23. *
  24. * We use SGPIO_OUTPUT_OFFSET to define the split between the inputs and
  25. * outputs; the inputs start at line 0, the outputs start at OUTPUT_OFFSET.
  26. */
  27. #define MAX_NR_HW_SGPIO 80
  28. #define SGPIO_OUTPUT_OFFSET MAX_NR_HW_SGPIO
  29. #define ASPEED_SGPIO_CTRL 0x54
  30. #define ASPEED_SGPIO_PINS_MASK GENMASK(9, 6)
  31. #define ASPEED_SGPIO_CLK_DIV_MASK GENMASK(31, 16)
  32. #define ASPEED_SGPIO_ENABLE BIT(0)
  33. struct aspeed_sgpio {
  34. struct gpio_chip chip;
  35. struct clk *pclk;
  36. spinlock_t lock;
  37. void __iomem *base;
  38. int irq;
  39. int n_sgpio;
  40. };
  41. struct aspeed_sgpio_bank {
  42. uint16_t val_regs;
  43. uint16_t rdata_reg;
  44. uint16_t irq_regs;
  45. const char names[4][3];
  46. };
  47. /*
  48. * Note: The "value" register returns the input value when the GPIO is
  49. * configured as an input.
  50. *
  51. * The "rdata" register returns the output value when the GPIO is
  52. * configured as an output.
  53. */
  54. static const struct aspeed_sgpio_bank aspeed_sgpio_banks[] = {
  55. {
  56. .val_regs = 0x0000,
  57. .rdata_reg = 0x0070,
  58. .irq_regs = 0x0004,
  59. .names = { "A", "B", "C", "D" },
  60. },
  61. {
  62. .val_regs = 0x001C,
  63. .rdata_reg = 0x0074,
  64. .irq_regs = 0x0020,
  65. .names = { "E", "F", "G", "H" },
  66. },
  67. {
  68. .val_regs = 0x0038,
  69. .rdata_reg = 0x0078,
  70. .irq_regs = 0x003C,
  71. .names = { "I", "J" },
  72. },
  73. };
  74. enum aspeed_sgpio_reg {
  75. reg_val,
  76. reg_rdata,
  77. reg_irq_enable,
  78. reg_irq_type0,
  79. reg_irq_type1,
  80. reg_irq_type2,
  81. reg_irq_status,
  82. };
  83. #define GPIO_VAL_VALUE 0x00
  84. #define GPIO_IRQ_ENABLE 0x00
  85. #define GPIO_IRQ_TYPE0 0x04
  86. #define GPIO_IRQ_TYPE1 0x08
  87. #define GPIO_IRQ_TYPE2 0x0C
  88. #define GPIO_IRQ_STATUS 0x10
  89. static void __iomem *bank_reg(struct aspeed_sgpio *gpio,
  90. const struct aspeed_sgpio_bank *bank,
  91. const enum aspeed_sgpio_reg reg)
  92. {
  93. switch (reg) {
  94. case reg_val:
  95. return gpio->base + bank->val_regs + GPIO_VAL_VALUE;
  96. case reg_rdata:
  97. return gpio->base + bank->rdata_reg;
  98. case reg_irq_enable:
  99. return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE;
  100. case reg_irq_type0:
  101. return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0;
  102. case reg_irq_type1:
  103. return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1;
  104. case reg_irq_type2:
  105. return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2;
  106. case reg_irq_status:
  107. return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS;
  108. default:
  109. /* acturally if code runs to here, it's an error case */
  110. BUG();
  111. }
  112. }
  113. #define GPIO_BANK(x) ((x % SGPIO_OUTPUT_OFFSET) >> 5)
  114. #define GPIO_OFFSET(x) ((x % SGPIO_OUTPUT_OFFSET) & 0x1f)
  115. #define GPIO_BIT(x) BIT(GPIO_OFFSET(x))
  116. static const struct aspeed_sgpio_bank *to_bank(unsigned int offset)
  117. {
  118. unsigned int bank;
  119. bank = GPIO_BANK(offset);
  120. WARN_ON(bank >= ARRAY_SIZE(aspeed_sgpio_banks));
  121. return &aspeed_sgpio_banks[bank];
  122. }
  123. static int aspeed_sgpio_init_valid_mask(struct gpio_chip *gc,
  124. unsigned long *valid_mask, unsigned int ngpios)
  125. {
  126. struct aspeed_sgpio *sgpio = gpiochip_get_data(gc);
  127. int n = sgpio->n_sgpio;
  128. int c = SGPIO_OUTPUT_OFFSET - n;
  129. WARN_ON(ngpios < MAX_NR_HW_SGPIO * 2);
  130. /* input GPIOs in the lower range */
  131. bitmap_set(valid_mask, 0, n);
  132. bitmap_clear(valid_mask, n, c);
  133. /* output GPIOS above SGPIO_OUTPUT_OFFSET */
  134. bitmap_set(valid_mask, SGPIO_OUTPUT_OFFSET, n);
  135. bitmap_clear(valid_mask, SGPIO_OUTPUT_OFFSET + n, c);
  136. return 0;
  137. }
  138. static void aspeed_sgpio_irq_init_valid_mask(struct gpio_chip *gc,
  139. unsigned long *valid_mask, unsigned int ngpios)
  140. {
  141. struct aspeed_sgpio *sgpio = gpiochip_get_data(gc);
  142. int n = sgpio->n_sgpio;
  143. WARN_ON(ngpios < MAX_NR_HW_SGPIO * 2);
  144. /* input GPIOs in the lower range */
  145. bitmap_set(valid_mask, 0, n);
  146. bitmap_clear(valid_mask, n, ngpios - n);
  147. }
  148. static bool aspeed_sgpio_is_input(unsigned int offset)
  149. {
  150. return offset < SGPIO_OUTPUT_OFFSET;
  151. }
  152. static int aspeed_sgpio_get(struct gpio_chip *gc, unsigned int offset)
  153. {
  154. struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
  155. const struct aspeed_sgpio_bank *bank = to_bank(offset);
  156. unsigned long flags;
  157. enum aspeed_sgpio_reg reg;
  158. int rc = 0;
  159. spin_lock_irqsave(&gpio->lock, flags);
  160. reg = aspeed_sgpio_is_input(offset) ? reg_val : reg_rdata;
  161. rc = !!(ioread32(bank_reg(gpio, bank, reg)) & GPIO_BIT(offset));
  162. spin_unlock_irqrestore(&gpio->lock, flags);
  163. return rc;
  164. }
  165. static int sgpio_set_value(struct gpio_chip *gc, unsigned int offset, int val)
  166. {
  167. struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
  168. const struct aspeed_sgpio_bank *bank = to_bank(offset);
  169. void __iomem *addr_r, *addr_w;
  170. u32 reg = 0;
  171. if (aspeed_sgpio_is_input(offset))
  172. return -EINVAL;
  173. /* Since this is an output, read the cached value from rdata, then
  174. * update val. */
  175. addr_r = bank_reg(gpio, bank, reg_rdata);
  176. addr_w = bank_reg(gpio, bank, reg_val);
  177. reg = ioread32(addr_r);
  178. if (val)
  179. reg |= GPIO_BIT(offset);
  180. else
  181. reg &= ~GPIO_BIT(offset);
  182. iowrite32(reg, addr_w);
  183. return 0;
  184. }
  185. static void aspeed_sgpio_set(struct gpio_chip *gc, unsigned int offset, int val)
  186. {
  187. struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
  188. unsigned long flags;
  189. spin_lock_irqsave(&gpio->lock, flags);
  190. sgpio_set_value(gc, offset, val);
  191. spin_unlock_irqrestore(&gpio->lock, flags);
  192. }
  193. static int aspeed_sgpio_dir_in(struct gpio_chip *gc, unsigned int offset)
  194. {
  195. return aspeed_sgpio_is_input(offset) ? 0 : -EINVAL;
  196. }
  197. static int aspeed_sgpio_dir_out(struct gpio_chip *gc, unsigned int offset, int val)
  198. {
  199. struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
  200. unsigned long flags;
  201. int rc;
  202. /* No special action is required for setting the direction; we'll
  203. * error-out in sgpio_set_value if this isn't an output GPIO */
  204. spin_lock_irqsave(&gpio->lock, flags);
  205. rc = sgpio_set_value(gc, offset, val);
  206. spin_unlock_irqrestore(&gpio->lock, flags);
  207. return rc;
  208. }
  209. static int aspeed_sgpio_get_direction(struct gpio_chip *gc, unsigned int offset)
  210. {
  211. return !!aspeed_sgpio_is_input(offset);
  212. }
  213. static void irqd_to_aspeed_sgpio_data(struct irq_data *d,
  214. struct aspeed_sgpio **gpio,
  215. const struct aspeed_sgpio_bank **bank,
  216. u32 *bit, int *offset)
  217. {
  218. struct aspeed_sgpio *internal;
  219. *offset = irqd_to_hwirq(d);
  220. internal = irq_data_get_irq_chip_data(d);
  221. WARN_ON(!internal);
  222. *gpio = internal;
  223. *bank = to_bank(*offset);
  224. *bit = GPIO_BIT(*offset);
  225. }
  226. static void aspeed_sgpio_irq_ack(struct irq_data *d)
  227. {
  228. const struct aspeed_sgpio_bank *bank;
  229. struct aspeed_sgpio *gpio;
  230. unsigned long flags;
  231. void __iomem *status_addr;
  232. int offset;
  233. u32 bit;
  234. irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset);
  235. status_addr = bank_reg(gpio, bank, reg_irq_status);
  236. spin_lock_irqsave(&gpio->lock, flags);
  237. iowrite32(bit, status_addr);
  238. spin_unlock_irqrestore(&gpio->lock, flags);
  239. }
  240. static void aspeed_sgpio_irq_set_mask(struct irq_data *d, bool set)
  241. {
  242. const struct aspeed_sgpio_bank *bank;
  243. struct aspeed_sgpio *gpio;
  244. unsigned long flags;
  245. u32 reg, bit;
  246. void __iomem *addr;
  247. int offset;
  248. irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset);
  249. addr = bank_reg(gpio, bank, reg_irq_enable);
  250. spin_lock_irqsave(&gpio->lock, flags);
  251. reg = ioread32(addr);
  252. if (set)
  253. reg |= bit;
  254. else
  255. reg &= ~bit;
  256. iowrite32(reg, addr);
  257. spin_unlock_irqrestore(&gpio->lock, flags);
  258. }
  259. static void aspeed_sgpio_irq_mask(struct irq_data *d)
  260. {
  261. aspeed_sgpio_irq_set_mask(d, false);
  262. }
  263. static void aspeed_sgpio_irq_unmask(struct irq_data *d)
  264. {
  265. aspeed_sgpio_irq_set_mask(d, true);
  266. }
  267. static int aspeed_sgpio_set_type(struct irq_data *d, unsigned int type)
  268. {
  269. u32 type0 = 0;
  270. u32 type1 = 0;
  271. u32 type2 = 0;
  272. u32 bit, reg;
  273. const struct aspeed_sgpio_bank *bank;
  274. irq_flow_handler_t handler;
  275. struct aspeed_sgpio *gpio;
  276. unsigned long flags;
  277. void __iomem *addr;
  278. int offset;
  279. irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset);
  280. switch (type & IRQ_TYPE_SENSE_MASK) {
  281. case IRQ_TYPE_EDGE_BOTH:
  282. type2 |= bit;
  283. fallthrough;
  284. case IRQ_TYPE_EDGE_RISING:
  285. type0 |= bit;
  286. fallthrough;
  287. case IRQ_TYPE_EDGE_FALLING:
  288. handler = handle_edge_irq;
  289. break;
  290. case IRQ_TYPE_LEVEL_HIGH:
  291. type0 |= bit;
  292. fallthrough;
  293. case IRQ_TYPE_LEVEL_LOW:
  294. type1 |= bit;
  295. handler = handle_level_irq;
  296. break;
  297. default:
  298. return -EINVAL;
  299. }
  300. spin_lock_irqsave(&gpio->lock, flags);
  301. addr = bank_reg(gpio, bank, reg_irq_type0);
  302. reg = ioread32(addr);
  303. reg = (reg & ~bit) | type0;
  304. iowrite32(reg, addr);
  305. addr = bank_reg(gpio, bank, reg_irq_type1);
  306. reg = ioread32(addr);
  307. reg = (reg & ~bit) | type1;
  308. iowrite32(reg, addr);
  309. addr = bank_reg(gpio, bank, reg_irq_type2);
  310. reg = ioread32(addr);
  311. reg = (reg & ~bit) | type2;
  312. iowrite32(reg, addr);
  313. spin_unlock_irqrestore(&gpio->lock, flags);
  314. irq_set_handler_locked(d, handler);
  315. return 0;
  316. }
  317. static void aspeed_sgpio_irq_handler(struct irq_desc *desc)
  318. {
  319. struct gpio_chip *gc = irq_desc_get_handler_data(desc);
  320. struct irq_chip *ic = irq_desc_get_chip(desc);
  321. struct aspeed_sgpio *data = gpiochip_get_data(gc);
  322. unsigned int i, p, girq;
  323. unsigned long reg;
  324. chained_irq_enter(ic, desc);
  325. for (i = 0; i < ARRAY_SIZE(aspeed_sgpio_banks); i++) {
  326. const struct aspeed_sgpio_bank *bank = &aspeed_sgpio_banks[i];
  327. reg = ioread32(bank_reg(data, bank, reg_irq_status));
  328. for_each_set_bit(p, &reg, 32) {
  329. girq = irq_find_mapping(gc->irq.domain, i * 32 + p);
  330. generic_handle_irq(girq);
  331. }
  332. }
  333. chained_irq_exit(ic, desc);
  334. }
  335. static struct irq_chip aspeed_sgpio_irqchip = {
  336. .name = "aspeed-sgpio",
  337. .irq_ack = aspeed_sgpio_irq_ack,
  338. .irq_mask = aspeed_sgpio_irq_mask,
  339. .irq_unmask = aspeed_sgpio_irq_unmask,
  340. .irq_set_type = aspeed_sgpio_set_type,
  341. };
  342. static int aspeed_sgpio_setup_irqs(struct aspeed_sgpio *gpio,
  343. struct platform_device *pdev)
  344. {
  345. int rc, i;
  346. const struct aspeed_sgpio_bank *bank;
  347. struct gpio_irq_chip *irq;
  348. rc = platform_get_irq(pdev, 0);
  349. if (rc < 0)
  350. return rc;
  351. gpio->irq = rc;
  352. /* Disable IRQ and clear Interrupt status registers for all SGPIO Pins. */
  353. for (i = 0; i < ARRAY_SIZE(aspeed_sgpio_banks); i++) {
  354. bank = &aspeed_sgpio_banks[i];
  355. /* disable irq enable bits */
  356. iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_enable));
  357. /* clear status bits */
  358. iowrite32(0xffffffff, bank_reg(gpio, bank, reg_irq_status));
  359. }
  360. irq = &gpio->chip.irq;
  361. irq->chip = &aspeed_sgpio_irqchip;
  362. irq->init_valid_mask = aspeed_sgpio_irq_init_valid_mask;
  363. irq->handler = handle_bad_irq;
  364. irq->default_type = IRQ_TYPE_NONE;
  365. irq->parent_handler = aspeed_sgpio_irq_handler;
  366. irq->parent_handler_data = gpio;
  367. irq->parents = &gpio->irq;
  368. irq->num_parents = 1;
  369. /* Apply default IRQ settings */
  370. for (i = 0; i < ARRAY_SIZE(aspeed_sgpio_banks); i++) {
  371. bank = &aspeed_sgpio_banks[i];
  372. /* set falling or level-low irq */
  373. iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type0));
  374. /* trigger type is edge */
  375. iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type1));
  376. /* single edge trigger */
  377. iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type2));
  378. }
  379. return 0;
  380. }
  381. static const struct of_device_id aspeed_sgpio_of_table[] = {
  382. { .compatible = "aspeed,ast2400-sgpio" },
  383. { .compatible = "aspeed,ast2500-sgpio" },
  384. {}
  385. };
  386. MODULE_DEVICE_TABLE(of, aspeed_sgpio_of_table);
  387. static int __init aspeed_sgpio_probe(struct platform_device *pdev)
  388. {
  389. struct aspeed_sgpio *gpio;
  390. u32 nr_gpios, sgpio_freq, sgpio_clk_div;
  391. int rc;
  392. unsigned long apb_freq;
  393. gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
  394. if (!gpio)
  395. return -ENOMEM;
  396. gpio->base = devm_platform_ioremap_resource(pdev, 0);
  397. if (IS_ERR(gpio->base))
  398. return PTR_ERR(gpio->base);
  399. rc = of_property_read_u32(pdev->dev.of_node, "ngpios", &nr_gpios);
  400. if (rc < 0) {
  401. dev_err(&pdev->dev, "Could not read ngpios property\n");
  402. return -EINVAL;
  403. } else if (nr_gpios > MAX_NR_HW_SGPIO) {
  404. dev_err(&pdev->dev, "Number of GPIOs exceeds the maximum of %d: %d\n",
  405. MAX_NR_HW_SGPIO, nr_gpios);
  406. return -EINVAL;
  407. }
  408. gpio->n_sgpio = nr_gpios;
  409. rc = of_property_read_u32(pdev->dev.of_node, "bus-frequency", &sgpio_freq);
  410. if (rc < 0) {
  411. dev_err(&pdev->dev, "Could not read bus-frequency property\n");
  412. return -EINVAL;
  413. }
  414. gpio->pclk = devm_clk_get(&pdev->dev, NULL);
  415. if (IS_ERR(gpio->pclk)) {
  416. dev_err(&pdev->dev, "devm_clk_get failed\n");
  417. return PTR_ERR(gpio->pclk);
  418. }
  419. apb_freq = clk_get_rate(gpio->pclk);
  420. /*
  421. * From the datasheet,
  422. * SGPIO period = 1/PCLK * 2 * (GPIO254[31:16] + 1)
  423. * period = 2 * (GPIO254[31:16] + 1) / PCLK
  424. * frequency = 1 / (2 * (GPIO254[31:16] + 1) / PCLK)
  425. * frequency = PCLK / (2 * (GPIO254[31:16] + 1))
  426. * frequency * 2 * (GPIO254[31:16] + 1) = PCLK
  427. * GPIO254[31:16] = PCLK / (frequency * 2) - 1
  428. */
  429. if (sgpio_freq == 0)
  430. return -EINVAL;
  431. sgpio_clk_div = (apb_freq / (sgpio_freq * 2)) - 1;
  432. if (sgpio_clk_div > (1 << 16) - 1)
  433. return -EINVAL;
  434. iowrite32(FIELD_PREP(ASPEED_SGPIO_CLK_DIV_MASK, sgpio_clk_div) |
  435. FIELD_PREP(ASPEED_SGPIO_PINS_MASK, (nr_gpios / 8)) |
  436. ASPEED_SGPIO_ENABLE,
  437. gpio->base + ASPEED_SGPIO_CTRL);
  438. spin_lock_init(&gpio->lock);
  439. gpio->chip.parent = &pdev->dev;
  440. gpio->chip.ngpio = MAX_NR_HW_SGPIO * 2;
  441. gpio->chip.init_valid_mask = aspeed_sgpio_init_valid_mask;
  442. gpio->chip.direction_input = aspeed_sgpio_dir_in;
  443. gpio->chip.direction_output = aspeed_sgpio_dir_out;
  444. gpio->chip.get_direction = aspeed_sgpio_get_direction;
  445. gpio->chip.request = NULL;
  446. gpio->chip.free = NULL;
  447. gpio->chip.get = aspeed_sgpio_get;
  448. gpio->chip.set = aspeed_sgpio_set;
  449. gpio->chip.set_config = NULL;
  450. gpio->chip.label = dev_name(&pdev->dev);
  451. gpio->chip.base = -1;
  452. aspeed_sgpio_setup_irqs(gpio, pdev);
  453. rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);
  454. if (rc < 0)
  455. return rc;
  456. return 0;
  457. }
  458. static struct platform_driver aspeed_sgpio_driver = {
  459. .driver = {
  460. .name = KBUILD_MODNAME,
  461. .of_match_table = aspeed_sgpio_of_table,
  462. },
  463. };
  464. module_platform_driver_probe(aspeed_sgpio_driver, aspeed_sgpio_probe);
  465. MODULE_DESCRIPTION("Aspeed Serial GPIO Driver");
  466. MODULE_LICENSE("GPL");