gpio-amd8111.c 6.8 KB

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  1. /*
  2. * GPIO driver for AMD 8111 south bridges
  3. *
  4. * Copyright (c) 2012 Dmitry Eremin-Solenikov
  5. *
  6. * Based on the AMD RNG driver:
  7. * Copyright 2005 (c) MontaVista Software, Inc.
  8. * with the majority of the code coming from:
  9. *
  10. * Hardware driver for the Intel/AMD/VIA Random Number Generators (RNG)
  11. * (c) Copyright 2003 Red Hat Inc <jgarzik@redhat.com>
  12. *
  13. * derived from
  14. *
  15. * Hardware driver for the AMD 768 Random Number Generator (RNG)
  16. * (c) Copyright 2001 Red Hat Inc
  17. *
  18. * derived from
  19. *
  20. * Hardware driver for Intel i810 Random Number Generator (RNG)
  21. * Copyright 2000,2001 Jeff Garzik <jgarzik@pobox.com>
  22. * Copyright 2000,2001 Philipp Rumpf <prumpf@mandrakesoft.com>
  23. *
  24. * This file is licensed under the terms of the GNU General Public
  25. * License version 2. This program is licensed "as is" without any
  26. * warranty of any kind, whether express or implied.
  27. */
  28. #include <linux/ioport.h>
  29. #include <linux/module.h>
  30. #include <linux/kernel.h>
  31. #include <linux/gpio/driver.h>
  32. #include <linux/pci.h>
  33. #include <linux/spinlock.h>
  34. #define PMBASE_OFFSET 0xb0
  35. #define PMBASE_SIZE 0x30
  36. #define AMD_REG_GPIO(i) (0x10 + (i))
  37. #define AMD_GPIO_LTCH_STS 0x40 /* Latch status, w1 */
  38. #define AMD_GPIO_RTIN 0x20 /* Real Time in, ro */
  39. #define AMD_GPIO_DEBOUNCE 0x10 /* Debounce, rw */
  40. #define AMD_GPIO_MODE_MASK 0x0c /* Pin Mode Select, rw */
  41. #define AMD_GPIO_MODE_IN 0x00
  42. #define AMD_GPIO_MODE_OUT 0x04
  43. /* Enable alternative (e.g. clkout, IRQ, etc) function of the pin */
  44. #define AMD_GPIO_MODE_ALTFN 0x08 /* Or 0x09 */
  45. #define AMD_GPIO_X_MASK 0x03 /* In/Out specific, rw */
  46. #define AMD_GPIO_X_IN_ACTIVEHI 0x01 /* Active High */
  47. #define AMD_GPIO_X_IN_LATCH 0x02 /* Latched version is selected */
  48. #define AMD_GPIO_X_OUT_LOW 0x00
  49. #define AMD_GPIO_X_OUT_HI 0x01
  50. #define AMD_GPIO_X_OUT_CLK0 0x02
  51. #define AMD_GPIO_X_OUT_CLK1 0x03
  52. /*
  53. * Data for PCI driver interface
  54. *
  55. * This data only exists for exporting the supported
  56. * PCI ids via MODULE_DEVICE_TABLE. We do not actually
  57. * register a pci_driver, because someone else might one day
  58. * want to register another driver on the same PCI id.
  59. */
  60. static const struct pci_device_id pci_tbl[] = {
  61. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS), 0 },
  62. { 0, }, /* terminate list */
  63. };
  64. MODULE_DEVICE_TABLE(pci, pci_tbl);
  65. struct amd_gpio {
  66. struct gpio_chip chip;
  67. u32 pmbase;
  68. void __iomem *pm;
  69. struct pci_dev *pdev;
  70. spinlock_t lock; /* guards hw registers and orig table */
  71. u8 orig[32];
  72. };
  73. static int amd_gpio_request(struct gpio_chip *chip, unsigned offset)
  74. {
  75. struct amd_gpio *agp = gpiochip_get_data(chip);
  76. agp->orig[offset] = ioread8(agp->pm + AMD_REG_GPIO(offset)) &
  77. (AMD_GPIO_DEBOUNCE | AMD_GPIO_MODE_MASK | AMD_GPIO_X_MASK);
  78. dev_dbg(&agp->pdev->dev, "Requested gpio %d, data %x\n", offset, agp->orig[offset]);
  79. return 0;
  80. }
  81. static void amd_gpio_free(struct gpio_chip *chip, unsigned offset)
  82. {
  83. struct amd_gpio *agp = gpiochip_get_data(chip);
  84. dev_dbg(&agp->pdev->dev, "Freed gpio %d, data %x\n", offset, agp->orig[offset]);
  85. iowrite8(agp->orig[offset], agp->pm + AMD_REG_GPIO(offset));
  86. }
  87. static void amd_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
  88. {
  89. struct amd_gpio *agp = gpiochip_get_data(chip);
  90. u8 temp;
  91. unsigned long flags;
  92. spin_lock_irqsave(&agp->lock, flags);
  93. temp = ioread8(agp->pm + AMD_REG_GPIO(offset));
  94. temp = (temp & AMD_GPIO_DEBOUNCE) | AMD_GPIO_MODE_OUT | (value ? AMD_GPIO_X_OUT_HI : AMD_GPIO_X_OUT_LOW);
  95. iowrite8(temp, agp->pm + AMD_REG_GPIO(offset));
  96. spin_unlock_irqrestore(&agp->lock, flags);
  97. dev_dbg(&agp->pdev->dev, "Setting gpio %d, value %d, reg=%02x\n", offset, !!value, temp);
  98. }
  99. static int amd_gpio_get(struct gpio_chip *chip, unsigned offset)
  100. {
  101. struct amd_gpio *agp = gpiochip_get_data(chip);
  102. u8 temp;
  103. temp = ioread8(agp->pm + AMD_REG_GPIO(offset));
  104. dev_dbg(&agp->pdev->dev, "Getting gpio %d, reg=%02x\n", offset, temp);
  105. return (temp & AMD_GPIO_RTIN) ? 1 : 0;
  106. }
  107. static int amd_gpio_dirout(struct gpio_chip *chip, unsigned offset, int value)
  108. {
  109. struct amd_gpio *agp = gpiochip_get_data(chip);
  110. u8 temp;
  111. unsigned long flags;
  112. spin_lock_irqsave(&agp->lock, flags);
  113. temp = ioread8(agp->pm + AMD_REG_GPIO(offset));
  114. temp = (temp & AMD_GPIO_DEBOUNCE) | AMD_GPIO_MODE_OUT | (value ? AMD_GPIO_X_OUT_HI : AMD_GPIO_X_OUT_LOW);
  115. iowrite8(temp, agp->pm + AMD_REG_GPIO(offset));
  116. spin_unlock_irqrestore(&agp->lock, flags);
  117. dev_dbg(&agp->pdev->dev, "Dirout gpio %d, value %d, reg=%02x\n", offset, !!value, temp);
  118. return 0;
  119. }
  120. static int amd_gpio_dirin(struct gpio_chip *chip, unsigned offset)
  121. {
  122. struct amd_gpio *agp = gpiochip_get_data(chip);
  123. u8 temp;
  124. unsigned long flags;
  125. spin_lock_irqsave(&agp->lock, flags);
  126. temp = ioread8(agp->pm + AMD_REG_GPIO(offset));
  127. temp = (temp & AMD_GPIO_DEBOUNCE) | AMD_GPIO_MODE_IN;
  128. iowrite8(temp, agp->pm + AMD_REG_GPIO(offset));
  129. spin_unlock_irqrestore(&agp->lock, flags);
  130. dev_dbg(&agp->pdev->dev, "Dirin gpio %d, reg=%02x\n", offset, temp);
  131. return 0;
  132. }
  133. static struct amd_gpio gp = {
  134. .chip = {
  135. .label = "AMD GPIO",
  136. .owner = THIS_MODULE,
  137. .base = -1,
  138. .ngpio = 32,
  139. .request = amd_gpio_request,
  140. .free = amd_gpio_free,
  141. .set = amd_gpio_set,
  142. .get = amd_gpio_get,
  143. .direction_output = amd_gpio_dirout,
  144. .direction_input = amd_gpio_dirin,
  145. },
  146. };
  147. static int __init amd_gpio_init(void)
  148. {
  149. int err = -ENODEV;
  150. struct pci_dev *pdev = NULL;
  151. const struct pci_device_id *ent;
  152. /* We look for our device - AMD South Bridge
  153. * I don't know about a system with two such bridges,
  154. * so we can assume that there is max. one device.
  155. *
  156. * We can't use plain pci_driver mechanism,
  157. * as the device is really a multiple function device,
  158. * main driver that binds to the pci_device is an smbus
  159. * driver and have to find & bind to the device this way.
  160. */
  161. for_each_pci_dev(pdev) {
  162. ent = pci_match_id(pci_tbl, pdev);
  163. if (ent)
  164. goto found;
  165. }
  166. /* Device not found. */
  167. goto out;
  168. found:
  169. err = pci_read_config_dword(pdev, 0x58, &gp.pmbase);
  170. if (err)
  171. goto out;
  172. err = -EIO;
  173. gp.pmbase &= 0x0000FF00;
  174. if (gp.pmbase == 0)
  175. goto out;
  176. if (!devm_request_region(&pdev->dev, gp.pmbase + PMBASE_OFFSET,
  177. PMBASE_SIZE, "AMD GPIO")) {
  178. dev_err(&pdev->dev, "AMD GPIO region 0x%x already in use!\n",
  179. gp.pmbase + PMBASE_OFFSET);
  180. err = -EBUSY;
  181. goto out;
  182. }
  183. gp.pm = ioport_map(gp.pmbase + PMBASE_OFFSET, PMBASE_SIZE);
  184. if (!gp.pm) {
  185. dev_err(&pdev->dev, "Couldn't map io port into io memory\n");
  186. err = -ENOMEM;
  187. goto out;
  188. }
  189. gp.pdev = pdev;
  190. gp.chip.parent = &pdev->dev;
  191. spin_lock_init(&gp.lock);
  192. printk(KERN_INFO "AMD-8111 GPIO detected\n");
  193. err = gpiochip_add_data(&gp.chip, &gp);
  194. if (err) {
  195. printk(KERN_ERR "GPIO registering failed (%d)\n",
  196. err);
  197. ioport_unmap(gp.pm);
  198. goto out;
  199. }
  200. out:
  201. return err;
  202. }
  203. static void __exit amd_gpio_exit(void)
  204. {
  205. gpiochip_remove(&gp.chip);
  206. ioport_unmap(gp.pm);
  207. }
  208. module_init(amd_gpio_init);
  209. module_exit(amd_gpio_exit);
  210. MODULE_AUTHOR("The Linux Kernel team");
  211. MODULE_DESCRIPTION("GPIO driver for AMD chipsets");
  212. MODULE_LICENSE("GPL");