gpio-amd-fch.c 4.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * GPIO driver for the AMD G series FCH (eg. GX-412TC)
  4. *
  5. * Copyright (C) 2018 metux IT consult
  6. * Author: Enrico Weigelt, metux IT consult <info@metux.net>
  7. *
  8. */
  9. #include <linux/err.h>
  10. #include <linux/io.h>
  11. #include <linux/kernel.h>
  12. #include <linux/module.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/gpio/driver.h>
  15. #include <linux/platform_data/gpio/gpio-amd-fch.h>
  16. #include <linux/spinlock.h>
  17. #define AMD_FCH_MMIO_BASE 0xFED80000
  18. #define AMD_FCH_GPIO_BANK0_BASE 0x1500
  19. #define AMD_FCH_GPIO_SIZE 0x0300
  20. #define AMD_FCH_GPIO_FLAG_DIRECTION BIT(23)
  21. #define AMD_FCH_GPIO_FLAG_WRITE BIT(22)
  22. #define AMD_FCH_GPIO_FLAG_READ BIT(16)
  23. static const struct resource amd_fch_gpio_iores =
  24. DEFINE_RES_MEM_NAMED(
  25. AMD_FCH_MMIO_BASE + AMD_FCH_GPIO_BANK0_BASE,
  26. AMD_FCH_GPIO_SIZE,
  27. "amd-fch-gpio-iomem");
  28. struct amd_fch_gpio_priv {
  29. struct gpio_chip gc;
  30. void __iomem *base;
  31. struct amd_fch_gpio_pdata *pdata;
  32. spinlock_t lock;
  33. };
  34. static void __iomem *amd_fch_gpio_addr(struct amd_fch_gpio_priv *priv,
  35. unsigned int gpio)
  36. {
  37. return priv->base + priv->pdata->gpio_reg[gpio]*sizeof(u32);
  38. }
  39. static int amd_fch_gpio_direction_input(struct gpio_chip *gc,
  40. unsigned int offset)
  41. {
  42. unsigned long flags;
  43. struct amd_fch_gpio_priv *priv = gpiochip_get_data(gc);
  44. void __iomem *ptr = amd_fch_gpio_addr(priv, offset);
  45. spin_lock_irqsave(&priv->lock, flags);
  46. writel_relaxed(readl_relaxed(ptr) & ~AMD_FCH_GPIO_FLAG_DIRECTION, ptr);
  47. spin_unlock_irqrestore(&priv->lock, flags);
  48. return 0;
  49. }
  50. static int amd_fch_gpio_direction_output(struct gpio_chip *gc,
  51. unsigned int gpio, int value)
  52. {
  53. unsigned long flags;
  54. struct amd_fch_gpio_priv *priv = gpiochip_get_data(gc);
  55. void __iomem *ptr = amd_fch_gpio_addr(priv, gpio);
  56. u32 val;
  57. spin_lock_irqsave(&priv->lock, flags);
  58. val = readl_relaxed(ptr);
  59. if (value)
  60. val |= AMD_FCH_GPIO_FLAG_WRITE;
  61. else
  62. val &= ~AMD_FCH_GPIO_FLAG_WRITE;
  63. writel_relaxed(val | AMD_FCH_GPIO_FLAG_DIRECTION, ptr);
  64. spin_unlock_irqrestore(&priv->lock, flags);
  65. return 0;
  66. }
  67. static int amd_fch_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio)
  68. {
  69. int ret;
  70. unsigned long flags;
  71. struct amd_fch_gpio_priv *priv = gpiochip_get_data(gc);
  72. void __iomem *ptr = amd_fch_gpio_addr(priv, gpio);
  73. spin_lock_irqsave(&priv->lock, flags);
  74. ret = (readl_relaxed(ptr) & AMD_FCH_GPIO_FLAG_DIRECTION);
  75. spin_unlock_irqrestore(&priv->lock, flags);
  76. return ret ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
  77. }
  78. static void amd_fch_gpio_set(struct gpio_chip *gc,
  79. unsigned int gpio, int value)
  80. {
  81. unsigned long flags;
  82. struct amd_fch_gpio_priv *priv = gpiochip_get_data(gc);
  83. void __iomem *ptr = amd_fch_gpio_addr(priv, gpio);
  84. u32 mask;
  85. spin_lock_irqsave(&priv->lock, flags);
  86. mask = readl_relaxed(ptr);
  87. if (value)
  88. mask |= AMD_FCH_GPIO_FLAG_WRITE;
  89. else
  90. mask &= ~AMD_FCH_GPIO_FLAG_WRITE;
  91. writel_relaxed(mask, ptr);
  92. spin_unlock_irqrestore(&priv->lock, flags);
  93. }
  94. static int amd_fch_gpio_get(struct gpio_chip *gc,
  95. unsigned int offset)
  96. {
  97. unsigned long flags;
  98. int ret;
  99. struct amd_fch_gpio_priv *priv = gpiochip_get_data(gc);
  100. void __iomem *ptr = amd_fch_gpio_addr(priv, offset);
  101. spin_lock_irqsave(&priv->lock, flags);
  102. ret = (readl_relaxed(ptr) & AMD_FCH_GPIO_FLAG_READ);
  103. spin_unlock_irqrestore(&priv->lock, flags);
  104. return ret;
  105. }
  106. static int amd_fch_gpio_request(struct gpio_chip *chip,
  107. unsigned int gpio_pin)
  108. {
  109. return 0;
  110. }
  111. static int amd_fch_gpio_probe(struct platform_device *pdev)
  112. {
  113. struct amd_fch_gpio_priv *priv;
  114. struct amd_fch_gpio_pdata *pdata;
  115. pdata = dev_get_platdata(&pdev->dev);
  116. if (!pdata) {
  117. dev_err(&pdev->dev, "no platform_data\n");
  118. return -ENOENT;
  119. }
  120. priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
  121. if (!priv)
  122. return -ENOMEM;
  123. priv->pdata = pdata;
  124. priv->gc.owner = THIS_MODULE;
  125. priv->gc.parent = &pdev->dev;
  126. priv->gc.label = dev_name(&pdev->dev);
  127. priv->gc.ngpio = priv->pdata->gpio_num;
  128. priv->gc.names = priv->pdata->gpio_names;
  129. priv->gc.base = -1;
  130. priv->gc.request = amd_fch_gpio_request;
  131. priv->gc.direction_input = amd_fch_gpio_direction_input;
  132. priv->gc.direction_output = amd_fch_gpio_direction_output;
  133. priv->gc.get_direction = amd_fch_gpio_get_direction;
  134. priv->gc.get = amd_fch_gpio_get;
  135. priv->gc.set = amd_fch_gpio_set;
  136. spin_lock_init(&priv->lock);
  137. priv->base = devm_ioremap_resource(&pdev->dev, &amd_fch_gpio_iores);
  138. if (IS_ERR(priv->base))
  139. return PTR_ERR(priv->base);
  140. platform_set_drvdata(pdev, priv);
  141. return devm_gpiochip_add_data(&pdev->dev, &priv->gc, priv);
  142. }
  143. static struct platform_driver amd_fch_gpio_driver = {
  144. .driver = {
  145. .name = AMD_FCH_GPIO_DRIVER_NAME,
  146. },
  147. .probe = amd_fch_gpio_probe,
  148. };
  149. module_platform_driver(amd_fch_gpio_driver);
  150. MODULE_AUTHOR("Enrico Weigelt, metux IT consult <info@metux.net>");
  151. MODULE_DESCRIPTION("AMD G-series FCH GPIO driver");
  152. MODULE_LICENSE("GPL");
  153. MODULE_ALIAS("platform:" AMD_FCH_GPIO_DRIVER_NAME);