gpio-altera.c 9.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (C) 2013 Altera Corporation
  4. * Based on gpio-mpc8xxx.c
  5. */
  6. #include <linux/io.h>
  7. #include <linux/module.h>
  8. #include <linux/gpio/driver.h>
  9. #include <linux/of_gpio.h> /* For of_mm_gpio_chip */
  10. #include <linux/platform_device.h>
  11. #define ALTERA_GPIO_MAX_NGPIO 32
  12. #define ALTERA_GPIO_DATA 0x0
  13. #define ALTERA_GPIO_DIR 0x4
  14. #define ALTERA_GPIO_IRQ_MASK 0x8
  15. #define ALTERA_GPIO_EDGE_CAP 0xc
  16. /**
  17. * struct altera_gpio_chip
  18. * @mmchip : memory mapped chip structure.
  19. * @gpio_lock : synchronization lock so that new irq/set/get requests
  20. * will be blocked until the current one completes.
  21. * @interrupt_trigger : specifies the hardware configured IRQ trigger type
  22. * (rising, falling, both, high)
  23. * @mapped_irq : kernel mapped irq number.
  24. * @irq_chip : IRQ chip configuration
  25. */
  26. struct altera_gpio_chip {
  27. struct of_mm_gpio_chip mmchip;
  28. raw_spinlock_t gpio_lock;
  29. int interrupt_trigger;
  30. int mapped_irq;
  31. struct irq_chip irq_chip;
  32. };
  33. static void altera_gpio_irq_unmask(struct irq_data *d)
  34. {
  35. struct altera_gpio_chip *altera_gc;
  36. struct of_mm_gpio_chip *mm_gc;
  37. unsigned long flags;
  38. u32 intmask;
  39. altera_gc = gpiochip_get_data(irq_data_get_irq_chip_data(d));
  40. mm_gc = &altera_gc->mmchip;
  41. raw_spin_lock_irqsave(&altera_gc->gpio_lock, flags);
  42. intmask = readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
  43. /* Set ALTERA_GPIO_IRQ_MASK bit to unmask */
  44. intmask |= BIT(irqd_to_hwirq(d));
  45. writel(intmask, mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
  46. raw_spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
  47. }
  48. static void altera_gpio_irq_mask(struct irq_data *d)
  49. {
  50. struct altera_gpio_chip *altera_gc;
  51. struct of_mm_gpio_chip *mm_gc;
  52. unsigned long flags;
  53. u32 intmask;
  54. altera_gc = gpiochip_get_data(irq_data_get_irq_chip_data(d));
  55. mm_gc = &altera_gc->mmchip;
  56. raw_spin_lock_irqsave(&altera_gc->gpio_lock, flags);
  57. intmask = readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
  58. /* Clear ALTERA_GPIO_IRQ_MASK bit to mask */
  59. intmask &= ~BIT(irqd_to_hwirq(d));
  60. writel(intmask, mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
  61. raw_spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
  62. }
  63. /*
  64. * This controller's IRQ type is synthesized in hardware, so this function
  65. * just checks if the requested set_type matches the synthesized IRQ type
  66. */
  67. static int altera_gpio_irq_set_type(struct irq_data *d,
  68. unsigned int type)
  69. {
  70. struct altera_gpio_chip *altera_gc;
  71. altera_gc = gpiochip_get_data(irq_data_get_irq_chip_data(d));
  72. if (type == IRQ_TYPE_NONE) {
  73. irq_set_handler_locked(d, handle_bad_irq);
  74. return 0;
  75. }
  76. if (type == altera_gc->interrupt_trigger) {
  77. if (type == IRQ_TYPE_LEVEL_HIGH)
  78. irq_set_handler_locked(d, handle_level_irq);
  79. else
  80. irq_set_handler_locked(d, handle_simple_irq);
  81. return 0;
  82. }
  83. irq_set_handler_locked(d, handle_bad_irq);
  84. return -EINVAL;
  85. }
  86. static unsigned int altera_gpio_irq_startup(struct irq_data *d)
  87. {
  88. altera_gpio_irq_unmask(d);
  89. return 0;
  90. }
  91. static int altera_gpio_get(struct gpio_chip *gc, unsigned offset)
  92. {
  93. struct of_mm_gpio_chip *mm_gc;
  94. mm_gc = to_of_mm_gpio_chip(gc);
  95. return !!(readl(mm_gc->regs + ALTERA_GPIO_DATA) & BIT(offset));
  96. }
  97. static void altera_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
  98. {
  99. struct of_mm_gpio_chip *mm_gc;
  100. struct altera_gpio_chip *chip;
  101. unsigned long flags;
  102. unsigned int data_reg;
  103. mm_gc = to_of_mm_gpio_chip(gc);
  104. chip = gpiochip_get_data(gc);
  105. raw_spin_lock_irqsave(&chip->gpio_lock, flags);
  106. data_reg = readl(mm_gc->regs + ALTERA_GPIO_DATA);
  107. if (value)
  108. data_reg |= BIT(offset);
  109. else
  110. data_reg &= ~BIT(offset);
  111. writel(data_reg, mm_gc->regs + ALTERA_GPIO_DATA);
  112. raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);
  113. }
  114. static int altera_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
  115. {
  116. struct of_mm_gpio_chip *mm_gc;
  117. struct altera_gpio_chip *chip;
  118. unsigned long flags;
  119. unsigned int gpio_ddr;
  120. mm_gc = to_of_mm_gpio_chip(gc);
  121. chip = gpiochip_get_data(gc);
  122. raw_spin_lock_irqsave(&chip->gpio_lock, flags);
  123. /* Set pin as input, assumes software controlled IP */
  124. gpio_ddr = readl(mm_gc->regs + ALTERA_GPIO_DIR);
  125. gpio_ddr &= ~BIT(offset);
  126. writel(gpio_ddr, mm_gc->regs + ALTERA_GPIO_DIR);
  127. raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);
  128. return 0;
  129. }
  130. static int altera_gpio_direction_output(struct gpio_chip *gc,
  131. unsigned offset, int value)
  132. {
  133. struct of_mm_gpio_chip *mm_gc;
  134. struct altera_gpio_chip *chip;
  135. unsigned long flags;
  136. unsigned int data_reg, gpio_ddr;
  137. mm_gc = to_of_mm_gpio_chip(gc);
  138. chip = gpiochip_get_data(gc);
  139. raw_spin_lock_irqsave(&chip->gpio_lock, flags);
  140. /* Sets the GPIO value */
  141. data_reg = readl(mm_gc->regs + ALTERA_GPIO_DATA);
  142. if (value)
  143. data_reg |= BIT(offset);
  144. else
  145. data_reg &= ~BIT(offset);
  146. writel(data_reg, mm_gc->regs + ALTERA_GPIO_DATA);
  147. /* Set pin as output, assumes software controlled IP */
  148. gpio_ddr = readl(mm_gc->regs + ALTERA_GPIO_DIR);
  149. gpio_ddr |= BIT(offset);
  150. writel(gpio_ddr, mm_gc->regs + ALTERA_GPIO_DIR);
  151. raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);
  152. return 0;
  153. }
  154. static void altera_gpio_irq_edge_handler(struct irq_desc *desc)
  155. {
  156. struct altera_gpio_chip *altera_gc;
  157. struct irq_chip *chip;
  158. struct of_mm_gpio_chip *mm_gc;
  159. struct irq_domain *irqdomain;
  160. unsigned long status;
  161. int i;
  162. altera_gc = gpiochip_get_data(irq_desc_get_handler_data(desc));
  163. chip = irq_desc_get_chip(desc);
  164. mm_gc = &altera_gc->mmchip;
  165. irqdomain = altera_gc->mmchip.gc.irq.domain;
  166. chained_irq_enter(chip, desc);
  167. while ((status =
  168. (readl(mm_gc->regs + ALTERA_GPIO_EDGE_CAP) &
  169. readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK)))) {
  170. writel(status, mm_gc->regs + ALTERA_GPIO_EDGE_CAP);
  171. for_each_set_bit(i, &status, mm_gc->gc.ngpio) {
  172. generic_handle_irq(irq_find_mapping(irqdomain, i));
  173. }
  174. }
  175. chained_irq_exit(chip, desc);
  176. }
  177. static void altera_gpio_irq_leveL_high_handler(struct irq_desc *desc)
  178. {
  179. struct altera_gpio_chip *altera_gc;
  180. struct irq_chip *chip;
  181. struct of_mm_gpio_chip *mm_gc;
  182. struct irq_domain *irqdomain;
  183. unsigned long status;
  184. int i;
  185. altera_gc = gpiochip_get_data(irq_desc_get_handler_data(desc));
  186. chip = irq_desc_get_chip(desc);
  187. mm_gc = &altera_gc->mmchip;
  188. irqdomain = altera_gc->mmchip.gc.irq.domain;
  189. chained_irq_enter(chip, desc);
  190. status = readl(mm_gc->regs + ALTERA_GPIO_DATA);
  191. status &= readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
  192. for_each_set_bit(i, &status, mm_gc->gc.ngpio) {
  193. generic_handle_irq(irq_find_mapping(irqdomain, i));
  194. }
  195. chained_irq_exit(chip, desc);
  196. }
  197. static int altera_gpio_probe(struct platform_device *pdev)
  198. {
  199. struct device_node *node = pdev->dev.of_node;
  200. int reg, ret;
  201. struct altera_gpio_chip *altera_gc;
  202. struct gpio_irq_chip *girq;
  203. altera_gc = devm_kzalloc(&pdev->dev, sizeof(*altera_gc), GFP_KERNEL);
  204. if (!altera_gc)
  205. return -ENOMEM;
  206. raw_spin_lock_init(&altera_gc->gpio_lock);
  207. if (of_property_read_u32(node, "altr,ngpio", &reg))
  208. /* By default assume maximum ngpio */
  209. altera_gc->mmchip.gc.ngpio = ALTERA_GPIO_MAX_NGPIO;
  210. else
  211. altera_gc->mmchip.gc.ngpio = reg;
  212. if (altera_gc->mmchip.gc.ngpio > ALTERA_GPIO_MAX_NGPIO) {
  213. dev_warn(&pdev->dev,
  214. "ngpio is greater than %d, defaulting to %d\n",
  215. ALTERA_GPIO_MAX_NGPIO, ALTERA_GPIO_MAX_NGPIO);
  216. altera_gc->mmchip.gc.ngpio = ALTERA_GPIO_MAX_NGPIO;
  217. }
  218. altera_gc->mmchip.gc.direction_input = altera_gpio_direction_input;
  219. altera_gc->mmchip.gc.direction_output = altera_gpio_direction_output;
  220. altera_gc->mmchip.gc.get = altera_gpio_get;
  221. altera_gc->mmchip.gc.set = altera_gpio_set;
  222. altera_gc->mmchip.gc.owner = THIS_MODULE;
  223. altera_gc->mmchip.gc.parent = &pdev->dev;
  224. altera_gc->mapped_irq = platform_get_irq_optional(pdev, 0);
  225. if (altera_gc->mapped_irq < 0)
  226. goto skip_irq;
  227. if (of_property_read_u32(node, "altr,interrupt-type", &reg)) {
  228. dev_err(&pdev->dev,
  229. "altr,interrupt-type value not set in device tree\n");
  230. return -EINVAL;
  231. }
  232. altera_gc->interrupt_trigger = reg;
  233. altera_gc->irq_chip.name = "altera-gpio";
  234. altera_gc->irq_chip.irq_mask = altera_gpio_irq_mask;
  235. altera_gc->irq_chip.irq_unmask = altera_gpio_irq_unmask;
  236. altera_gc->irq_chip.irq_set_type = altera_gpio_irq_set_type;
  237. altera_gc->irq_chip.irq_startup = altera_gpio_irq_startup;
  238. altera_gc->irq_chip.irq_shutdown = altera_gpio_irq_mask;
  239. girq = &altera_gc->mmchip.gc.irq;
  240. girq->chip = &altera_gc->irq_chip;
  241. if (altera_gc->interrupt_trigger == IRQ_TYPE_LEVEL_HIGH)
  242. girq->parent_handler = altera_gpio_irq_leveL_high_handler;
  243. else
  244. girq->parent_handler = altera_gpio_irq_edge_handler;
  245. girq->num_parents = 1;
  246. girq->parents = devm_kcalloc(&pdev->dev, 1, sizeof(*girq->parents),
  247. GFP_KERNEL);
  248. if (!girq->parents)
  249. return -ENOMEM;
  250. girq->default_type = IRQ_TYPE_NONE;
  251. girq->handler = handle_bad_irq;
  252. girq->parents[0] = altera_gc->mapped_irq;
  253. skip_irq:
  254. ret = of_mm_gpiochip_add_data(node, &altera_gc->mmchip, altera_gc);
  255. if (ret) {
  256. dev_err(&pdev->dev, "Failed adding memory mapped gpiochip\n");
  257. return ret;
  258. }
  259. platform_set_drvdata(pdev, altera_gc);
  260. return 0;
  261. }
  262. static int altera_gpio_remove(struct platform_device *pdev)
  263. {
  264. struct altera_gpio_chip *altera_gc = platform_get_drvdata(pdev);
  265. of_mm_gpiochip_remove(&altera_gc->mmchip);
  266. return 0;
  267. }
  268. static const struct of_device_id altera_gpio_of_match[] = {
  269. { .compatible = "altr,pio-1.0", },
  270. {},
  271. };
  272. MODULE_DEVICE_TABLE(of, altera_gpio_of_match);
  273. static struct platform_driver altera_gpio_driver = {
  274. .driver = {
  275. .name = "altera_gpio",
  276. .of_match_table = of_match_ptr(altera_gpio_of_match),
  277. },
  278. .probe = altera_gpio_probe,
  279. .remove = altera_gpio_remove,
  280. };
  281. static int __init altera_gpio_init(void)
  282. {
  283. return platform_driver_register(&altera_gpio_driver);
  284. }
  285. subsys_initcall(altera_gpio_init);
  286. static void __exit altera_gpio_exit(void)
  287. {
  288. platform_driver_unregister(&altera_gpio_driver);
  289. }
  290. module_exit(altera_gpio_exit);
  291. MODULE_AUTHOR("Tien Hock Loh <thloh@altera.com>");
  292. MODULE_DESCRIPTION("Altera GPIO driver");
  293. MODULE_LICENSE("GPL");